KAE-01093-ABB-SD-FA

KAE-01093 1024 (H) x 1024 (V) Interline Transfer EMCCD Image Sensor Table 1. GENERAL SPECIFICATIONS Parameter Architecture Resolution Total Number of Pixels Number of Effective Pixels Number of Active Pixels Pixel Size Active Image Size Typical Value Interline CCD; with EMCCD 1.0 Megapixels 1064 (H) × 1064 (V) 1040 (H) × 1040 (V) 1024 (H) × 1024 (V) 9.0Ămm (H) × 9.0Ămm (V) 9.21 mm (H) × 9.21 mm (V) 13.0 mm (Diagonal) 1″ Optical Format Aspect Ratio Number of Outputs Charge Capacity − VOUT2 / VOUT3 Output Sensitivity − VOUT2 / VOUT3 Quantum Efficiency Mono (500, 850, 920 nm) / R,G,B 1:1 2, or 4 60,000 e− / 30,000 e− 16.5ĂmV/e− / 44ĂmV/e− www.onsemi.com Figure 1. KAE−01093 Interline Transfer EMCCD Image Sensor (54%, 16%, 8%) / 44%, 48%, 43% Read Noise (40 MHz) Normal Mode (1× Gain) Intra-scene Mode (20× Gain) < 20 electrons rms < 1 electron rms Features Dark Current (0°C) Photodiode, VCCD < 0.1, 8 electrons/s Dynamic Range Normal Mode (1× Gain) Intra-scene Mode (20× Gain) 69 dB 95 dB • • • • • • • Charge Transfer Efficiency Blooming Suppression Smear Image Lag Maximum Data Rate Maximum Frame Rate Normal Mode (40 MHz) Intra-scene mode (40 MHz) 2x2 binning (40 MHz) 0.999999 > 500 X −115 dB < 1 electron 40 MHz Package Cover Glass 148 pin PGA with TEC MAR, Sealed NOTE: • Increased QE, with 2× Improvement at 91 fps (quad), 52 fps (dual) 91 fps (quad), 52 fps (dual) 144 fps (quad), 91 fps (dual) All Parameters are specified at T = 0°C unless otherwise noted. 820 nm 91 fps (4 Outputs); 144 fps (Binned) Intra-scene Switchable Gain Wide Dynamic Range Low Noise Architecture Exceptional Low Light Imaging Global Shutter Excellent Image Uniformity and MTF Applications • • • • Surveillance Scientific Imaging Medical Imaging Situational Awareness (Ground Vehicles) Description The KAE−01093 Image Sensor is a 1 megapixel 1024 × 1024 CCD in a 1″ optical format that provides enhanced Quantum Efficiency (particularly for NIR wavelengths) without a decrease in Modulation Transfer Function (MTF). In quad mode, the KAE−01093 runs at 91 fps. Each of the sensor’s four outputs incorporate both a conventional horizontal CCD register and a high gain EMCCD register. An intra-scene switchable gain feature samples each charge packet on a pixel-by-pixel basis. This enables the camera system to determine whether the charge will be routed through the normal gain output or the EMCCD output based on a user selectable threshold. Cameras can thus image in extreme low light even when bright objects are within a dark scene, allowing a single camera to capture quality images from sunlight to starlight. © Semiconductor Components Industries, LLC, 2018 August, 2019 − Rev. 0 1 ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Publication Order Number: KAE−01093/D KAE−01093 ORDERING INFORMATION US export controls apply to all shipments of this product designated for destinations outside of the US and Canada, requiring ON Semiconductor to obtain an export license from the US Department of Commerce before image sensors or evaluation kits can be exported. Table 2. ORDERING INFORMATION − KAE−01093 IMAGE SENSOR Description Marking Code KAE−01093−ABB−SD−FA Part Number Monochrome, Microlens, PGA Package, TEC, Sealed MAR Cover Glass, Standard Grade KAE−01093−ABB Serial Number KAE−01093−ABB−SD−EE Monochrome, Microlens, PGA Package, TEC, Sealed MAR Cover Glass, Engineering Grade KAE−01093−FBB−SD−FA Gen2 Color (Bayer RGB), Microlens, PGA Package, TEC, Sealed MAR Cover Glass, Standard Grade KAE−01093−FBB−SD−EE Gen2 Color (Bayer RGB), Microlens, PGA Package, TEC, Sealed MAR Cover Glass, Engineering Grade KAE−01093−QBB−SD−FA Gen2 Color (Sparse CFA), Microlens, PGA Package, TEC, Sealed MAR Cover Glass, Standard Grade KAE−01093−QBB−SD−EE Gen2 Color (Sparse CFA), Microlens, PGA Package, TEC, Sealed MAR Cover Glass, Engineering Grade KAE−01093−FBB Serial Number KAE−01093−QBB Serial Number See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. Warning Please address all inquiries and purchase orders to: The KAE−01093−ABB−SD and KAE−01093−FBB−SD, and KAE−01093−QBB−SD packages have an integrated thermoelectric cooler (TEC) and have epoxy sealed cover glass. The seal formed is non-hermetic, and may allow moisture ingress over time, depending on the storage environment. As a result, care must be taken to avoid cooling the device below the dew point inside the package cavity, since this may result in condensation on the sensor. For all KAE−01093 configurations, no warranty, expressed or implied, covers condensation. ON Semiconductor 1964 Lake Avenue Rochester, New York 14615 Phone: (585) 784−5500 ON Semiconductor reserves the right to change any information contained herein without notice. All information furnished by ON Semiconductor is believed to be accurate. www.onsemi.com 2 KAE−01093 DEVICE DESCRIPTION Architecture Quadrant c Quadrant d Quadrant a Quadrant b Figure 2. Block Diagram Dark Reference Pixels Image Acquisition There are 12 dark reference rows at the top and bottom of the image sensor, as well as 12 dark reference columns on the left and right sides. However, the rows and columns at the perimeter edges should not be included in acquiring a dark reference signal, since they may be subject to some light leakage. An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photo-site. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. Active Buffer Pixels 8 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. These pixels are light sensitive but are not tested for defects and non-uniformities. www.onsemi.com 3 KAE−01093 24 Figure 3. Bayer Color Filter Pattern Sparse Color Filter Pattern 24 Figure 4. Sparse Color Filter Pattern www.onsemi.com 4 KAE−01093 Physical Description Pin Grid Array Configuration Figure 5. PGA Package Pin Designations (Bottom View) Table 3. PIN DESCRIPTION Pin No. Label A3 VDD2a A4 H2SW3a HCCD Output 3 Selector, Quadrant a A5 RG23a Amplifier 2 and 3 Reset, Quadrant a A6 VDD3a Amplifier 3 Supply, Quadrant a A7 H1BEMa EMCCD Barrier Phase 1, Quadrant a A8 H2SEMa EMCCD Storage Phase 2, Quadrant a A9 H2a A10 H1Sa HCCD Storage Phase 1, Quadrant a A11 H2Ba HCCD Barrier Phase 2, Quadrant a A12 H3Ba HCCD Barrier Phase 3, Quadrant a A13 H3Bb HCCD Barrier Phase 3, Quadrant b A14 H2Bb HCCD Barrier Phase 2, Quadrant b A15 H1Sb HCCD Storage Phase 1, Quadrant b A16 H2b Description Amplifier 2 Supply, Quadrant a HCCD Phase 2, Quadrant a HCCD Phase 2, Quadrant b www.onsemi.com 5 KAE−01093 Table 3. PIN DESCRIPTION (continued) Pin No. Label Description A17 H2SEMb EMCCD Storage Multiplier Phase 2, Quadrant b A18 H1BEMb EMCCD Barrier Phase 1, Quadrant b A19 VDD3b Amplifier 3 Supply, Quadrant b A20 RG23b Amplifier 2 and 3 Reset, Quadrant b A21 H2SW3b HCCD Output 3 Selector, Quadrant b A22 VDD2b B2 VOUT1a B3 H2Xa B4 H2SW2a B5 H2La B6 VOUT3a Video Output 3, Quadrant a B7 H1SEMa EMCCD Storage Multiplier Phase 1, Quadrant a B8 H2BEMa EMCCD Barrier Phase 1, Quadrant a B9 H1a B10 H2Sa HCCD Storage Phase 2, Quadrant a B11 H3Sa HCCD Storage Phase 3, Quadrant a B12 H1Ba HCCD Barrier Phase 1, Quadrant a B13 H1Bb HCCD Barrier Phase 1, Quadrant b B14 H3Sb HCCD Storage Phase 3, Quadrant b B15 H2Sb HCCD Storage Phase 2, Quadrant b B16 H1b B17 H2BEMb EMCCD Barrier Phase 2, Quadrant b B18 H1SEMb EMCCD Storage Multiplier Phase 1, Quadrant b B19 VOUT3b Video Output 3, Quadrant b B20 H2Lb B21 H2SW2b B22 H2Xb B23 VOUT1b C1 V3B C2 VDD1a Amplifier 1 Supply, Quadrant a C3 RG1a Amplifier 1 Reset, Quadrant a C4 VOUT2a Video Output 2, Quadrant a C21 VOUT2b Video Output 2, Quadrant b C22 RG1b Amplifier 1 Reset, Quadrant b C23 VDD1b Amplifier 1 Supply, Quadrant b C24 V3B VCCD Bottom Phase 3 D1 V2B VCCD Bottom Phase 2 D2 OG1a Output 1 Gate, Quadrant a D3 VSS1a Amplifier 1 Return, Quadrant a Amplifier 2 Supply, Quadrant b Video Output 1, Quadrant a Floating Gate Exit HCCD Gate, Quadrant a HCCD Output 2 Selector, Quadrant a HCCD Last Gate, Outputs 1, 2 and 3, Quadrant a HCCD Phase 1, Quadrant a HCCD Phase 1, Quadrant b HCCD Last Gate, Outputs 1, 2 and 3, Quadrant b HCCD Output 2 Selector, Quadrant b Floating Gate Exit HCCD Gate, Quadrant b Video Output 1, Quadrant b VCCD Bottom Phase 3 www.onsemi.com 6 KAE−01093 Table 3. PIN DESCRIPTION (continued) Pin No. Label Description D22 VSS1b Amplifier 1 Return, Quadrant b D23 OG1b Output 1 Gate, Quadrant b D24 V2B VCCD Bottom Phase 2 E1 V1B VCCD Bottom Phase 1 E2 V4B VCCD Bottom Phase 4 E3 ESD ESD Protection Disable E22 ESD ESD Protection Disable E23 V4B VCCD Bottom Phase 4 E24 V1B VCCD Bottom Phase 1 F1 GND Ground F2 GND Ground F3 GND Ground F22 GND Ground F23 GND Ground F24 GND Ground G1 VDD15 G2 SUBREF Substrate Voltage Reference G3 THERM2 Thermistor Terminal 2 G22 TEC− Thermal Electric Cooler Negative Terminal G23 TEC− Thermal Electric Cooler Negative Terminal G24 TEC− Thermal Electric Cooler Negative Terminal H1 SUB Substrate H2 SUB Substrate H3 THERM1 H22 TEC+ Thermal Electric Cooler Positive Terminal H23 TEC+ Thermal Electric Cooler Positive Terminal H24 TEC+ Thermal Electric Cooler Positive Terminal I1 GND Ground I2 GND Ground I22 GND Ground I23 GND Ground I24 GND Ground J1 V1T VCCD Top Phase 1 J2 V4T VCCD Top Phase 4 J3 ID J22 VDD15 J23 V4T VCCD Top Phase 4 J24 V1T VCCD Top Phase 1 K1 V2T VCCD Top Phase 2 +15 V Supply Thermistor Terminal 1 Device ID +15 V Supply www.onsemi.com 7 KAE−01093 Table 3. PIN DESCRIPTION (continued) Pin No. Label Description K2 OG1c Output 1 Gate, Quadrant c K3 VSS1c Amplifier 1 Return, Quadrant c K22 VSS1d Amplifier 1 Return, Quadrant d K23 OG1d Output 1 Gate, Quadrant d K24 V2T VCCD Top Phase 2 L1 V3T VCCD Top Phase 3 L2 VDD1c Amplifier 1 Supply, Quadrant c L3 RG1c Amplifier 1 Reset, Quadrant c L4 VOUT2c Video Output 2, Quadrant c L21 VOUT2d Video Output 2, Quadrant d L22 RG1d Amplifier 1 Reset, Quadrant d L23 VDD1d Amplifier 1 Supply, Quadrant d L24 V3T M2 VOUT1c M3 H2Xc M4 H2SW2c M5 H2Lc M6 VOUT3c Video Output 3, Quadrant c M7 H1SEMc EMCCD Storage Multiplier Phase 1, Quadrant c M8 H2BEMc EMCCD Barrier Phase 2, Quadrant c M9 H1c M10 H2Sc HCCD Storage Phase 2, Quadrant c M11 H3Sc HCCD Storage Phase 3, Quadrant c M12 H1Bc HCCD Barrier Phase 1, Quadrant c M13 H1Bd HCCD Barrier Phase 1, Quadrant d M14 H3Sd HCCD Storage Phase 3, Quadrant d M15 H2Sd HCCD Storage Phase 2, Quadrant d M16 H1d M17 H2BEMd EMCCD Barrier Phase 2, Quadrant d M18 H1SEMd EMCCD Storage Multiplier Phase 1, Quadrant d M19 VOUT3d Video Output 3, Quadrant d M20 H2Ld M21 H2SW2d M22 H2Xd M23 VOUT1d N3 VDD2c N4 H2SW3c HCCD Output 3 Selector, Quadrant c N5 RG23c Amplifier 2 and 3 Reset, Quadrant c N6 VDD3c Amplifier 3 Supply, Quadrant c VCCD Top Phase 3 Video Output 1, Quadrant c Floating Gate Exit HCCD Gate, Quadrant c HCCD Output 2 Selector, Quadrant c HCCD Last Gate, Outputs 1, 2 and 3, Quadrant c HCCD Phase 1, Quadrant c HCCD Phase 1, Quadrant d HCCD Last Gate, Outputs 1, 2 and 3, Quadrant d HCCD Output 2 Selector, Quadrant d Floating Gate Exit HCCD Gate, Quadrant d Video Output 1, Quadrant d Amplifier 2 Supply, Quadrant c www.onsemi.com 8 KAE−01093 Table 3. PIN DESCRIPTION (continued) NOTE: Pin No. Label Description N7 H1BEMc EMCCD Barrier Phase 1, Quadrant c N8 H2SEMc EMCCD Storage Multiplier Phase 2, Quadrant c N9 H2c N10 H1Sc HCCD Storage Phase 1, Quadrant c N11 H2Bc HCCD Barrier Phase 2, Quadrant c N12 H3Bc HCCD Barrier Phase 3, Quadrant c N13 H3Bd HCCD Barrier Phase 3, Quadrant d N14 H2Bd HCCD Barrier Phase 2, Quadrant d N15 H1Sd HCCD Storage Phase 1, Quadrant d N16 H2d N17 H2SEMd EMCCD Storage Multiplier Phase 2, Quadrant d N18 H1BEMd EMCCD Barrier Phase 1, Quadrant d N19 VDD3d Amplifier 3 Supply, Quadrant d N20 RG23d Amplifier 2 and 3 Reset, Quadrant d N21 H2SW3d HCCD Output 3 Selector, Quadrant d N22 VDD2d HCCD Phase 2, Quadrant c HCCD Phase 2, Quadrant d Amplifier 2 Supply, Quadrant d Pin No. I3 is connected to the heat sink. Imaging Performance Table 4. TYPICAL OPERATION CONDITIONS (Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions) Condition Description Light Source (Note 1) Continuous Red, Green, Blue, and IR LED Illumination Operation Nominal Operating Voltages and Timing Temperature 0°C 1. For monochrome sensor, only green and IR LED illumination is used. Table 5. PERFORMANCE PARAMETERS (Performance parameters are evaluated at initial design validation.) (Note 5) Symbol Nom Unit NL 2 % Maximum Gain Difference Between Outputs (EMCCD gain = 1) (Note 4) DG 10 % Maximum Signal Error due to Non-linearity Differences (EMCCD gain = 1) (Note 1) DNL 1 % Photodiode Dark Current (Average) IPD 0.1 e/p/s 8 e/p/s e− Description Maximum Photoresponse Non-linearity (EMCCD gain = 1) (Note 1) Vertical CCD Dark Current Image Lag Lag