KAE-02152-FBB-SD-FA

KAE-02152 1920 (H) x 1080 (V) Interline CCD Image Sensor The KAE−02152 image sensor is a 1080p, 2/3” format Interline Transfer EMCCD that provides increased Quantum Efficiency (particularly for NIR wavelengths) without a decrease in Modulation Transfer Function (MTF) when compared to the KAE−02150. Each of the sensor’s four outputs includes both a conventional horizontal CCD register and a high gain EMCCD register. An intra−scene switchable gain feature samples each charge packet on a pixel−by−pixel basis, enabling the camera system to determine whether the charge will be routed through the normal gain output or the EMCCD output based on a user selectable threshold. This feature enables imaging in extreme low light even when bright objects are within a dark scene, allowing a single camera to capture quality images from sunlight to starlight. The device is available in two package configurations: PGA, and PGA with integrated thermoelectric cooler (TEC). www.onsemi.com Figure 1. KAE−02152 Interline CCD Image Sensor Table 1. GENERAL SPECIFICATIONS Parameter Architecture Total Number of Pixels Number of Effective Pixels Number of Active Pixels Pixel Size Active Image Size Aspect Ratio Number of Outputs Charge Capacity Output Sensitivity Quantum Efficiency Peak Mono/Color (RGB) 850 nm 920 nm Read Noise (20 MHz) Normal Mode (1× Gain) Intra-Scene Mode (20× Gain) Dark Current (0°C) Photodiode, VCCD Dynamic Range Normal Mode (1× Gain) Intra-Scene Mode (20× Gain) Charge Transfer Efficiency Blooming Suppression Smear Image Lag Maximum Pixel Clock Speed Maximum Frame Rate Normal Mode, Intra-Scene Mode Typical Value Interline CCD; with EMCCD 1984 (H) × 1124 (V) 1936 (H) × 1096 (V) 1920 (H) × 1080 (V) 5.5 mm (H) × 5.5 mm (V) 10.56 mm (H) × 5.94 mm (V) 12.1 mm (Diag.), 2/3″ Optical Format 16:9 1, 2, or 4 20,000 e− 44 mV/e− 51% / 44% / 45% / 41% 16% 8% 9 e− rms < 1 e− rms ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Features • Increased QE, with 2x Improvement at • • • • • • • • 820 nm Intra-Scene Switchable Gain Wide Dynamic Range Low Noise Architecture Exceptional Low Light Imaging Global Shutter Excellent Image Uniformity and MTF Bayer Color Pattern and Monochrome PGA, or PGA with integrated TEC Applications < 0.1 e−/s, 6 e−/s • • • • 68 dB 86 dB 0.999999 > 1000 X −100 dB < 1 e− 40 MHz Surveillance Scientific Imaging Medical Imaging Intelligent Transportation 60 fps (40 MHz), 30 fps (20 MHz) Package 135 pin PGA 143 pin PGA with TEC Cover Glass Clear Glass, Taped MAR Glass, Sealed (with TEC only) NOTE: All Parameters are specified at T = 0°C unless otherwise noted. © Semiconductor Components Industries, LLC, 2017 January, 2018 − Rev. 1 1 Publication Order Number: KAE−02152/D KAE−02152 ORDERING INFORMATION US export controls apply to all shipments of this product designated for destinations outside of the US and Canada, requiring ON Semiconductor to obtain an export license from the US Department of Commerce before image sensors or evaluation kits can be exported. Table 2. ORDERING INFORMATION Part Number Description KAE−02152−ABB−JP−FA Monochrome, Microlens, PGA Package, Taped Clear Cover Glass (No Coatings), Standard Grade KAE−02152−ABB−JP−EE Monochrome, Microlens, PGA Package, Taped Clear Cover Glass (No Coatings), Engineering Grade KAE−02152−FBB−JP−FA Gen2 Color (Bayer RGB), Microlens, PGA Package, Taped Clear Cover Glass (No Coatings), Standard Grade KAE−02152−FBB−JP−EE Gen2 Color (Bayer RGB), Microlens, PGA Package, Taped Clear Cover Glass (No Coatings), Engineering Grade KAE−02152−ABB−SD−FA Monochrome, Microlens, PGA Package with Integrated TEC, Sealed Clear Cover Glass with AR Coating (both sides), Standard Grade KAE−02152−ABB−SD−EE Monochrome, Microlens, PGA Package with Integrated TEC, Sealed Clear Cover Glass with AR Coating (both sides), Engineering Grade KAE−02152−FBB−SD−FA Gen2 Color (Bayer RGB), Microlens, PGA Package with Integrated TEC, Sealed Clear Cover Glass with AR Coating (both sides), Standard Grade KAE−02152−FBB−SD−EE Gen2 Color (Bayer RGB), Microlens, PGA Package with Integrated TEC, Sealed Clear Cover Glass with AR Coating (both sides), Engineering Grade KAE−02152−ABB−SP−FA Monochrome, Microlens, PGA Package with integrated TEC, Taped Clear Cover Glass (No Coatings), Standard Grade KAE−02152−ABB−SP−EE Monochrome, Microlens, PGA Package with integrated TEC, Taped Clear Cover Glass (No Coatings), Engineering Grade KAE−02152−FBB−SP−FA Gen2 Color (Bayer RGB), Microlens, PGA Package with integrated TEC, Taped Clear Cover Glass (No Coatings), Standard Grade KAE−02152−FBB−SP−EE Gen2 Color (Bayer RGB), Microlens, PGA Package with integrated TEC, Taped Clear Cover Glass (No Coatings), Engineering Grade KAE−02152−QBB−SD−FA Gen2 Color (Sparse CFA), Microlens, PGA Package with integrated TEC, Sealed Clear Cover Glass with AR Coating (both sides), Standard Grade KAE−02152−QBB−SD−EE Gen2 Color (Sparse CFA), Microlens, PGA Package with integrated TEC, Sealed Clear Cover Glass with AR Coating (both sides), Engineering Grade www.onsemi.com 2 Marking Code KAE−02152−ABB Serial Number KAE−02152−FBB Serial Number KAE−02152−ABB Serial Number KAE−02152−FBB Serial Number KAE−02152−ABB Serial Number KAE−02152−FBB Serial Number KAE−02152−QBB Serial Number KAE−02152 Table 3. EVALUATION SUPPORT Part Number Description G3−FPGA−BD−A−GEVK Evaluation Board KAE−S1−J−HEAD−BD−A−GEVK PGA Package Head Board KAE−S1−S−HEAD−BD−A−GEVK PGA Package with Integrated TEC Head Board LENS−MOUNT−KIT−D−GEVK Lens Mount Kit for IT−CCD Evaluation Hardware KAE−02152−AB−SD−A−GEVK Full Evaluation Kit. Includes Image Sensor KAE−02152−ABB−SD−FA KAE−02152−FB−SD−A−GEVK Full Evaluation Kit. Includes Image Sensor KAE−02152−FBB−SD−FA KAE−02152−QB−SD−A−GEVK Full Evaluation Kit. Includes Image Sensor KAE−02152−QBB−SD−FA See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. Warning The KAE−02152−ABB−SD, KAE−02152−FBB−SD and KAE−02152−QBB−SD packages have an integrated thermoelectric cooler (TEC) and have epoxy sealed cover glass. The seal formed is non−hermetic, and may allow moisture ingress over time, depending on the storage environment. As a result, care must be taken to avoid cooling the device below the dew point inside the package cavity, since this may result in condensation on the sensor. For all KAE−02152 configurations, no warranty, expressed or implied, covers condensation. www.onsemi.com 3 KAE−02152 DEVICE DESCRIPTION Architecture VOUTC3 VOUTD3 2072 1 28 1 10 2072 24 8 960 960 8 24 10 1 28 4 1 4 14 VOUTD2 8 24 VOUTB2 VOUTA1 VOUTA2 VOUTD1 1920 y 1080 5.5 mm Pixels 24 8 VOUTB1 VOUTC2 VOUTC1 8 8 14 4 1 4 28 1 10 24 8 2072 960 960 2070 8 24 2070 VOUTA3 10 1 28 1 2072 VOUTB3 Figure 2. Block Diagram Dark Reference Pixels electron-hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photo-site. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming There are 14 dark reference rows at the top and bottom of the image sensor, as well as 24 dark reference columns on the left and right sides. However, the rows and columns at the very edges should not be included in acquiring a dark reference signal, since they may be subject to some light leakage. Active Buffer Pixels 8 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. These pixels are light sensitive but are not tested for defects and non-uniformities. ESD Protection Adherence to the power-up and power-down sequence is critical. Failure to follow the proper power-up and power-down sequences may cause damage to the sensor. See Power-Up and Power-Down Sequence section. Image Acquisition An electronic representation of an image is formed when incident photons falling on the sensor plane create www.onsemi.com 4 KAE−02152 Bayer Color Filter Pattern VOUTC3 VOUTD3 2072 1 28 1 10 2072 24 8 960 960 8 24 10 1 28 4 1 4 14 VOUTD2 8 24 VOUTB2 VOUTA1 VOUTA2 VOUTD1 1920 y 1080 5.5 mm Pixels 24 8 VOUTB1 VOUTC2 VOUTC1 8 8 14 4 1 4 28 1 10 24 8 2072 960 960 2070 8 24 2070 VOUTA3 VOUTB3 Figure 3. Bayer Color Filter Pattern www.onsemi.com 5 2072 10 1 28 1 KAE−02152 Sparse Color Filter Pattern VOUTC3 VOUTD3 2072 1 28 1 10 2072 24 8 960 960 8 24 10 1 28 4 1 4 VOUTD2 8 24 G PRP PGP R B PGP P B PG 8 VOUTB2 G PRP PGP R BPGP PB PG VOUTA1 VOUTA2 G PRP PGP R B PGP P B PG 1920 y 1080 5.5 mm Pixels 24 8 VOUTD1 8 G PRP PGP R BPGP PB PG VOUTB1 VOUTC2 VOUTC1 14 14 4 1 4 28 1 10 24 8 2072 960 960 2070 8 24 2070 VOUTA3 VOUTB3 Figure 4. Sparse Color Filter Pattern www.onsemi.com 6 2072 10 1 28 1 KAE−02152 Physical Description Pin Grid Array and Pin Description H G F E D C B A 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 5. PGA Package Designations (Bottom View) Table 4. PIN DESCRIPTION Pin Label A02 V3B VCCD Bottom Phase 3 A03 N/C No Connection A04 RG2a A05 N/C A06 VDD23ab Amplifier 2 and 3 Supply, Quadrants A, B A07 H1BEMa EMCCD Barrier Phase 1, Quadrant A A08 H2Ba HCCD Barrier Phase 2, Quadrant A A09 GND Ground A10 H2Bb HCCD Barrier Phase 2, Quadrant B A11 H1BEMb EMCCD barrier phase 1, Quadrant B A12 VDD23ab Amplifier 2 and 3 Supply, Quadrants A, B A13 N/C A14 RG2a Description Amplifier 2 Reset, Quadrant A No Connection No Connection Amplifier 2 Reset, Quadrant B A15 N/C No Connection A16 V3B VCCD Bottom Phase 3 A17 ESD ESD Protection Disable B01 DEVID B02 V4B B03 VOUT1a Device ID Resistor VCCD Bottom Phase 4 Amplifier 1 Output, Quadrant A www.onsemi.com 7 KAE−02152 Table 4. PIN DESCRIPTION (continued) Pin Label Description B04 VOUT2a Video Output 2, Quadrant A B05 H2SW3a HCCD Output 3 Selector, Quadrant A B06 VOUT3a Video Output 3, Quadrant A B07 H2BEMa EMCCD Barrier Phase 2, Quadrant A B08 H1Ba HCCD Barrier Phase 1, Quadrant A B09 GND Ground B10 H1Bb HCCD Barrier Phase 1, Quadrant B B11 H2BEMb EMCCD Barrier Phase 2, Quadrant B B12 VOUT3b Video Output 3, Quadrant B B13 H2SW3b HCCD Output 3 Selector, Quadrant B B14 VOUT2b Video Output 2, Quadrant B B15 VOUT1b Amplifier 1 Output, Quadrant B B16 V4B VCCD Bottom Phase 4 B17 SUB Substrate C01 V1B VCCD Bottom Phase 1 C02 N/C No Connection C03 VSS1a C04 VDD23ab Amplifier 1 Return, Quadrant A Amplifier 2 and 3 Supply, Quadrants A, B C05 H2SW2a HCCD Output 2 Selector, Quadrant A C06 N/C C07 H1SEMa C08 H2Sa HCCD Storage Phase 2, Quadrant A C09 GND Ground C10 H2Sb HCCD Storage Phase 2, Quadrant B C11 H1SEMb No Connection EMCCD Storage Multiplier Phase 1, Quadrant A EMCCD Storage Multiplier Phase 1, Quadrant B C12 N/C C13 H2SW2b No Connection HCCD Output 2 Selector, Quadrant B C14 VDD23ab Amplifier 2 and 3 Supply, Quadrants A, B C15 VSS1b Amplifier 1 Return, Quadrant B C16 N/C No Connection C17 V1B VCCD Bottom Phase 1 D01 V2B VCCD Bottom Phase 2 D02 VDD1a Amplifier 1 Supply, Quadrant A D03 RG1a Amplifier 1 Reset, Quadrant A D04 H2Xa Floating Gate Exit HCCD Gate, Quadrant A D05 H2La HCCD Last Gate, Outputs 1, 2 and 3, Quadrant A D06 RG3a Amplifier 3 Reset, Quadrant A D07 H2SEMa D08 H1Sa HCCD Storage Phase 1, Quadrant A D09 GND Ground D10 H1Sb HCCD Storage Phase 1, Quadrant B D11 H2SEMb D12 RG3b Amplifier 3 Reset, Quadrant B D13 H2Lb HCCD Last Gate, Outputs 1, 2 and 3, Quadrant B D14 H2Xb Floating Gate Exit HCCD Gate, Quadrant B EMCCD Storage Multiplier Phase 2, Quadrant A EMCCD Storage Multiplier Phase 2, Quadrant B www.onsemi.com 8 KAE−02152 Table 4. PIN DESCRIPTION (continued) Pin Label Description D15 RG1b Amplifier 1 Reset, Quadrant B D16 VDD1b Amplifier 1 Supply, Quadrant B D17 V2B VCCD Bottom Phase 2 E01 V2T VCCD Top Phase 2 E02 VDD1c Amplifier 1 Supply, Quadrant C E03 RG1c Amplifier 1 Reset, Quadrant C E04 H2Xc Floating Gate Exit HCCD Gate, Quadrant C E05 H2Lc HCCD Last Gate, Outputs 1, 2 and 3, Quadrant C E06 RG3c Amplifier 3 Reset, Quadrant C E07 H2SEMc E08 H1Sc HCCD Storage Phase 1, Quadrant C E09 GND Ground E10 H1Sd HCCD Storage Phase 1, Quadrant D E11 H2SEMd E12 RG3d Amplifier 3 Reset, Quadrant D E13 H2Ld HCCD Last Gate, Outputs 1, 2 and 3, Quadrant D E14 H2Xd Floating Gate Exit HCCD Gate, Quadrant D E15 RG1d Amplifier 1 Reset, Quadrant D E16 VDD1d Amplifier 1 Supply, Quadrant D E17 V2T VCCD Top Phase 2 F01 V1T VCCD Top Phase 1 F02 N/C No Connection EMCCD Storage Multiplier Phase 2, Quadrant C EMCCD Storage Multiplier Phase 2, Quadrant D F03 VSS1c F04 VDD23cd Amplifier 1 Return, Quadrant C Amplifier 2 and 3 Supply, Quadrants C, D F05 H2SW2c HCCD Output 2 Selector, Quadrant C F06 N/C F07 H1SEMc No Connection F08 H2Sc HCCD Storage Phase 2, Quadrant C F09 GND Ground F10 H2Sd HCCD Storage Phase 2, Quadrant D F11 H1SEMd EMCCD Storage Multiplier Phase 1, Quadrant C EMCCD Storage Multiplier Phase 1, Quadrant D F12 N/C F13 H2SW2d No Connection HCCD Output 2 Selector, Quadrant D F14 VDD23cd Amplifier 2 and 3 Supply, Quadrants C, D F15 VSS1d Amplifier 1 Return, Quadrant D F16 N/C No Connection F17 V1T VCCD Top Phase 1 G01 ESD ESD Protection Disable G02 V4T VCCD Top Phase 4 G03 VOUT1c Amplifier 1 Output, Quadrant C G04 VOUT2c Video Output 2, Quadrant C G05 H2SW3c HCCD Output 3 Selector, Quadrant C G06 VOUT3c Video Output 3, Quadrant C G07 H2BEMc EMCCD Barrier Phase 2, Quadrant C G08 H1Bc HCCD Barrier Phase 1, Quadrant C www.onsemi.com 9 KAE−02152 Table 4. PIN DESCRIPTION (continued) Pin Label Description G09 GND Ground G10 H1Bd HCCD Barrier Phase 1, Quadrant D G11 H2BEMd EMCCD Barrier Phase 2, Quadrant D G12 VOUT3d Video Output 3, Quadrant D G13 H2SW3d HCCD Output 3 Selector, Quadrant D G14 VOUT2d Video Output 2, Quadrant D G15 VOUT1d Amplifier 1 Output, Quadrant D G16 V4T VCCD Top Phase 4 G17 SUB Substrate H01 GND Ground H02 V3T VCCD Top Phase 3 H03 N/C No Connection H04 RG2c H05 N/C H06 VDD23cd Amplifier 2 and 3 Supply, Quadrants C, D H07 H1BEMc EMCCD Barrier Phase 1, Quadrant C H08 H2Bc HCCD Barrier Phase 2, Quadrant C H09 GND Ground H10 H2Bd HCCD Barrier Phase 2, Quadrant D H11 H1BEMd EMCCD Barrier Phase 1, Quadrant D H12 VDD23cd Amplifier 2 and 3 Supply, Quadrants C, D H13 N/C H14 RG2d H15 N/C No Connection H16 V3T VCCD Top Phase 3 H17 SUBREF Amplifier 2 Reset, Quadrant C No Connection No Connection Amplifier 2 Reset, Quadrant D Substrate Voltage Reference www.onsemi.com 10 KAE−02152 PGA with Integrated TEC Pin Description and Device Orientation 18 17 16 15 14 13 12 11 10 9 D C B A 6 5 4 3 2 1 ÏÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏ ÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏ ÏÏÏ Ï ÏÏÏ ÏÏ ÏÏ Ï ÏÏ ÏÏ Ï Ï ÏÏ ÏÏ Ï Ï ÏÏ ÏÏ Ï ÏÏ ÏÏ Ï ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏ ÏÏÏ ÏÏ ÏÏ ÏÏÏ ÏÏÏ ÏÏÏ Ï ÏÏÏÏÏ ÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏ H G F 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 E S/N F E 7 S/N H G 8 D C B A 1 Figure 6. PGA with TEC Pin Descriptions − Bottom View Table 5. PGA WITH INTEGRATED TEC PIN DESCRIPTION Pin Label A02 V3B Description A03 NTC1 Negative Temperature Coefficient Thermistor Terminal 1 A04 RG2a Amplifier 2 Reset, Quadrant A A05 NTC2 Negative Temperature Coefficient Thermistor Terminal 2 A06 VDD23ab Amplifier 2 And 3 Supply, Quadrants A, B A07 H1BEMa EMCCD Barrier Phase 1, Quadrant A A08 H2Ba HCCD Barrier Phase 2, Quadrant A A09 GND Ground A10 H2Bb HCCD Barrier Phase 2, Quadrant B A11 H1BEMb EMCCD Barrier Phase 1, Quadrant B A12 VDD23ab Amplifier 2 And 3 Supply, Quadrants A, B VCCD Bottom Phase 3 A13 N/C A14 RG2b No Connect A15 N/C No Connection A16 V3B VCCD Bottom Phase 3 A17 ESD ESD Protection Disable A18 TEC− Thermal Electric Cooler Negative Terminal B01 DEVID Device ID Resistor B02 V4B Amplifier 2 Reset, Quadrant B VCCD Bottom Phase 4 www.onsemi.com 11 KAE−02152 Table 5. PGA WITH INTEGRATED TEC PIN DESCRIPTION (continued) Pin Label Description B03 VOUT1a Amplifier 1 Output, Quadrant A B04 VOUT2a Video Output 2, Quadrant A B05 H2SW3a HCCD Output 3 Selector, Quadrant A B06 VOUT3a Video Output 3, Quadrant A B07 H2BEMa EMCCD Barrier Phase 2, Quadrant A B08 H1Ba HCCD Barrier Phase 1, Quadrant A B09 GND Ground B10 H1Bb HCCD Barrier Phase 1, Quadrant B B11 H2BEMb EMCCD Barrier Phase 2, Quadrant B B12 VOUT3b Video Output 3, Quadrant B B13 H2SW3b HCCD Output 3 Selector, Quadrant B B14 VOUT2b Video Output 2, Quadrant B B15 VOUT1b Amplifier 1 Output, Quadrant B B16 V4B VCCD Bottom Phase 4 B17 SUB Substrate B18 TEC− Thermal Electric Cooler Negative Terminal C01 V1B VCCD Bottom Phase 1 C02 N/C No Connection C03 VSS1a C04 VDD23ab Amplifier 2 And 3 Supply, Quadrants A, B C05 H2SW2a HCCD Output 2 Selector, Quadrant A C06 N/C C07 H1SEMa C08 H2Sa HCCD Storage Phase 2, Quadrant A C09 GND Ground C10 H2Sb HCCD Storage Phase 2, Quadrant B C11 H1SEMb C12 N/C C13 H2SW2b HCCD Output 2 Selector, Quadrant B C14 VDD23ab Amplifier 2 And 3 Supply, Quadrants A, B C15 VSS1b C16 N/C No Connection C17 V1B VCCD Bottom Phase 1 C18 TEC− D01 V2B D02 VDD1a Amplifier 1 Supply, Quadrant A D03 RG1a Amplifier 1 Reset, Quadrant A D04 H2Xa Floating Gate Exit HCCD Gate, Quadrant A D05 H2La HCCD Last Gate, Outputs 1,2 And 3, Quadrant A D06 RG3a Amplifier 3 Reset, Quadrant A D07 H2SEMa D08 H1Sa Amplifier 1 Return, Quadrant A No Connection EMCCD Storage Multiplier Phase 1, Quadrant A EMCCD Storage Multiplier Phase 1, Quadrant B No Connection Amplifier 1 Return, Quadrant B Thermal Electric Cooler Negative Terminal VCCD Bottom Phase 2 EMCCD Storage Multiplier Phase 2, Quadrant A HCCD Storage Phase 1, Quadrant A www.onsemi.com 12 KAE−02152 Table 5. PGA WITH INTEGRATED TEC PIN DESCRIPTION (continued) Pin Label Description D09 GND Ground D10 H1Sb HCCD Storage Phase 1, Quadrant B D11 H2SEMb D12 RG3b Amplifier 3 Reset, Quadrant B D13 H2Lb HCCD Last Gate, Outputs 1,2 And 3, Quadrant B D14 H2Xb Floating Gate Exit HCCD Gate, Quadrant B D15 RG1b Amplifier 1 Reset, Quadrant B D16 VDD1b Amplifier 1 Supply, Quadrant B D17 V2B D18 TEC− E01 V2T E02 VDD1c Amplifier 1 Supply, Quadrant C E03 RG1c Amplifier 1 Reset, Quadrant C E04 H2Xc Floating Gate Exit HCCD Gate, Quadrant C E05 H2Lc HCCD Last Gate, Outputs 1,2 And 3, Quadrant C E06 RG3c Amplifier 3 Reset, Quadrant C E07 H2SEMc E08 H1Sc HCCD Storage Phase 1, Quadrant C E09 GND Ground E10 H1Sd HCCD Storage Phase 1, Quadrant D E11 H2SEMd E12 RG3d Amplifier 3 Reset, Quadrant B E13 H2Ld HCCD Last Gate, Outputs 1,2 And 3, Quadrant D E14 H2Xd Floating Gate Exit HCCD Gate, Quadrant D E15 RG1d Amplifier 1 Reset, Quadrant D E16 VDD1d Amplifier 1 Supply, Quadrant D E17 V2T E18 TEC+ F01 V1T VCCD Top Phase 1 F02 N/C No Connection F03 VSS1c F04 VDD23cd Amplifier 2 And 3 Supply, Quadrants C, D F05 H2SW2c HCCD Output 2 Selector, Quadrant C F06 N/C F07 H1SEMc F08 H2Sc HCCD Storage Phase 2, Quadrant C F09 GND Ground F10 H2Sd HCCD Storage Phase 2, Quadrant D F11 H1SEMd F12 N/C F13 H2SW2d HCCD Output 2 Selector, Quadrant D F14 VDD23cd Amplifier 2 And 3 Supply, Quadrants C, D EMCCD Storage Multiplier Phase 2, Quadrant B VCCD Bottom Phase 2 Thermal Electric Cooler Negative Terminal VCCD Top Phase 2 EMCCD Storage Multiplier Phase 2, Quadrant C EMCCD Storage Multiplier Phase 2, Quadrant D VCCD Top Phase 2 Thermal Electric Cooler Positive Terminal Amplifier 1 Return, Quadrant C No Connection EMCCD Storage Multiplier Phase 1, Quadrant C EMCCD Storage Multiplier Phase 1, Quadrant D No Connection www.onsemi.com 13 KAE−02152 Table 5. PGA WITH INTEGRATED TEC PIN DESCRIPTION (continued) Pin Label Description F15 VSS1d F16 N/C No Connection F17 V1T VCCD Top Phase 1 F18 TEC+ Thermal Electric Cooler Positive Terminal G01 ESD ESD Protection Disable G02 V4T VCCD Top Phase 4 G03 VOUT1c Amplifier 1 Output, Quadrant C G04 VOUT2c Video Output 2, Quadrant C G05 H2SW3c HCCD Output 3 Selector, Quadrant C G06 VOUT3c Video Output 3, Quadrant C G07 H2BEMc EMCCD Barrier Phase 2, Quadrant C G08 H1Bc HCCD Barrier Phase 1, Quadrant C G09 GND Ground G10 H1Bd HCCD Barrier Phase 1, Quadrant D G11 H2BEMd EMCCD Barrier Phase 2, Quadrant D G12 VOUT3d Video Output 3, Quadrant B G13 H2SW3d HCCD Output 3 Selector, Quadrant D G14 VOUT2d Video Output 2, Quadrant D G15 VOUT1d Amplifier 1 Output, Quadrant D G16 V4T VCCD Top Phase 4 G17 SUB Substrate G18 TEC+ Thermal Electric Cooler Positive Terminal H01 GND Ground H02 V3T VCCD Top Phase 3 H03 N/C No Connection H04 RG2c H05 N/C H06 VDD23cd Amplifier 2 And 3 Supply, Quadrants C, D H07 H1BEMc EMCCD Barrier Phase 1, Quadrant C H08 H2Bc HCCD Barrier Phase 2, Quadrant C H09 GND Ground H10 H2Bd HCCD Barrier Phase 2, Quadrant D H11 H1BEMd EMCCD Barrier Phase 1, Quadrant D H12 VDD23cd Amplifier 2 And 3 Supply, Quadrants C, D H13 N/C H14 RG2d H15 N/C No Connection H16 V3T VCCD Top Phase 3 H17 SUBREF H18 TEC+ Amplifier 1 Return, Quadrant D Amplifier 2 Reset, Quadrant C No Connection No Connection Amplifier 2 Reset, Quadrant D Substrate Voltage Reference Thermal Electric Cooler Positive Terminal 1. Pins A03 and A05 are connected to a negative temperature coefficient thermistor 2. All TEC pins (A18, B18, C18, D18, E18, F18, G18, and H18) must be driven. www.onsemi.com 14 KAE−02152 IMAGING PERFORMANCE Table 6. TYPICAL OPERATIONAL CONDITIONS (Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.) Condition Description Notes Light Source Continuous Red, Green and Blue LED Illumination Operation Nominal Operating Voltages and Timing Temperature 0°C 1 1. For monochrome sensor, only green LED used. Table 7. SPECIFICATIONS Description Dark Field Global Non-Uniformity Symbol Min. Nom. Max. Units Sampling Plan Temperature Tested at (5C) DSNU − − 2.0 mV pp Die 0 − 2.0 5.0 % rms Die 0 1 − 5.0 15.0 % pp Die 0 1 − 1.0 2.0 % rms Die 0 1 Bright Field Global Non-Uniformity Bright Field Global Peak to Peak Non-Uniformity PRNU Bright Field Center Non-Uniformity Notes Maximum Photoresponse Nonlinearity (EMCCD Gain = 1) NL − 2 − % Design 2 Maximum Gain Difference Between Outputs (EMCCD Gain = 1) DG − 10 − % Design 2 Maximum Signal Error due to Nonlinearity Differences (EMCCD Gain = 1) DNL − 1 − % Design 2 Horizontal CCD Charge Capacity HNe − 30 − ke− Design Vertical CCD Charge Capacity VNe − 30 − ke− Design Photodiode Charge Capacity PNe − 20 − ke− Die 0 Horizontal CCD Charge Transfer Efficiency HCTE 0.999995 0.999999 − Die 0 Vertical CCD Charge Transfer Efficiency VCTE 0.999995 0.999999 − Die 0 Photodiode Dark Current (Average) IPD − 0.1 3 e−/p/s Design 0 Vertical CCD Dark Current IVD − 6 − e−/p/s Design 0 e− Design Image Lag Lag − − 99.2% 435−630 nm T > 98.0% 5. Units: mm 630−680 nm www.onsemi.com 56 KAE−02152 Cover Glass Transmissions Figure 59. Cover Glass Transmission ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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