KAE-08151-FBA-JP-FA

KAE-08151 2856 (H) x 2856 (V) Interline Transfer EMCCD Image Sensor The KAE−08151 Image Sensor is a 8.1 Mp, 4/3″ format, Interline Transfer EMCCD image sensor that provides exceptional imaging performance in extreme low light applications. Each of the sensor’s four outputs incorporates both a conventional horizontal CCD register and a high gain EMCCD register. An intra-scene switchable gain feature samples each charge packet on a pixel-by-pixel basis. This enables the camera system to determine whether the charge will be routed through the normal gain output or the EMCCD output based on a user selectable threshold. This feature enables imaging in extreme low light, even when bright objects are within a dark scene, allowing a single camera to capture quality images from sunlight to starlight. This image sensor is based on an advanced 5.5-micron Interline Transfer CCD Platform, and features extended dynamic range, excellent imaging performance, and a flexible readout architecture that enables use of 1, 2, or 4 outputs. A vertical overflow drain structure suppresses image blooming, provides excellent MTF, and enables electronic shuttering for precise exposure. www.onsemi.com Figure 1. KAE−08151 Interline Transfer EMCCD Image Sensor Table 1. GENERAL SPECIFICATIONS Parameter Architecture Total Number of Pixels Number of Effective Pixels Number of Active Pixels Pixel Size Active Image Size Typical Value Interline CDD; with EMCCD 2928 (H) × 2904 (V) 2880 (H) × 2880 (V) 2856 (H) × 2856 (V) 5.5 mm (H) × 5.5 mm (V) 15.71 mm (H) × 15.71 mm (V) 22.22 mm (Diagonal) 4/3″ Optical Format Aspect Ratio Number of Outputs Charge Capacity Output Sensitivity Quantum Sensitivity Mono/Color (RGB) 1:1 1, 2, or 4 20,000 e− 44 mV/e− 9 e− rms < 1 e− rms Dark Current (0°C) Photodiode, VCCD < 0.1, 6 e−/s Dynamic Range Normal Mode (1× Gain) Intra-Scene Mode (20× Gain) • • • • 0.999999 > 1000 X −100 dB < 1 e− 40 MHz for horiz. binning Package Type Cover Glass 155 Pin PGA Clear Glass, Taped MAR Glass, Sealed Intra-Scene Switchable Gain Wide Dynamic Range Low Noise Architecture Exceptional Low Light Imaging Global Shutter Excellent Image Uniformity and MTF Bayer Color Pattern and Monochrome Surveillance Scientific Imaging Medical Imaging Intelligent Transportation ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. 66 dB 86 dB Charge Transfer Efficiency Blooming Suppression Smear Image Lag Maximum Pixel Clock Speed Maximum Frame Rate Normal Gain Mode, Intra-Scene Mode • • • • • • • Applications 50% / 33%, 41%, 43% Readout Noise (20 MHz) Normal Mode (1× Gain) Intra-Scene Mode (20× Gain) Features 14 fps (40 MHz), 8 fps (20 MHz) NOTE: All Parameters are specified at T = −10°C unless otherwise noted. © Semiconductor Components Industries, LLC, 2016 March, 2018 − Rev. 3 1 Publication Order Number: KAE−08151/D KAE−08151 ORDERING INFORMATION US export controls apply to all shipments of this product designated for destinations outside of the US and Canada, requiring ON Semiconductor to obtain an export license from the US Department of Commerce before image sensors or evaluation kits can be exported. Table 2. ORDERING INFORMATION − KAE−08151 IMAGE SENSOR Part Number Description KAE−08151−ABA−JP−FA Monochrome, Microlens, PGA Package, Taped Clear Cover Glass (No Coatings), Standard Grade KAE−08151−ABA−JP−EE Monochrome, Microlens, PGA Package, Taped Clear Cover Glass (No Coatings), Engineering Grade KAE−08151−FBA−JP−FA Color (Bayer RGB), Microlens, PGA Package, Taped Clear Cover Glass (No Coatings), Standard Grade KAE−08151−FBA−JP−EE Color (Bayer RGB), Microlens, PGA Package, Taped Clear Cover Glass (No Coatings), Engineering Grade KAE−08151−ABA−SP−FA Monochrome, Microlens, PGA Package with Integrated TEC, Taped Clear Cover Glass (No Coatings), Standard Grade KAE−08151−ABA−SP−EE Monochrome, Microlens, PGA Package with Integrated TEC, Taped Clear Cover Glass (No Coatings), Engineering Grade KAE−08151−FBA−SP−FA Color (Bayer RGB), Microlens, PGA Package with Integrated TEC, Taped Clear Cover Glass (No Coatings), Standard Grade KAE−08151−FBA−SP−EE Color (Bayer RGB), Microlens, PGA Package with Integrated TEC, Taped Clear Cover Glass (No Coatings), Engineering Grade KAE−08151−ABA−SD−FA Monochrome, Microlens, PGA Package with Integrated TEC, Sealed MAR Cover Glass, Standard Grade KAE−08151−ABA−SD−EE Monochrome, Microlens, PGA Package with Integrated TEC, Sealed MAR Cover Glass, Engineering Grade KAE−08151−FBA−SD−FA Color (Bayer RGB), Microlens, PGA Package with Integrated TEC, Sealed MAR Cover Glass, Standard Grade KAE−08151−FBA−SD−EE Color (Bayer RGB), Microlens, PGA Package with Integrated TEC, Sealed MAR Cover Glass, Engineering Grade Marking Code KAE−08151−ABA Serial Number KAE−08151−FBA Serial Number KAE−08151−ABA Serial Number KAE−08151−FBA Serial Number KAE−08151−ABA Serial Number KAE−08151−FBA Serial Number See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. Warning As a result, care must be taken to avoid cooling the device below the dew point inside the package cavity, since this may result in moisture condensation. For all KAE−08151 configurations, no warranty, expressed or implied, covers condensation. The KAE−08151−ABA−SD and KAE−08151−FBA−SD packages have an integrated thermoelectric cooler (TEC) and have epoxy−sealed cover glass. The seal formed is non−hermetic, and may allow moisture ingress over time, depending on the storage environment. www.onsemi.com 2 KAE−08151 DEVICE DESCRIPTION Architecture 3 3 1242 1242 450 450 450 1 28 3 2 837 12 1464 3 1 28 450 1464 12 28 1 3 12 12 1 24 12 2 837 2856 x 2856 12 12 1464 450 1464 837 2 1 2 12 24 1 12 1 837 450 12 3 28 1 450 450 1242 1242 3 3 Figure 2. Block Diagram Dark Reference Pixels Image Acquisition There are 12 dark reference rows at the top and bottom of the image sensor, as well as 24 dark reference columns on the left and right sides. However, the rows and columns at the perimeter edges should not be included in acquiring a dark reference signal, since they may be subject to some light leakage. An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photo-site. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. Active Buffer Pixels 12 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. These pixels are light sensitive but are not tested for defects and non-uniformities. www.onsemi.com 3 KAE−08151 Physical Description Pin Grid Array Configuration Output “D” Output “C” F E D C B A 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Output “B” Output “A” Figure 3. PGA Package Pin Designations (Bottom View) Table 3. PIN DESCRIPTION Pin No. Label A2 +9 V A3 VDD15ac A4 VDD1a A5 VOUT1a A6 VDD2a A7 VOUT2a A8 H2La Description Charge Injection diode, quadrants a and c +15 Volts supply Amplifier 1 supply, quadrant a Video output 1, quadrant a Amplifier 2 supply, quadrant a Video output 2, quadrant a HCCD last gate, outputs 1,2 and 3, quadrant a A9 VDD3a A10 VOUT3a Amplifier 3 supply, quadrant a video output 3, quadrant a A11 H1a HCCD phase 1, quadrant a www.onsemi.com 4 KAE−08151 Table 3. PIN DESCRIPTION (continued) Pin No. Label Description A12 H2a HCCD phase 2, quadrant a A13 GND Ground A14 H2b HCCD phase 2, quadrant b A15 H1b HCCD phase 1, quadrant b A16 VOUT3b Video output 3, quadrant b A17 VDD3b A18 H2Lb A19 VOUT2b Amplifier 3 supply, quadrant b HCCD last gate, outputs 1,2 and 3, quadrant b Video output 2, quadrant b A20 VDD2b Amplifier 2 supply, quadrant b A21 VOUT1b Amplifier 1 output, quadrant b A22 VDD1b amplifier 1 supply, quadrant b A23 VDD15bd A24 +9 V Charge injection diode, quadrants b and d A25 GND Ground A26 N/C No connect B1 GND Ground B2 ESD Charge injection clock, quadrants a and c B3 V4B VCCD bottom phase 4 B4 GND Ground B5 VSS1a Amplifier 1 return, quadrant a B6 RG1a Amplifier 1 reset, quadrant a B7 RG23a Amplifier 2 and 3 reset, quadrant a B8 GND 15 V Supply, quadrants b and d Ground B9 H2BEMa EMCCD barrier phase 2, quadrant a B10 H1BEMa EMCCD barrier phase 1, quadrant a B11 H1Sa HCCD storage phase 1, quadrant a B12 H2Sa HCCD storage phase 2, quadrant a B13 GND Ground B14 H2Sb HCCD storage phase 2, quadrant b B15 H1Sb HCCD storage phase 1, quadrant b B16 H1BEMb EMCCD barrier phase 1, quadrant b B17 H2BEMb EMCCD barrier phase 2, quadrant b B18 GND B19 RG23b Amplifier 2 and 3 reset, quadrant b B20 RG1b Amplifier 1 reset, quadrant b B21 VSS1b Amplifier 1 return, quadrant b B22 GND Ground B23 V4B VCCD bottom phase 4 B24 ESD Charge injection clock, quadrants b and d B25 GND Ground B26 N/C No connect C1 GND Ground C2 ID C3 V3B VCCD bottom phase 3 C4 V2B VCCD bottom phase 2 Ground Device ID www.onsemi.com 5 KAE−08151 Table 3. PIN DESCRIPTION (continued) Pin No. Label Description C5 V1B C6 H2Xa VCCD bottom phase 1 C7 H2SW2a HCCD output 2 selector, quadrant a C8 H2SW3a HCCD output 3 selector, quadrant a C9 H2SEMa EMCCD storage multiplier phase 2, quadrant a C10 H1SEMa EMCCD storage multiplier phase 1, quadrant a C11 H1Ba HCCD barrier phase 1, quadrant a C12 H2Ba HCCD barrier phase 2, quadrant a C13 SUB substrate C14 H2Bb HCCD barrier phase 2, quadrant b C15 H1Bb HCCD barrier phase 1, quadrant b C16 H1SEMb EMCCD storage multiplier phase 1, quadrant b C17 H2SEMb EMCCD storage multiplier phase 2, quadrant b C18 H2SW3b HCCD Output 3 Selector, Quadrant b C19 H2SW2b HCCD Output 2 Selector, Quadrant b C20 H2Xb C21 V1B VCCD bottom phase 1 C22 V2B VCCD bottom phase 2 C23 V3B VCCD bottom phase 3 C24 N/C No connect C25 GND Ground C26 N/C No connect D1 N/C No connect D2 N/C No connect D3 V3T VCCD top phase 3 D4 V2T VCCD top phase 2 D5 V1T VCCD top phase 1 D6 H2Xc D7 H2SW2c HCCD Output 2 Selector, Quadrant c D8 H2SW3c HCCD Output 3 Selector, Quadrant c Floating gate exit HCCD gate, quadrant a Floating gate exit HCCD gate, quadrant b Floating gate exit HCCD gate, quadrant c D9 H2SEMc EMCCD storage phase 2, quadrant c D10 H1SEMc EMCCD storage phase 1, quadrant c D11 H1Bc HCCD barrier phase 1, quadrant c D12 H2Bc HCCD barrier phase 2, quadrant c D13 SUB Substrate D14 H2Bd HCCD barrier phase 2, quadrant d D15 H1Bd HCCD barrier phase 1, quadrant d D16 H1SEMd EMCCD storage multiplier phase 1, quadrant d D17 H2SEMd EMCCD storage multiplier phase 2, quadrant d D18 H2SW3d HCCD output 3 selector, quadrant d D19 H2SW2d HCCD output 2 selector, quadrant d D20 H2Xd D21 V1T VCCD top phase 1 D22 V2T VCCD top phase 2 D23 V3T VCCD top phase 3 Floating gate exit HCCD gate, quadrant d www.onsemi.com 6 KAE−08151 Table 3. PIN DESCRIPTION (continued) Pin No. Label Description D24 VSUBREF D25 GND Ground D26 N/C No connect E1 N/C No connect E2 GND Charge injection gate, quadrants a and c E3 V4T VCCD top phase 4 E4 GND Ground E5 VSS1c Amplifier 1 return, quadrant c E6 RG1c Amplifier 1 reset, quadrant c E7 RG23c Amplifier 2 and 3 reset, quadrant c Substrate voltage reference E8 GND E9 H2BEMc Ground EMCCD barrier phase 2, quadrant c E10 H1BEMc EMCCD barrier phase 1, quadrant c E11 H1Sc HCCD storage phase 1, quadrant c E12 H2Sc HCCD storage phase 2, quadrant c E13 GND Ground E14 H2Sd HCCD storage phase 2, quadrant d E15 H1Sd HCCD storage phase 1, quadrant d E16 H1BEMd EMCCD barrier phase 1, quadrant d E17 H2BEMd EMCCD barrier phase 2, quadrant d E18 GND E19 RG23d Ground Amplifier 2 and 3 reset, quadrant d E20 RG1d Amplifier 1 reset, quadrant d E21 VSS1d Amplifier 1 return, quadrant d E22 GND Ground E23 V4T VCCD top phase 4 E24 GND Charge injection gate, quadrants b and d E25 GND Ground E26 N/C No connect F1 N/C No connect F2 V2B Charge injection clock, quadrants a and c F3 ESD F4 VDD1c F5 VOUT1c F6 VDD2c F7 VOUT2c F8 H2Lc F9 VDD3c F10 VOUT3c Video output 3, quadrant c F11 H1c HCCD phase 1, quadrant c F12 H2c HCCD phase 2, quadrant c F13 GND Ground F14 H2d HCCD phase 2, quadrant d F15 H1d HCCD phase 1, quadrant d F16 VOUT3d Video output 3, quadrant b Amplifier 1 supply, quadrant c Video output 1, quadrant c Amplifier 2 supply, quadrant c Video output 2, quadrant c HCCD last gate, outputs 1,2 and 3, quadrant c Amplifier 3 supply, quadrant c www.onsemi.com 7 KAE−08151 Table 3. PIN DESCRIPTION (continued) Pin No. Label F17 VDD3d F18 H2Ld F19 VOUT2d Description Amplifier 3 supply, quadrant d HCCD last gate, outputs 1,2 and 3, quadrant d Video output 2, quadrant d F20 VDD2d amplifier 2 supply, quadrant d F21 VOUT1d Amplifier 1 Output, Quadrant d F22 VDD1d Amplifier 1 Supply, Quadrant d F23 ESD F24 V2B Charge injection clock, quadrants b and d Table 4. PIN DESCRIPTION FOR PACKAGE WITH INTEGRATED TEC Pin No. Label Description A2 +9 V +9 V Supply A3 VDD15ac +15 V Supply A4 VDD1a A5 VOUT1a A6 VDD2a A7 VOUT2a A8 H2La Amplifier 1 Supply, Quadrant a Video Output 1, Quadrant a Amplifier 2 Supply, Quadrant a Video Output 2, Quadrant a HCCD Last Gate, Outputs 1, 2 and 3, Quadrant a A9 VDD3a A10 VOUT3a Amplifier 3 Supply, Quadrant a Video Output 3, Quadrant a A11 H1a HCCD Phase 1, Quadrant a A12 H2a HCCD Phase 2, Quadrant a A13 GND Ground A14 H2b HCCD Phase 2, Quadrant b A15 H1b HCCD Phase 1, Quadrant b A16 VOUT3b Video Output 3, Quadrant b A17 VDD3b A18 H2Lb A19 VOUT2b A20 VDD2b Amplifier 2 Supply, Quadrant b A21 VOUT1b Amplifier 1 Output, Quadrant b A22 VDD1b Amplifier 1 Supply, Quadrant b A23 VDD15bd Amplifier 3 Supply, Quadrant b HCCD Last Gate, Outputs 1, 2 and 3, Quadrant b Video Output 2, Quadrant b +15 V Supply, Quadrants b and d A24 +9 V +9 V Supply A25 GND Ground A26 TEC− Thermoelectric Cooler Negative Bias B1 GND Ground B2 ESD ESD B3 V4B VCCD Bottom Phase 4 B4 GND Ground B5 VSS1a Amplifier 1 Return, Quadrant a B6 RG1a Amplifier 1 Reset, Quadrant a B7 RG23a Amplifier 2 and 3 Reset, Quadrant a B8 GND Ground www.onsemi.com 8 KAE−08151 Table 4. PIN DESCRIPTION FOR PACKAGE WITH INTEGRATED TEC (continued) Pin No. Label Description B9 H2BEMa EMCCD Barrier Phase 2, Quadrant a B10 H1BEMa EMCCD Barrier Phase 1, Quadrant a B11 H1Sa HCCD Storage Phase 1, Quadrant a B12 H2Sa HCCD Storage Phase 2, Quadrant a B13 GND Ground B14 H2Sb HCCD Storage Phase 2, Quadrant b B15 H1Sb HCCD Storage Phase 1, Quadrant b B16 H1BEMb EMCCD Barrier Phase 1, Quadrant b B17 H2BEMb EMCCD Barrier Phase 2, Quadrant b B18 GND B19 RG23b Amplifier 2 and 3 Reset, Quadrant b B20 RG1b Amplifier 1 Reset, Quadrant b B21 VSS1b Amplifier 1 Return, Quadrant b B22 GND Ground B23 V4B VCCD Bottom Phase 4 B24 ESD ESD B25 GND Ground B26 TEC− Thermoelectric Cooler Negative Bias C1 GND Ground C2 ID C3 V3B VCCD Bottom Phase 3 C4 V2B VCCD Bottom Phase 2 C5 V1B VCCD Bottom Phase 1 Ground Device ID C6 H2Xa C7 H2SW2a Floating Gate Exit HCCD Gate, Quadrant a HCCD Output 2 Selector, Quadrant a C8 H2SW3a HCCD Output 3 Selector, Quadrant a C9 H2SEMa EMCCD Storage Multiplier Phase 2, Quadrant a C10 H1SEMa EMCCD Storage Multiplier Phase 1, Quadrant a C11 H1Ba HCCD Barrier Phase 1, Quadrant a C12 H2Ba HCCD Barrier Phase 2, Quadrant a C13 SUB Substrate C14 H2Bb HCCD Barrier Phase 2, Quadrant b C15 H1Bb HCCD Barrier Phase 1, Quadrant b C16 H1SEMb EMCCD Storage Multiplier Phase 1, Quadrant b C17 H2SEMb EMCCD Storage Multiplier Phase 2, Quadrant b C18 H2SW3b HCCD Output 3 Selector, Quadrant b C19 H2SW2b HCCD Output 2 Selector, Quadrant b C20 H2Xb C21 V1B VCCD Bottom Phase 1 C22 V2B VCCD Bottom Phase 2 C23 V3B VCCD Bottom Phase 3 C24 N/C No connect C25 GND Ground C26 TEC− Thermoelectric Cooler Negative Bias D1 N/C Floating Gate Exit HCCD Gate, Quadrant b No connect www.onsemi.com 9 KAE−08151 Table 4. PIN DESCRIPTION FOR PACKAGE WITH INTEGRATED TEC (continued) Pin No. Label Description D2 N/C No connect D3 V3T VCCD Top Phase 3 D4 V2T VCCD Top Phase 2 D5 V1T VCCD Top Phase 1 D6 H2Xc D7 H2SW2c HCCD Output 2 Selector, Quadrant c D8 H2SW3c HCCD Output 3 Selector, Quadrant c D9 H2SEMc EMCCD Storage Phase 2, Quadrant c D10 H1SEMc EMCCD Storage Phase 1, Quadrant c D11 H1Bc HCCD Barrier Phase 1, Quadrant c D12 H2Bc HCCD Barrier Phase 2, Quadrant c D13 SUB Substrate D14 H2Bd HCCD Barrier Phase 2, Quadrant d D15 H1Bd HCCD Barrier Phase 1, Quadrant d D16 H1SEMd EMCCD Storage Multiplier Phase 1, Quadrant d D17 H2SEMd EMCCD Storage Multiplier Phase 2, Quadrant d D18 H2SW3d HCCD Output 3 Selector, Quadrant d D19 H2SW2d HCCD Output 2 Selector, Quadrant d D20 H2Xd D21 V1T VCCD Top Phase 1 D22 V2T VCCD Top Phase 2 D23 V3T VCCD Top Phase 3 D24 VSUBREF Floating Gate Exit HCCD Gate, Quadrant c Floating Gate Exit HCCD Gate, Quadrant d Substrate Voltage Reference D25 GND Ground D26 TEC+ Thermoelectric Cooler Positive Bias E1 N/C No connect E2 GND Ground E3 V4T VCCD Top Phase 4 E4 GND Ground E5 VSS1c Amplifier 1 Return, Quadrant c E6 RG1c Amplifier 1 Reset, Quadrant c E7 RG23c Amplifier 2 and 3 Reset, Quadrant c E8 GND Ground E9 H2BEMc EMCCD Barrier Phase 2, Quadrant c E10 H1BEMc EMCCD Barrier Phase 1, Quadrant c E11 H1Sc HCCD Storage Phase 1, Quadrant c E12 H2Sc HCCD Storage Phase 2, Quadrant c E13 GND Ground E14 H2Sd HCCD Storage Phase 2, Quadrant d E15 H1Sd HCCD Storage Phase 1, Quadrant d E16 H1BEMd EMCCD Barrier Phase 1, Quadrant d E17 H2BEMd EMCCD Barrier Phase 2, Quadrant d E18 GND E19 RG23d Amplifier 2 and 3 Reset, Quadrant d E20 RG1d Amplifier 1 Reset, Quadrant d Ground www.onsemi.com 10 KAE−08151 Table 4. PIN DESCRIPTION FOR PACKAGE WITH INTEGRATED TEC (continued) Pin No. Label Description E21 VSS1d E22 GND Ground E23 V4T VCCD Top Phase 4 E24 GND Ground E25 GND Ground E26 TEC+ Thermoelectric Cooler Positive Bias F1 N/C No connect F2 V2B VCCD Bottom Phase 2 F3 ESD ESD F4 VDD1c F5 VOUT1c F6 VDD2c F7 VOUT2c Amplifier 1 Return, Quadrant d Amplifier 1 Supply, Quadrant c Video Output 1, Quadrant c Amplifier 2 Supply, Quadrant c Video Output 2, Quadrant c F8 H2Lc F9 VDD3c F10 VOUT3c Video Output 3, Quadrant c F11 H1c HCCD Phase 1, Quadrant c F12 H2c HCCD Phase 2, Quadrant c F13 GND Ground F14 H2d HCCD Phase 2, Quadrant d F15 H1d HCCD Phase 1, Quadrant d F16 VOUT3d Video Output 3, Quadrant b F17 VDD3d F18 H2Ld F19 VOUT2d HCCD Last Gate, Outputs 1, 2 and 3, Quadrant c Amplifier 3 Supply, Quadrant c Amplifier 3 Supply, Quadrant d HCCD Last Gate, Outputs 1, 2 and 3, Quadrant d Video Output 2, Quadrant d F20 VDD2d Amplifier 2 Supply, Quadrant d F21 VOUT1d Amplifier 1 Output, Quadrant d F22 VDD1d Amplifier 1 Supply, Quadrant d F23 ESD ESD F24 V2B VCCD Bottom Phase 2 F25 GND Ground F26 TEC+ Thermoelectric Cooler Positive Bias www.onsemi.com 11 KAE−08151 Imaging Performance Table 5. TYPICAL OPERATION CONDITIONS (Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.) Condition Description Light Source (Note 1) Continuous Red, Green and Blue LED Illumination Operation Nominal Operating Voltages and Timing 1. For monochrome sensor, only green LED light source is used. Table 6. SPECIFICATIONS Description Dark Field Global Non-Uniformity Symbol Min. Nom. Max. Unit DSNU − − 2.0 mV pp Die −10 − 2.0 5.0 % rms Die −10 − 5.0 15.0 % pp Die −10 − 1.0 2.0 % rms Die −10 Bright Field Global Non-Uniformity (Note 2) Bright Field Global Peak to Peak Non-Uniformity (Note 2) Temperature Tested at (5C) Sampling Plan PRNU Bright Field Center Non-Uniformity (Note 2) Maximum Photoresponse Non-Linearity (EMCCD Gain = 1) (Note 3) NL − 2 − % Design Maximum Gain Difference Between Outputs (EMCCD Gain = 1) (Note 8) DG − 10 − % Design Maximum Signal Error due to Non-Linearity Differences (EMCCD Gain = 1) (Note 3) DNL − 1 − % Design Horizontal CCD Charge Capacity HNe − 30 − ke− Design − ke− Design ke− Die −10 Vertical CCD Charge Capacity VNe − 30 Photodiode Charge Capacity (Note 4) PNe − 20 − Horizontal CCD Charge Transfer Efficiency HCTE 0.999995 0.999999 − Die −10 Vertical CCD Charge Transfer Efficiency VCTE 0.999995 0.999999 − Die −10 Photodiode Dark Current (Average) IPD − 0.1 3 e/p/s Design −10 − 0.3 − e/p/s Design −10 − 10 e− Design Vertical CCD Dark Current Image Lag Lag − Anti-Blooming Factor XAB 1000 − − Vertical Smear (Blue Light) Smr − −100 − dB Design Read Noise (EMCCD Gain = 1) (Note 5) ne−T − 9 − e− rms Design Read Noise (EMCCD Gain = 20) − 50% 400−900 nm Tabs > 97% 900−1100 nm Tabs > 85% 900−1100 nm Tave > 88% 4. Epoxy is B−staged Form (Ref. KSD−248−0109, Spec KSD−241−0009) 5. All Contamination Outside the A−Zone must be Removable with N2 at 40 PSI 6. Edge Chips: X ≤ 0.50 mm, Y ≤ 0.50 mm, Z ≤ 0.48 mm Figure 54. MAR Glass for PGA with Sealed Cover Glass Figure 55. MAR Cover Glass Transmission www.onsemi.com 52 KAE−08151 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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