KAF-1603-ABA-CD-B2

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Other names and brands may be claimed as the property of others. KAF-1603 1536 (H) x 1024 (V) Full Frame CCD Image Sensor Description The KAF−1603 Image Sensor is a high performance monochrome area CCD (charge-coupled device) image sensor with 1536 (H) × 1024 (V) photoactive pixels designed for a wide range of image sensing applications. The sensor incorporates true two-phase CCD technology, simplifying the support circuits required to drive the sensor as well as reducing dark current without compromising charge capacity. The sensor also utilizes the TRUESENSE Transparent Gate Electrode to improve sensitivity compared to the use of a standard front side illuminated polysilicon electrode. Optional microlenses focus the majority of the light through the transparent gate, increasing the optical response further. www.onsemi.com Table 1. GENERAL SPECIFICATIONS Parameter Figure 1. KAF−1603 CCD Image Sensor Typical Value Architecture Full Frame CCD Total Number of Pixels 1552 (H) × 1032 (V) Number of Active Pixels 1536 (H) × 1024 (V) = approx. 1.6 Mp Pixel Size 9.0 mm (H) × 9.0 mm (V) Active Image Size 13.8 mm (H) × 9.2 mm (V) 16.6 mm (Diagonal) 1″ Optical Format Applications Die Size 15.5 mm (H) × 10.0 mm (V) • Scientific Imaging Aspect Ratio 3:2 Saturation Signal 100,000 electrons Features for High Sensitivity ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Output Sensitivity 10 mV/e− Quantum Efficiency (with Microlens) Peak: 77% 400 nm: 45% Quantum Efficiency (no Microlens) Peak: 65% 400 nm: 30% Read Noise 15 electrons Dark Current < 10 pA/cm2 Dark Current Doubling Temperature 6.3°C Dynamic Range 74 dB Charge Transfer Efficiency > 0.99999 Blooming Suppression None Maximum Date Rate 10 MHz Package CERDIP Package (Sidebrazed) Cover Glass Clear or AR Coated, 2 Sides NOTE: • True Two Phase Full Frame Architecture • TRUESENSE Transparent Gate Electrode Parameters above are specified at T = 25°C unless otherwise noted. © Semiconductor Components Industries, LLC, 2014 February, 2017 − Rev. 2 1 Publication Order Number: KAF−1603/D KAF−1603 ORDERING INFORMATION Table 2. ORDERING INFORMATION − KAF−1603 IMAGE SENSOR Part Number Description Marking Code KAF−1603−ABA−CD−B2 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass with AR Coating (Both Sides), Grade 2 KAF−1603−ABA−CD−AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass with AR Coating (Both Sides), Engineering Sample KAF−1603−ABA−CP−B2 Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Grade 2 KAF−1603−ABA−CP−AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Engineering Sample KAF−1603−AAA−CP−B2 Monochrome, No Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Grade 2 KAF−1603−AAA−CP−AE Monochrome, No Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Engineering Sample KAF−1603−ABA Serial Number KAF−1603−AAA Serial Number Table 3. ORDERING INFORMATION − EVALUATION SUPPORT Part Number KAF−1603−12−5−A−EVK Description Evaluation Board (Complete Kit) See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAF−1603 DEVICE DESCRIPTION Architecture 4 Dark Lines fV1 fV2 KAF−1603 Usable Active Image Area 1536 (H) × 1024 (V) 9 × 9 mm Pixels GUARD 3:2 Aspect Ratio VRD fR VDD VOUT VSS ÉÉ 1536 Active Pixels/Line 4 Dark 10 Inactive 12 Dark 2 Inactive É 4 Dark Lines fH1 fH2 SUB VOG Figure 2. Block Diagram Microlenses The sensor consists of 1,552 parallel (vertical) CCD shift registers each 1,032 elements long. These registers act as both the photosensitive elements and as the transport circuits that allow the image to be sequentially read out of the sensor. The parallel (vertical) CCD registers transfer the image one line at a time into a single 1,564 element (horizontal) CCD shift register. The horizontal register transfers the charge to a single output amplifier. The output amplifier is a two-stage source follower that converts the photo-generated charge to a voltage for each pixel. Micro lenses are formed along each row. They are effectively half of a cylinder centered on the transparent gates, extending continuously in the row direction. They act to direct the photons away from the polysilicon gate and through the transparent gate. This increases the response, especially at the shorter wavelengths (< 600 nm). Microlens V1 V2 Silicon Figure 3. Microlens Cross-Section www.onsemi.com 3 KAF−1603 Image Acquisition Output Structure Charge presented to the floating diffusion is converted into a voltage and current amplified in order to drive off-chip loads. The resulting voltage change seen at the output is linearly related to the amount of charge placed on the floating diffusion. Once the signal has been sampled by the system electronics, the reset gate (fR) is clocked to remove the signal, and the floating diffusion is reset to the potential applied by Vrd (see Figure 4). More signal at the floating diffusion reduces the voltage seen at the output pin. In order to activate the output structure, an off-chip load must be added to the Vout pin of the device such as shown in Figure 5. An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the sensor. These photon-induced electrons are collected locally by the formation of potential wells at each photogate or pixel site. The number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the pixel’s capacity is reached, excess electrons will leak into the adjacent pixels within the same column. This is termed blooming. During the integration period, the fV1 and fV2 register clocks are held at a constant (low) level, and the sensor is illuminated. See Figure 9. The sensor must be illuminated only during the integration period. Light must not reach the sensor during the time the image is read out. This is usually accomplished with the use of a mechanical shutter or a pulsed light source. Dark Reference Pixels There are 4 light shielded pixels at the beginning of each line, and 12 at the end. There are 4 dark lines at the start of every frame and 4 dark lines at the end of each frame. Under normal circumstances, these pixels do not respond to light. However, dark reference pixels in close proximity to an active pixel can scavenge signal depending on light intensity and wavelength and therefore will not represent the true dark signal. Charge Transport Referring to Figure 10, the integrated charge from each photogate is transported to the output using a two-step process. During this readout time, the sensor needs to be protected from all light through the use of a shutter or pulsed light source. Each line (row) of charge is first moved from the vertical CCD to the horizontal CCD register using the fV1 and fV2 register clocks. The horizontal CCD is presented a new line on the falling edge of fV2 while fH1 is held high. The horizontal CCD then transports each line, pixel by pixel, to the output structure by alternately clocking the fH1 and fH2 pins in a complementary fashion. On each falling edge of fH2 a new charge packet is transferred onto a floating diffusion and sensed by the output amplifier. Dummy Pixels Within the horizontal shift register are 10 leading additional pixels that are not associated with a column of pixels within the vertical register. These pixels contain only horizontal shift register dark current signal and do not respond to light. A few leading dummy pixels may scavenge false signal depending on operating conditions. There are two more dummy pixels at the end of each line. www.onsemi.com 4 KAF−1603 Horizontal Register Output Structure H1 H2 HCCD Charge Transfer H1 H2 VDD VOG R VRD Floating Diffusion VOUT Source Follower #1 Source Follower #2 Figure 4. Output Schematic +15 V 0.1 mF ~5ma VOUT 2N3904 or Equivalent Buffered Output 140 W 1 kW Figure 5. Output Structure Load Diagram www.onsemi.com 5 KAF−1603 Physical Description Pin Description and Device Orientation VOG 1 24 N/C Pin 1 VOUT 2 23 GUARD Pixel 1,1 VDD 3 22 fV1 VRD 4 21 fV1 fR 5 20 fV2 VSS 6 19 fV2 fH1 7 18 fV2 fH2 8 17 fV2 N/C 9 16 fV1 N/C 10 15 fV1 14 VSUB VSUB 11 N/C 12 13 N/C Figure 6. Pinout Diagram NOTE: The KAF−1603 is mechanically the same and electrically identical to the KAF−0402 sensor. It is also mechanically the same as the KAF−0261 and KAF−3200 sensors. There are some electrical differences since the KAF−0261 has two outputs and two additional clock inputs. The KAF−3200 requires that pin 11 be a “No connect” and be electrically floating. Refer to their specifications for details. Table 4. PIN DESCRIPTION Pin Name Pin Name 1 VOG Output Gate 13 N/C 2 VOUT Video Output 14 VSUB 3 VDD Amplifier Supply 15 fV1 Vertical CCD Clock − Phase 1 4 VRD Reset Drain 16 fV1 Vertical CCD Clock − Phase 1 5 fR Reset Clock 17 fV2 Vertical CCD Clock − Phase 2 6 VSS Amplifier Supply Return 18 fV2 Vertical CCD Clock − Phase 2 7 fH1 Horizontal CCD Clock − Phase 1 19 fV2 Vertical CCD Clock − Phase 2 8 fH2 Horizontal CCD Clock − Phase 2 20 fV2 Vertical CCD Clock − Phase 2 9 N/C No Connection (Open Pin) 21 fV1 Vertical CCD Clock − Phase 1 10 N/C No Connection (Open Pin) 22 fV1 Vertical CCD Clock − Phase 1 11 VSUB Substrate (Ground) 23 GUARD 12 N/C No Connection (Open Pin) 24 N/C Description www.onsemi.com 6 Description No Connection (Open Pin) Substrate (Ground) Guard Ring No Connection (Open Pin) KAF−1603 IMAGING PERFORMANCE Table 5. TYPICAL OPERATIONAL CONDITIONS (All values measured at 25°C, and nominal operating conditions. These parameters exclude defective pixels.) Description Saturation Signal Vertical CCD Capacity Horizontal CCD Capacity Output Node Capacity Symbol Min. Nom. Max. 85,000 170,000 190,000 100,000 200,000 220,000 − − 240,000 − − − − 77% 65% NSAT Quantum Efficiency Microlens No Microlens Notes Verification Plan e−/pix 1 Design9 Design9 % QE % 2 Design9 − % 3 Die8 e−/pix/sec pA/cm2 4 Die8 Photoresponse Non-Linearity PRNL − 1.0 2.0 Photoresponse Non-Uniformity PRNU − 0.8 Dark Signal Units JDARK Dark Signal Doubling Temperature − − 10 2 50 10 − 6.3 7 °C 5 Die8 6 Design9 Design9 DSNU − 10 50 e−/pix/sec Dynamic Range DR 72 74 − dB Charge Transfer Efficiency CTE 0.99997 0.99999 − Output Amplifier DC Offset VODC VRD VRD + 0.5 VRD + 1.0 V Die8 Output Amplifier Sensitivity VOUT/Ne− 9 10 − mV/e− Design9 ZOUT 180 200 220 W Design9 − 15 20 electrons Dark Signal Non-Uniformity Output Amplifier Output Impedance Noise Floor ne − 1. 2. 3. 4. 5. 6. 7. Die8 7 Die8 For pixel binning applications, electron capacity up to 330,000 can be achieved with modified CCD inputs. Worst case deviation from straight line fit, between 2% and 90% of VSAT. One Sigma deviation of a 128 × 128 sample when CCD illuminated uniformly at half of saturation. Average of all pixels with no illumination at 25°C. Average dark signal of any of 11 × 8 blocks within the sensor (each block is 128 × 128 pixels). 20log (NSAT / ne−) at nominal operating frequency and 25°C. Noise floor is specified at the nominal pixel frequency and excludes any dark or pattern noises. It is dominated by the output amplifier power spectrum with a bandwidth = 5 × pixel rate. 8. A parameter that is measured on every sensor during production testing. 9. A parameter that is quantified during the design verification activity. www.onsemi.com 7 KAF−1603 TYPICAL PERFORMANCE CURVES KAF−1603 Spectral Response 1 0.9 KAF−1603 (with microlenses) KAF−1603 (no microlenses) Absolute Quantum Efficiency 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 800 Wavelength (nm) Figure 7. Typical Spectral Response www.onsemi.com 8 900 1000 KAF−1603 DEFECT DEFINITIONS Table 6. SPECIFICATIONS (All tests performed at T = 25°C) Point Defect Cluster Defect Column Defect Classification Total Zone A Total Zone A Total Zone A C2 ≤ 10 ≤5 ≤4 ≤2 0 0 Point Defects Dark: A pixel which deviates by more than 6% from neighboring pixels when illuminated to 70% of saturation. Bright: A pixel with a dark current greater than 5,000 e−/pixel/sec at 25°C. A column that does not meet the minimum vertical CCD charge capacity (Low charge capacity column). A column that loses > 250 e− under 2 ke− illumination (Trap defect). Neighboring Pixels The surrounding 128 × 128 pixels or ±64 columns/rows. Cluster Defect A grouping of not more than 5 adjacent point defects. Defect Separation Column and cluster defects are separated by no less than 2 pixels in any direction (excluding single pixel defects). Column Defect A grouping of > 5 contiguous point defects along a single column. A column containing a pixel with dark current > 12,000 e−/pix/sec at 25°C (Bright column). 1, 1024 1536, 1024 368, 812 1168, 812 Zone A Center 800 × 600 Pixels 368, 212 1168, 212 1, 1 1536, 1 Figure 8. Active Pixel Region www.onsemi.com 9 KAF−1603 OPERATION Table 7. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Diode Pin Voltages (Notes 10, 11) VDIODE 0 20 V Gate Pin Voltages (Notes 10, 12, 15) VGATE1 −16 16 V IOUT − −10 mA CLOAD − 15 pF T −20 80 °C RH 5 90 % Output Bias Current (Note 13) Output Load Capacitance (Note 13) Storage Temperature Humidity (Note 14) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 10. Referenced to pin VSUB or between each pin in this group. 11. Includes pins: VRD, VDD, VSS, VOUT. 12. Includes pins: fV1, fV2, fH1, fH2, VOG, VLG, fR. 13. Avoid shorting output pins to ground or any low impedance source during operation. 14. T = 25°C. Excessive humidity will degrade MTTF. 15. This sensor contains gate protection circuits to provide some protection against ESD events. The circuits will turn on when greater than 16 V appears between any two gate pins. Permanent damage can result if excessive current is allowed to flow under these conditions. Table 8. DC BIAS OPERATING CONDITIONS Symbol Minimum Nominal Maximum Units Maximum DC Current (mA) Reset Drain VRD 10.5 11.0 11.5 V 0.01 Output Amplifier Return VSS 1.5 2.0 2.5 V −0.5 Output Amplifier Supply VDD 14.5 15 15.5 V IOUT Substrate VSUB 0 0 0 V 0.01 Output Gate VOG 3.75 4 5 V 0.01 Guard Ring VLG 8.0 9.0 12.0 V 0.01 Video Output Current (Note 16) IOUT − −5 −10 mA − Description 16. An output load sink must be applied to VOUT to activate output amplifier − see Figure 5. AC Operating Conditions Table 9. CLOCK LEVELS Symbol Level Minimum Nominal Maximum Units Effective Capacitance Vertical CCD Clock − Phase 1 fV1 Low −10.5 −10 −9.5 V 6 nF (All fV1 Pins) Vertical CCD Clock − Phase 1 fV1 High 0 0.5 1.0 V 6 nF (All fV1 Pins) Vertical CCD Clock − Phase 2 fV2 Low −10.5 −10.0 −9.5 V 6 nF (All fV2 Pins) Vertical CCD Clock − Phase 2 fV2 High 0 0.5 1.0 V 6 nF (All fV2 Pins) Horizontal CCD Clock − Phase 1 fH1 Low −4.5 −4.0 −3.5 V 50 pF Horizontal CCD Clock − Phase 1 fH1 Amplitude 9.5 10.0 10.5 V 50 pF Horizontal CCD Clock − Phase 2 fH2 Low −4.5 −4.0 −3.5 V 50 pF Horizontal CCD Clock − Phase 2 fH2 Amplitude 9.5 10.0 10.5 V 50 pF Reset Clock fR Low −3.0 −2.0 −1.75 V 50 pF Reset Clock fR Amplitude 5.0 6.0 7.0 V 50 pF Description 17. All pins draw less than 10 mA DC current. 18. Capacitance values relative to VSUB. www.onsemi.com 10 KAF−1603 TIMING Table 10. REQUIREMENTS AND CHARACTERISTICS Description Symbol Minimum Nominal Maximum Units fH − 4 10 MHz tPIX 100 250 − ns fH1, fH2 Set-up Time tfHS 0.5 1 − ms fV1, fV2 Clock Pulse Width (Note 20) tfV 4 5 − ms Reset Clock Width (Note 22) tfR 10 20 − ns tREADOUT 178 420 − ms Integration Time (Note 24) tINT − − − Line Time (Note 25) tLINE 172.4 407 − fH1, fH2 Clock Frequency (Notes 19, 20, 21) Pixel Period (1 Count) Readout Time (Note 23) ms 19. 50% duty cycle values. 20. CTE may degrade above the nominal frequency. 21. Rise and fall times (10/90% levels) should be limited to 5−10% of clock period. Crossover of register clocks should be between 40−60% of amplitude. 22. fR should be clocked continuously. 23. tREADOUT = (1032 × tLINE) 24. Integration time (tINT) is user specified. Longer integration times will degrade noise performance due to dark signal fixed pattern and shot noise. 25. tLINE = (3 × tfV) + tfHS + (1564 × tPIX) + tPIX Frame Timing Frame Timing tINT tREADOUT 1 Frame = 1032 Lines fV1 fV2 Line 1 2 fH1 fH2 Figure 9. Frame Timing Diagram www.onsemi.com 11 1031 1032 KAF−1603 Line Timing and Pixel Timing Line Timing Detail Pixel Timing Detail 1 Line = 796 Pixels tfR tfV fR fV1 tfV fH1 fV2 tPIX 1 Count tPIX tfHS fH2 fH1 VPIX fH2 VOUT 1564 Counts VSAT VDARK fR VODC VSUB Line Content 1−10 11−14 VSAT VDARK 15−1550 1551−1562 1563−1564 VPIX Photoactive VODC VSUB Dummy Pixels Saturated pixel video output signal Video output signal in no-light situation (not zero due to JDARK and HCLOCK feedthrough) Pixel video output signal level, mode electrons = less positive* Video level offset with respect to VSUB Analog ground * See Image Acquisition section. Dark Reference Figure 10. Timing Diagrams www.onsemi.com 12 KAF−1603 STORAGE AND HANDLING Table 11. STORAGE CONDITIONS Description Symbol Minimum Maximum Units Storage Temperature (Note 26) TST −20 80 °C Operating Temperature TOP −60 60 °C 26. Storage toward the maximum temperature will accelerate color filter degradation. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. www.onsemi.com 13 KAF−1603 MECHANICAL INFORMATION Completed Assembly Figure 11. Completed Assembly (1 of 2) www.onsemi.com 14 KAF−1603 Figure 12. Completed Assembly (2 of 2) ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ◊ N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 15 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative KAF−1603/D