KAF-16801-AAA-DP-B1

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Other names and brands may be claimed as the property of others. KAF-16801 4096 (H) x 4096 (V) Full Frame CCD Image Sensor Description The KAF−16801 is a high performance area CCD (charge-coupled device) image sensor with 4096 (H) × 4096 (V) photo active pixels designed for a wide range of image sensing applications. The sensor incorporates true two-phase CCD technology, simplifying the support circuits required to drive the sensor as well as reducing dark current without compromising charge capacity. The sensor also utilizes the TRUESENSE Transparent Gate Electrode to improve sensitivity compared to the use of a standard front side illuminated polysilicon electrode. www.onsemi.com Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture Full Frame CCD Pixel Count 4096 (H) × 4096 (V) Pixel Size 9.0 mm (H) × 9.0 mm (V) Active Image Size 36.88 mm (H) × 36.88 mm (V) 52.1 mm (Diagonal) 645 1.3x Optical Format Figure 1. KAF−16801 Full Frame CCD Image Sensor Features • True Two Phase Full Frame Architecture • TRUESENSE Transparent Gate Electrode Chip Size 38.60 mm (H) × 37.76 mm (V) Optical Fill Factor 100% Saturation Signal 100,000 electrons Output Sensitivity 13 mV/e− Dark Current (Accumulation Model) < 10 pA/cm2 Dark Current Doubling Rate 6°C Application Dynamic Range (Saturation Signal/Dark Noise) 76 dB • Scientific Imaging Quantum Efficiency (450, 550, 650 nm) 40%, 52%, 65% Maximum Date Rate 10 MHz Package CERDIP Package (Sidebrazed) Cover Glass Clear for High Sensitivity • Low Dark Current • High Output Sensitivity ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. NOTE: Parameters above are specified at T = 25°C unless otherwise noted. © Semiconductor Components Industries, LLC, 2015 October, 2017 − Rev. 4 1 Publication Order Number: KAF−16801/D KAF−16801 ORDERING INFORMATION Table 2. ORDERING INFORMATION − KAF−16801 IMAGE SENSOR Part Number Description Marking Code KAF−16801−AAA−DP−B1 Monochrome, No Microlens, CERDIP Package (Sidebrazed, CuW), Taped Clear Cover Glass (No Coatings), Grade 1 KAF−16801−AAA−DP−B2 Monochrome, No Microlens, CERDIP Package (Sidebrazed, CuW), Taped Clear Cover Glass (No Coatings), Grade 2 KAF−16801−AAA−DP−AE Monochrome, No Microlens, CERDIP Package (Sidebrazed, CuW), Taped Clear Cover Glass (No Coatings), Engineering Sample KAF−16801−AAA Serial Number Table 3. ORDERING INFORMATION − EVALUATION SUPPORT Part Number KEK−4H0082−KAF−160801−12−5 Description Evaluation Board (Complete Kit) See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAF−16801 DEVICE DESCRIPTION Architecture VRD fR VDD VOUT VSS SUB VOG ÄÄ ÄÄ ÄÄÄÄ ÄÄ ÄÄ ÄÄÄÄ ÄÄ ÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄ ÄÄ ÄÄÄÄ ÄÄ ÄÄ ÄÄÄÄ ÄÄ ÄÄ ÄÄ ÄÄ ÄÄÄÄ ÉÉÉÉ ÄÄ ÄÄ = Scavenging CCDs KAF−16801 Usable Active Image Area 4096 (H) × 4096 (V) 9.0 × 9.0 mm Pixels 4096 Active Pixels/Line 1 Buffer 20 Dark 1 Buffer 9 Dark 3 Invalid 1 Active (CTE Monitor) 11 Invalid Ä Ä Ä Ä Ä Ä Ä Ä Ä Ä Ä Ä Ä Ä Ä É 10 Dark Lines 1 Buffer (Active) Line fV1 fV2 1 Buffer (Active) Line 20 Dark Lines fH1 fH2 1 Active (CTE Monitor) 2 Invalid Figure 2. Block Diagram Dark Reference Pixels Surrounding the periphery of the device is a border of light shielded pixels. This includes 20 leading and 10 trailing pixels on every line excluding the inactive and photosensitive buffer pixels. There are also 20 full dark lines at the start of every frame and 10 full dark lines at the end of each frame. Under normal circumstances, these dark reference pixels do not respond to light. However, the pixels in close proximity to an active pixel can scavenge signal depending on light intensity and wavelength and therefore will not represent the true dark signal. The sensor consists of 4,127 parallel (vertical) CCD shift registers each 4,128 elements long. These registers act as both the photosensitive elements and as the transport circuits that allow the image to be sequentially read out of the sensor. The elements of these registers are arranged into a 4096 × 4096 photosensitive array surrounded by a light shielded dark reference of 29 columns and 30 rows. There is a buffer region of one photosensitive pixel surrounding the photosensitive region (one column at the beginning of a line, one column at the end of a line, one row at the beginning of a frame, and one row at the end of a frame). The parallel (vertical) CCD registers transfer the image one line at a time into a single 4,145 element (horizontal) CCD shift register. The horizontal register transfers the charge to a single output amplifier. The output amplifier is a three-stage source follower that converts the photo-generated charge to a voltage for each pixel. Output Structure Charge presented to the floating diffusion (FD) is converted into a voltage and current amplified in order to drive off-chip loads. The resulting voltage change seen at the output is linearly related to the amount of charge placed on www.onsemi.com 3 KAF−16801 Image Acquisition FD. Once the signal has been sampled by the system electronics, the reset gate (fR) is clocked to remove the signal and FD is reset to the potential applied by VRD. More signal at the floating diffusion reduces the voltage seen at the output pin. In order to activate the output structure, an off-chip load must be added to the VOUT pin of the device – see Figure 3. An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the sensor. These photon-induced electrons are collected locally by the formation of potential wells at each photogate or pixel site. The number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the pixel’s capacity is reached, excess electrons will leak into the adjacent pixels within the same column. This is termed blooming. During the integration period, the fV1 and fV2 register clocks are held at a constant (low) level. See Figure 8. Transfer Efficiency Test Pixels and Dummy Pixels At the beginning of each line and at the end of each line are extra horizontal CCD pixels. These are a combination of pixels that are not associated with any vertical CCD register and two that are associated with extra photo active vertical CCDs. The two extra photo active vertical CCDs are provided to give an accurate photo generated signal that can be used to monitor the charge transfer efficiency in the serial (horizontal) register. They are arranged as follows beginning with the first pixel in each line: • 11 Dark, Inactive Pixels • 1 Photoactive Test Pixel • 3 Inactive Pixels • 20 Dark Reference Pixels • 1 Active Buffer Pixel • 4,096 Photoactive Pixels • 1 Active Buffer Pixel • 9 Dark Reference Pixels • 1 Photoactive Test Pixel • 2 Inactive Pixels Charge Transport Referring again to Figure 8 − Timing Diagrams, the integrated charge from each photogate is transported to the output using a two-step process. Each line (row) of charge is first transported from the vertical CCDs to the horizontal CCD register using the fV1 and fV2 register clocks. The horizontal CCD is presented a new line on the falling edge of fV1 while fH2 is held high. The horizontal CCDs then transport each line, pixel by pixel, to the output structure by alternately clocking the fH1 and fH2 pins in a complementary fashion. On each falling edge of fH1 a new charge packet is transferred onto a floating diffusion and sensed by the output amplifier. Horizontal Register Output Structure +15 V 0.1 mF ~5ma VOUT 2N3904 or Equivalent Buffered Output R1 1 kW Notes: 1. For operation of up to 10 MHz. 2. The value of R1 depends on the desired output current according the following formula: R1 = 0.7 / IOUT. 3. The optimal output current depends on the capacitance that needs to be driven by the amplifier and the bandwidth required. 5 mA is recommended for capacitance of 12 pF and pixel rates up to 20 MHz. Figure 3. Output Structure Load Diagram www.onsemi.com 4 KAF−16801 Physical Description Pin Description and Device Orientation 34 fV2 VSUB 1 fV2 2 (4096, 4096) fV2 3 33 fV2 32 fV1 fV1 4 31 fV1 fV1 5 30 VSUB VGUARD 6 29 N/C N/C 7 28 N/C N/C 8 27 N/C N/C 9 26 N/C N/C 10 25 N/C VSUB 11 24 N/C VOG 12 23 N/C VDD 13 22 N/C VOUT 14 21 N/C 20 fH2 VSS 15 VRD 16 fR 17 Pixel (1, 1) 19 fH1 18 VSUB Figure 4. Pinout Diagram Table 4. PIN DESCRIPTION Pin Name Substrate (Ground) 18 VSUB fV2 Vertical CCD Clock − Phase 2 19 fH1 Horizontal CCD Clock − Phase 1 3 fV2 Vertical CCD Clock − Phase 2 20 fH2 Horizontal CCD Clock − Phase 2 4 fV1 Vertical CCD Clock − Phase 1 21 N/C No Connection (Open Pin) 5 fV1 Vertical CCD Clock − Phase 1 22 N/C No Connection (Open Pin) 6 VGUARD Guard Ring 23 N/C No Connection (Open Pin) 7 N/C No Connection (Open Pin) 24 N/C No Connection (Open Pin) 8 N/C No Connection (Open Pin) 25 N/C No Connection (Open Pin) 9 N/C No Connection (Open Pin) 26 N/C No Connection (Open Pin) 10 N/C No Connection (Open Pin) 27 N/C No Connection (Open Pin) 11 VSUB Substrate (Ground) 28 N/C No Connection (Open Pin) 12 VOG Output Gate 29 N/C No Connection (Open Pin) 13 VDD Amplified Supply 30 VSUB 14 VOUT Video Output 31 fV1 Vertical CCD Clock − Phase 1 15 VSS Amplifier Supply Returen 32 fV1 Vertical CCD Clock − Phase 1 16 VRD Reset Drain 33 fV2 Vertical CCD Clock − Phase 2 17 fR Reset Clock 34 fV2 Vertical CCD Clock − Phase 2 Pin Name 1 VSUB 2 Description www.onsemi.com 5 Description Substrate (Ground) Substrate (Ground) KAF−16801 IMAGING PERFORMANCE Table 5. TYPICAL OPERATIONAL CONDITIONS (All values measured at 25°C, and nominal operating conditions. These parameters exclude defective pixels.) Description Symbol Min. Nom. Max. − 90,000 − 100,000 200,000 180,000 100,000 − 250,000 Units Notes Verification Plan e−/pix 1 Design12 Saturation Signal Vertical CCD Capacity Horizontal CCD Capacity Output Node Capacity NSAT Photoresponse Non-Linearity PRNL − 1 2 % 2 Design12 Photoresponse Non-Uniformity PRNU − 1 3 % 3, 10 Die11 Dark Signal JDARK − − 18 3.5 50 10 e−/pix/sec pA/cm2 4 Die11 5 6.3 7.5 °C DSNU − 18 50 e−/pix/sec 5, 10 Die11 Dynamic Range DR 73 76 − dB 6 Design12 Charge Transfer Efficiency CTE 0.99997 0.99999 − Output Amplifier DC Offset VODC VRD − 3.0 VRD − 2.5 VRD − 2.0 V 7 Die11 Output Amplifier Bandwidth f−3dB − 140 − MHz 8 Design12 12.5 13 14 mV/e− Design12 ZOUT − 130 − W Design12 ne− − 15 20 electrons Dark Signal Doubling Temperature Dark Signal Non-Uniformity Output Amplifier Sensitivity Output Amplifier Output Impedance Noise Floor VOUT/Ne − Design12 Die11 9 Die11 1. For pixel binning applications, electron capacity up to 270,000 can be achieved with modified CCD inputs. Each sensor may have to be optimized individually for these applications. Some performance parameters may be compromised to achieve the largest signals. 2. Worst case deviation from straight line fit, between 1% and 90% of VSAT. 3. One Sigma deviation of a 128 × 128 sample when CCD illuminated uniformly. 4. Average of all pixels with no illumination at 25°C. 5. Average dark signal of any of 32 × 32 blocks within the sensor (each block is 128 × 128 pixels). 6. 20log (NSAT / ne−) at nominal operating frequency and 25°C. 7. Video level offset with respect to ground. 8. Assumes 10 pF off-chip load. 9. Output amplifier noise at 25°C, operating at pixel frequency up to 2 MHz, bandwidth = 20 MHz, tINT = 0, and no dark current shot noise. 10. Specification excludes region [1, 1, 400, 400]. See Dark Current Non-uniformity. 11. A parameter that is measured on every sensor during production testing. 12. A parameter that is quantified during the design verification activity. www.onsemi.com 6 KAF−16801 TYPICAL PERFORMANCE CURVES KAF−16801 Quantum Efficiency Absolute Quantum Efficiency 0.75 0.50 0.25 0 400 500 600 700 800 Wavelength (nm) Figure 5. Typical Spectral Response the output amplifier emitting light into the photoactive area (see Figure 9). The elevated dark signal in this region typically ranges from 30 e−/pix/sec to 100 e−/pix/sec, depending on the part, and is independent of temperature. If VDD is switched to 0 V at least 10 msec after the last pixel is read out, and switched back to full value 10 msec before the first pixel of the next frame, the effect of the amplifier glow will be eliminated (see Figure 10). Dark Current Non-Uniformity The photoresponse non-uniformity specification and the dark signal non-uniformity specification of the sensor both exclude the region that is [1, 1, 400, 400]. The reason for this exclusion is that when the sensor is running with VDD always on, and the integration times are greater than 100 msec, a non-uniformity will become evident surrounding the first pixel. This non-uniformity is a result of www.onsemi.com 7 KAF−16801 DEFECT DEFINITIONS Table 6. SPECIFICATIONS (All defect tests performed at T = 25°C) Classification Point Defects Cluster Defects Maximum Cluster Size Column Defects Maximum Column Width C1 ≤ 60 ≤8 8 4 1 C2 ≤ 120 ≤ 16 8 10 1 C3 ≤ 240 ≤ 32 15 20 2 Point Defects Dark: A pixel which deviates by more than 6% from neighboring pixels when illuminated to 70% of saturation. Bright: A pixel with a dark current > 7,000 e−/pixel/sec at 25°C. Neighboring Pixels The surrounding 128 × 128 pixels or ±64 columns/rows. Defect Separation Column and cluster defects are separated by no less than 2 pixels in any direction (excluding single pixel defects). Cluster Defect A grouping of not more than 5 adjacent point defects. Defect Region Exclusion Defect region excludes the outer 2 rows and columns at each side/end of the sensor. Column Defect A grouping of > 5 contiguous point defects along a single column. A column containing a pixel with dark current > 20,000 e−/pixel/sec. A column that does not meet the CTE specification for all exposures less than the specified Max sat. signal level and greater than 2 ke−. A column which contains a pixel that loses > 250 e− under 2 ke− illumination. 1, 4096 4096, 4096 1, 1 4096, 1 Figure 6. Active Pixel Region www.onsemi.com 8 KAF−16801 OPERATION Table 7. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Notes Diode Pin Voltages VDIODE 0 20 V 13, 14 Gate Pin Voltages − Type 1 VGATE1 −16 16 V 13, 15 Gate Pin Voltages − Type 2 VGATE2 0 16 V 13, 16 Inter-Gate Voltages VG−G − 16 V 17 Output Bias Current IOUT − −10 mA 18 CLOAD − 15 pF 18 T −50 70 °C RH 5 90 % Output Load Capacitance Storage Temperature Humidity 19 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 13. Referenced to pin VSUB. 14. Includes pins: VRD, VDD, VSS, VOUT, VGUARD. 15. Includes pins: fV1, fV2, fH1, fH2. 16. Includes pins: fR, VOG. 17. Voltage difference between overlapping gates. Includes: fV1 to fV2, fH1 to fH2, fV1 to fH2, fH1 to VOG. 18. Avoid shorting output pins to ground or any low impedance source during operation. 19. T = 25°C. Excessive humidity will degrade MTF. Table 8. DC BIAS OPERATING CONDITIONS Description Reset Drain Symbol Minimum Nominal Maximum Units Maximum DC Current (mA) VRD 11.0 12.0 12.25 V 0.01 Output Amplifier Return VSS 1.5 2.0 2.5 V 0.45 Output Amplifier Supply VDD 14.5 15.0 17.0 V IOUT Substrate VSUB 0 0 0 V 0.01 Output Gate VOG 4.5 5.0 5.2 V 0.01 Guard Ring VLG 9.0 10.0 12.0 V 0.01 Video Output Current IOUT −3.5 −5.0 −10.0 mA Notes 20 20. An output load sink must be applied to VOUT to activate output amplifier − see Figure 3. AC Operating Conditions Table 9. CLOCK LEVELS Symbol Level Minimum Nominal Maximum Units Effective Capacitance Vertical CCD Clock − Phase 1 fV1 Low −9.0 −8.5 −8.3 V 250 nF (All fV1 Pins) Vertical CCD Clock − Phase 1 fV1 High fV1 Low + 10.5 2.0 fV1 Low + 10.5 V 250 nF (All fV1 Pins) Vertical CCD Clock − Phase 2 fV2 Low −9.0 −8.5 −8.3 V 250 nF (All fV2 Pins) Vertical CCD Clock − Phase 2 fV2 High fV2 Low + 10.5 2.0 fV2 Low + 10.5 V 250 nF (All fV2 Pins) Horizontal CCD Clock − Phase 1 fH1 Low −2.5 −2.5 −1.8 V 500 pF Horizontal CCD Clock − Phase 1 fH1 High fH1 Low + 10.5 8.0 fH1 Low + 10.5 V 500 pF Horizontal CCD Clock − Phase 2 fH2 Low −2.5 −2.5 −1.8 V 300 pF Horizontal CCD Clock − Phase 2 fH2 High fH2 Low + 10.5 8.0 fH2 Low + 10.5 V 300 pF Reset Clock fR Low 3.0 5.0 5.5 V 10 pF Reset Clock fR High 9.5 10.0 10.5 V 10 pF Description 21. All pins draw less than 10 mA DC current. 22. Capacitance include gate to VSUB and gate to gate (fV1−fV2, fH1−fH2). www.onsemi.com 9 KAF−16801 TIMING Table 10. REQUIREMENTS AND CHARACTERISTICS Description Symbol Minimum Nominal Maximum Units Notes fH1, fH2 Clock Frequency fH − 8 15 MHz 23, 24, 25 fV1, fV2 Clock Frequency FV − 25 25 MHz 23, 24, 25 Pixel Period (1 Count) te 67 125 − ns fH1, fH2 Set-up Time tfHS 0.5 1 − ms fV1, fV2 Clock Pulse Width tfV 40 40 − ms tOVRLP 20 20 − ms tfR 10 20 − ns 26 tREADOUT 1,398 2,390 − ms 27 Integration Time tINT − − − Line Time tLINE 338.7 580 − fV1, fV2 Clock Pulse Overlap Reset Clock Width Readout Time 24 28 ms 29 23. 50% duty cycle values. 24. CTE may degrade above the nominal frequency. 25. Rise and fall times (10/90% levels) should be limited to 5−10% of clock period. Cross-over of register clocks should be between 40−60% of amplitude. 26. fR should be clocked continuously. 27. tREADOUT = (4128 ⋅ tLINE) 28. Integration time is user specified. Longer integration times will degrade noise performance. 29. tLINE = (2 ⋅ tfV ) − tOVRLP + tfHS + (4145 ⋅ te) + te. Frame Timing tINT tREADOUT 1 Frame = 4128 Lines fV1 fV2 Line 1 2 fH1 fH2 Figure 7. Frame Timing Diagram www.onsemi.com 10 4127 4128 KAF−16801 Line Timing and Pixel Timing Line Timing Detail 1 Line fV1 tfV tfVovrlp fV2 te tfHS fH2 fH1 4145 Counts fR Pixel Timing Detail tfR fR fH1 te 1 Count fH2 VPIX VOUT VDARK VODC VSUB VSAT Figure 8. Line Timing and Pixel Timing www.onsemi.com 11 KAF−16801 Figure 9. Amplifier Glow − S11LE @-20C with 20 sec Integration @1 MHz VDD always ON (+15) Figure 10. Amplifier Glow − S11LE @-20C with 20 sec Integration @1 MHz VDD OFF during Integration NOTE: Amplifier glow is suppressed by switching VDD to 0 V during integration. www.onsemi.com 12 KAF−16801 STORAGE AND HANDLING Table 11. STORAGE CONDITIONS Description Symbol Minimum Maximum Units Notes Storage Temperature TST −20 100 °C 30 Operating Temperature TOP −60 60 °C 30. Storage toward the maximum temperature will accelerate microlens degradation. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. www.onsemi.com 13 KAF−16801 MECHANICAL INFORMATION Completed Assembly Figure 11. Completed Assembly (1 of 2) www.onsemi.com 14 KAF−16801 Figure 12. Completed Assembly (2 of 2) www.onsemi.com 15 KAF−16801 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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