KAF-18500-NXA-JH-AE-08

KAF-18500 5270 (H) x 3516 (V) Full Frame CCD Image Sensor Description The KAF−18500 is a dual output, high performance color CCD (charge coupled device) image sensor with 5270 (H) x 3516 (V) photoactive pixels designed for a wide range of color image sensing applications including digital imaging. Each pixel contains anti−blooming protection by means of a lateral overflow drain thereby preventing image corruption during high light level conditions. Each of the 6.8 mm square pixels are selectively covered with red, green or blue pigmented filters for color separation. Microlenses are added for improved sensitivity. The sensor utilizes the TRUESENSE Transparent Gate Electrode to improve sensitivity compared to the use of a standard front side illuminated polysilicon electrode. www.onsemi.com Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Figure 1. KAF−18500 CCD Image Sensor Architecture Full Frame CCD with Square Pixels Total Number of Pixels 5422 (H) x 3610 (V) = 19.6 M Features Number of Effective Pixels 5310 (H) x 3556 (V) = 18.8 M • TRUESENSE Transparent Gate Electrode Number of Active Pixels 5270 (H) x 3516 (V) = 18.5 M • • • • for High Sensitivity High Resolution, 35 mm Format Broad Dynamic Range Low Noise Large Image Area Pixel Size 6.8 mm (H) x 6.8 mm (V) Imager Size 43.1 mm (diagonal), 35 mm Optical format Chip Size 37.8 mm (H) x 26.4 mm (V) Aspect Ratio 3:2 Saturation Signal 42 ke− Applications Charge to Voltage Conversion 25 mV/e− Quantum Efficiency (RGB) 30%, 45%, 40% • Digital Still Cameras Read Noise (f = 24 MHz) 15.7 e− Dark Signal (T = 60°C) 50 pA/cm2 Dark Current Doubling Temperature 5.3°C Linear Dynamic Range (f = 24 MHz, T = 60°C) 68.1 dB Charge Transfer Efficiency (HCTE/VCTE) 0.999995 0.999998 Blooming Protection (4 ms exposure time) 5600 X saturation exposure Maximum Data Rate 24 MHz Readout Mode Dual Output Only Package PGA Cover Glass AR coated (S8612) ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. NOTE: Unless otherwise noted, all parameters above are specified at T = 20°C to 25°C. © Semiconductor Components Industries, LLC, 2015 April, 2015 − Rev. 2 1 Publication Order Number: KAF−18500/D KAF−18500 ORDERING INFORMATION Table 2. ORDERING INFORMATION Part Number Description KAF−18500−NXA−JH−AA−08 Special Color, Aperture, Enhanced, ESD, LOD, Microlens, Sealed IR Cover Glass, 0.8 mm glass KAF−18500−NXA−JH−AE−08 Special Color, Aperture, Enhanced, ESD, LOD, Microlens, Sealed IR Cover Glass, 0.8 mm glass [Engineering Grade] Marking Code KAF−18500−NXA−08 See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAF−18500 DEVICE DESCRIPTION Architecture Figure 2. Block Diagram Image Acquisition Dark Reference Pixels Surrounding the periphery of the device is a border of light shielded pixels creating a dark region. Within this dark region, exist light shielded pixels that include 36 leading dark pixels on every line. There are also 30 full dark lines at the start and 23 full dark lines at the end of every frame. Under normal circumstances, these pixels do not respond to light and may be used as a dark reference. An electronic representation of an image is formed when incident photons falling on the sensor plane create electron−hole pairs within the device. These photon−induced electrons are collected locally by the formation of potential wells at each photogate or pixel site. The number of electrons collected is linearly dependent on light level and exposure time and non−linearly dependent on wavelength. When the pixel’s capacity is reached, excess electrons are discharged into the lateral overflow drain to prevent crosstalk or ‘blooming’. During the integration period, the V1 and V2 register clocks are held at a constant (low) level. Dummy Pixels Within each horizontal shift register there are 20 leading additional shift phases required before the dark reference pixels: (1 + 8 + 5 + 1 + 5) (See Figure 2). These pixels are designated as dummy pixels and should not be used to determine a dark reference level. Charge Transport The integrated charge from each photogate (pixel) is transported to the output using a two−step process. Each line (row) of charge is first transported from the vertical CCD’s to a horizontal CCD register using the V1 and V2 register clocks. The horizontal CCD is presented with a new line on the falling edge of V2 while H1 is held high. The horizontal CCD’s then transport each line, pixel by pixel, to the output structure by alternately clocking the H1 and H2 pins in a complementary fashion. A separate connection to the last H1 phase (H1L) is provided to improve the transfer speed of charge to the floating diffusion output amplifier. On each falling edge of H1L a new charge packet is dumped onto a floating diffusion and sensed by the output amplifier. Active Buffer Pixels Forming the outer boundary of the effective active pixel region, there are 20 unshielded active buffer pixels between the photoactive area and the dark reference. These pixels are light sensitive but they are not tested for defects and non−uniformities. For the leading 20 active column pixels, the first 4 pixels are covered with blue pigment while the remaining are arranged in a Bayer pattern (R, GR, GB, B). www.onsemi.com 3 KAF−18500 HORIZONTAL REGISTER Output Structure H2 H1 HCCD Charge Transfer VDD H1L OG RG RD Floating Diffusion VOUTX X= L or R VSS Source Follower #1 Source Follower #2 Source Follower #3 Figure 3. Output Architecture (Left or Right) the reset gate (RG) is clocked to remove the signal and FD is reset to the potential applied by reset drain (RD). Increased signal at the floating diffusion reduces the voltage seen at the output pin. To activate the output structures, an off−chip current source must be added to the VOUT pins of the device. See Figure 4. The output consists of a floating diffusion capacitance connected to a three−stage source follower. Charge presented to the floating diffusion (FD) is converted into a voltage and is current amplified in order to drive off−chip loads. The resulting voltage change seen at the output is linearly related to the amount of charge placed on the FD. Once the signal has been sampled by the system electronics, www.onsemi.com 4 KAF−18500 Output Load VDD = +15 V Iout = 5 mA 0.1 μF VOUT 2N3904 or Equiv. 140 W 1 kW Buffered Video Output Note: Component values may be revised based on operating conditions and other design considerations. Figure 4. Typical Output Structure Load Diagram www.onsemi.com 5 KAF−18500 PHYSICAL DESCRIPTION Pin Description and Device Orientation VSUB D 1 C 1 V1 VL NC 2 3 4 5 6 7 3 4 5 6 7 2 V1 V2 NC V2 V1 VSUB LODT LODT VSUB VSUB 8 D 8 V2 V1 C KAF−18500 LODB OGL RDL VOUTL H2 H1 B NC 1 2 3 4 5 6 7 A 1 2 3 4 5 6 7 VDDL H2 VSUB NC H1LL RGL VSSL VSUB VSUB H1 H2 VOUTR RDR OGR LODB 8 9 10 11 12 13 14 15 16 8 9 10 11 12 13 14 15 16 H1 H1 H2 VDDR VSSR RGR H1LR NC NC B A VSUB Top View Figure 5. Pinout Diagram − Top View Table 3. PGA GRID ROW A Pin Name 1 VSUB 2 NC 3 Table 4. PGA GRID ROW B Description Pin Name Substrate 1 NC Physical pin with no connection on die 2 LODB H1LL Horizontal Phase 1, last phase, left side 3 OGL Output Gate, left side 4 RGL Reset Drain, left side 4 RDL Reset Gate, left side 5 VSSL Output Amplifier Return, left side 5 VOUTL 6 VDDL Output Amplifier Supply, left side 6 H2 Horizontal Phase 2 7 H2 Horizontal Phase 2 7 H1 Horizontal Phase 1 8 H1 Horizontal Phase 1 8 VSUB Substrate 9 H1 Horizontal Phase 1 9 VSUB Substrate 10 H2 Horizontal Phase 2 10 H1 Horizontal Phase 1 11 VDDR Output Amplifier Supply, right side 11 H2 Horizontal Phase 2 12 VSSR Output Amplifier Return, right side 12 VOUTR Video Output, right side 13 RGR Reset Gate, right side 13 RDR Reset Drain, right side 14 H1LR Horizontal Phase 1, last phase, right side 14 OGR Output Gate, right side 15 NC Physical pin with no connection on die 15 LODB Lateral Overflow Drain, bottom 16 VSUB Substrate 16 NC www.onsemi.com 6 Description Physical pin with no connection on die Lateral Overflow Drain, bottom Video Output, left side Physical pin with no connection on die KAF−18500 Table 5. PGA GRID ROW C Table 6. PGA GRID ROW D Pin Name Pin Name 1 V1 Vertical Phase 1 Description 1 VSUB Description 2 V2 Vertical Phase 2 2 V1 Vertical Phase 1 3 LODT Lateral Overflow Drain, top 3 V2 Vertical Phase 2 4 VSUB Substrate 4 NC Physical pin with no connection on die 5 VSUB Substrate 5 NC Physical pin with no connection on die 6 LODT Lateral Overflow Drain, top 6 V2 Vertical Phase 2 7 V2 Vertical Phase 2 7 V1 Vertical Phase 1 8 V1 Vertical Phase 1 8 VSUB Substrate Substrate IMAGING PERFORMANCE Table 7. TYPICAL OPERATIONAL CONDITIONS Description Condition Frame time (treadout + tint) Varies, see below Readout time (treadout) 527 ms Integration time (tint) Varies per test: Bright Field 250 ms, Dark Field 1 sec, Saturation 250 ms, Low light 33 ms Horizontal clock frequency 24 MHz Temperature 20 − 25°C Mode integrate – readout cycle Operation Nominal operating voltages and timing with min. vertical pulse width tVw = 11 ms Notes Includes overclock pixels Room temperature www.onsemi.com 7 KAF−18500 Table 8. SPECIFICATIONS Description Symbol Min Nom. Units Notes Verification Plan Vsat Ne−sat Q/V 900 (35000) 1086 42000 25.6 mV e− mV/e− 1, 19 die17 design18 design18 Rr Rg Rb 30 45 40 % High Level Photoresponse Non−Linearity Le_High 2 10 % 2 die17 Low Level Photoresponse Non−Linearity Le_Low 2 10 % 2 die17 PRNU 4.5 25 %p−p 3 die17 Vdark, int 4 10 mV/s 4, 16 die17 Vdark, read 12 20 mV/s 15, 16 die17 DSNU 0.5 4 mV p−p 5 die17 Dark Signal Doubling Temperature ΔT 5.3 °C design18 Read Noise NR 15.7 e− rms design18 Total Noise N 18.9 e− rms 6 design18 Linear Dynamic Range DR 68.1 dB 7 design18 Red−Green Hue Shift Blue−Green Hue Shift RGHueUnif BGHueUnif 1.8 % 8 die17 9 die17 Saturation Signal Peak Quantum Efficiency red green blue Photo Response Non−Uniformity each color plane Integration Dark Signal Readout Dark Signal Dark Signal Non−Uniformity Horizontal Charge Transfer Efficiency HCTE 0.999995 0.999995 Vertical Charge Transfer Efficiency VCTE 0.999999 0.999999 Blooming Protection Xab DC Offset, output amplifier Vodc Output Amplifier Bandwidth f−3dB Output Impedance, Amplifier ROUT Max 12 die17 5600 6.0 8 9.5 232 100 design18 x Vsat 10 design18 V 11 die17 MHz 12 design18 die17 137 300 W 20 mV 13 die17 V 14 design18 Hclk Feedthru Vhft 3.7 Reset Feedthru Vrft 0.5 1. Increasing output load currents to improve bandwidth will decrease the conversion factor (Q/V). 2. Worst case deviation (from 10 mV to Vsat min), relative to a linear fit applied between 0 and 85% of Vsat min. 3. Difference between the maximum and minimum average signal levels of 148 x 148 blocks within the sensor on a per color basis as a % of average signal level. 4. T = 60°C. Average non−illuminated signal with respect to over−clocked vertical register signal. 5. T = 60°C. Absolute difference between the maximum and minimum average signal levels of 148 x 148 blocks within the sensor. 6. rms deviation of a multi−sampled pixel measured in the dark including amplifier and system noise sources. 7. 20log (0.95 * Vsat/VN). Specified at T = 60°C. 8. Gradual variations in hue (red with respect to green pixels and blue with respect to green pixels) in regions of interest (148 x 148 blocks) within the sensor. 9. Measured per transfer at Vsat min. Typically, no degradation in CTE is observed up to 24 MHz. 10. Xab is the number of times above the Vsat illumination level that the sensor will bloom by spot size doubling. The spot size is 10% of the imager height. Xab is measured at 4 ms. 11. Video level offset with respect to ground. 12. Last stage only. Assumes 5 pF off−chip load. 13. Amount of artificial signal due to H1 coupling. 14. Amplitude of feedthrough pulse in VOUT due to RG coupling. 15. T = 60°C. Average non−illuminated signal collected due to the read out time. 16. Total dark signal = (Vdark,int x tint) + (Vdark,read x treadout). 17. A parameter that is measured on every sensor during production testing. 18. A parameter that is quantified during the design verification activity. 19. Specified at T = 60°C. www.onsemi.com 8 KAF−18500 TYPICAL PERFORMANCE CURVES KAF−18500 Quantum Efficiency with S8612 (IR−cut) with MAR coating @ 0.8um thickness 0.5 0.45 0.4 Absolute QE 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 350 400 450 500 550 600 650 700 750 800 Wavelength Figure 6. Typical Quantum Efficiency KAF−18500 Green Pixel Response Difference GR − GB Absolute QE Difference 0.02 0.015 0.01 0.005 0 −0.005 −0.01 −0.015 −0.02 350 400 450 500 550 600 650 Wavelngth (nm) Figure 7. Typical GR−GB QE Difference www.onsemi.com 9 700 750 800 KAF−18500 Normalized QE Angle QE about diagonal (BLUE light BLUE pixel) Slash Angle Figure 8. Typical Normalized Angle QE Anti−blooming Performance KAF−18500 Anti−blooming Performance Integration Time (ms) Figure 9. Typical Anti Blooming Performance www.onsemi.com 10 KAF−18500 DEFECT DEFINITIONS Operating Conditions All defect tests performed at: Table 9. OPERATING CONDITIONS Description Condition Integration time (tint) Notes Varies per test: Bright Field 250 ms, Dark Field 1 sec, Saturation 250 ms, Low light 33 ms Horizontal clock frequency 24 MHz Temperature 20 − 25°C Room temperature Table 10. SPECIFICATIONS Classification Standard Grade Points Clusters, small and large Clusters, large Columns Includes Dead Columns ≤ 4400 ≤ 50 ≤5 ≤ 15 yes Column Defect A grouping of more than 10 point defects along a single column −or− A column that deviates by more than 0.9 mV above or below neighboring columns under non−illuminated conditions. −or− A column that deviates by more than 1.5% above or below neighboring columns under illuminated conditions. Column and cluster defects are separated by at least 4 good columns in the x direction. No multiple column defects (double or more) will be permitted. Point Defects A pixel that deviates by more than 9 mV above neighboring pixels under non−illuminated conditions. −or− A pixel that deviates by more than 7% above or 11% below neighboring pixels under illuminated conditions. Cluster Defect Small clusters: A grouping of adjacent point defects that can number in size from 2 to 10 pixels. Large clusters: A grouping of more than 10 pixels but not larger than 20 adjacent point defects. A single large cluster is not to exceed 5 adjacent pixels within the same color plane. Dead Columns A column that deviates by more than 50% below neighboring columns under illuminated conditions. Cluster Separation Cluster defects are separated by no less than 4 good pixels in any direction. Saturated Columns A column that deviates by more than 100 mV above neighboring columns under non−illuminated conditions. No saturated columns are allowed. www.onsemi.com 11 KAF−18500 OPERATION Table 11. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Notes Diode Pin Voltages Vdiode –0.5 +17.5 V 1, 2 Gate Pin Voltages Vgate1 −13.5 +13.5 V 1, 3 V1−2 −13.5 +13.5 V 4, 5 Gate−Gate Voltages Output Bias Current Iout −30 mA 6 LOD Diode Voltage VLODT −0.5 +13.0 V 7 TOP 0 60 °C 8 Operating Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Referenced to pin SUB. 2. Includes pins: RD, VDD, VSS, VOUT. 3. Includes pins: V1, V2, H1, H1L, H2, RG, OG. 4. Voltage difference between overlapping gates. Includes: V1 to V2; H1, H1L to H2; H1L to OG; V1 to H2. These inputs contain an ESD protection circuit. Exceeding the maximum voltages will cause an uncontrolled current to flow in these circuits and may damage the input pin. 5. Voltage difference between non−overlapping gates. Includes: V1 to H1, H1L; V2, OG to H2. These inputs contain an ESD protection circuit. Exceeding the maximum voltages will cause an uncontrolled current to flow in these circuits and may damage the input pin. 6. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher currents and lower load capacitance at the expense of reduced gain (sensitivity). Operation at the maximum values will reduce Mean Time to Failure (MTTF). 7. V1, H1, V2, H2, H1L, OG, and RD are tied to 0 V. 8. Noise performance will degrade at higher temperatures. 9. Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or condition is exceeded, the device will be degraded and may be damaged. Power−up Sequence The sequence chosen to perform an initial power−up is not critical for device reliability. A coordinated sequence may minimize noise and the following sequence is recommended: 1. Connect the ground pins (SUB). 2. Supply the appropriate biases and clocks to the remaining pins. Table 12. DC BIAS OPERATING CONDITIONS Symbol Minimum Nominal Maximum Units Maximum DC Current (mA) Reset Drain RD 11.3 11.5 11.7 V IRD = 0.01 Output Amplifier Return VSS 0.5 0.7 1.0 V ISS = 3.0 Output Amplifier Supply VDD 14.5 15.0 15.5 V IOUT + ISS Substrate SUB V 0.01 Output Gate OG −2.2 −2.0 −1.8 V 0.01 Lateral Overflow Drain LOD 9.8 10.0 10.2 V 0.01 Video Output Current IOUT −5 −10 mA Description 0 1. An output load sink must be applied to VOUT to activate output amplifier – see Figure 4. www.onsemi.com 12 Notes 1 KAF−18500 AC Operating Conditions Table 13. CLOCK LEVELS Symbol Level Minimum Nominal Maximum Units Effective Capacitance Notes V1 Low Level V1L Low −9.2 −9.0 −8.8 V 245 nF 1, 2 V1 High Level V1H High 2.3 2.5 2.7 V 245 nF 1, 2 V2 Low Level V2L Low −9.2 −9.0 −8.8 V 303 nF 1, 2 V2 High Level V2H High 2.3 2.5 2.7 V 303 nF 1, 2 H1, H2 (amplitude) H1amp H2amp Amplitude 6.5 6.75 7.0 V See below H1 Low Level H1Low Low −4.7 −4.5 −4.3 V 460 pF 1 H2 Low Level H2Low Low −5.2 −5.0 −4.8 V 302 pF 1 H1L Low Level H1Llow Low −6.7 −6.5 −6.3 V 15 pF 1 H1L High Level H1Lhigh High 1.3 1.5 1.7 V 15 pF 1 RG Low Level RGL Low 0.3 0.5 0.7 V 21 pF 1 RG High Level RGH High 7.8 8.0 8.2 V 21 pF 1 Description 1. All pins draw less than 10 mA DC current. Capacitance values relative to SUB (substrate). 2. Clock capacitance is the effective capacitance extrapolated from the rise and fall time measured while operating the sensor. www.onsemi.com 13 KAF−18500 TIMING Table 14. REQUIREMENTS AND CHARACTERISTICS Description Symbol Minimum Nominal Maximum Units Notes H1, H2 Clock Frequency fH 24 MHz 1, 2 V1, V2 Clock Frequency fV 45.5 kHz 1, 2 H1, H2 Rise, Fall Times tH1r, tH1f 5 10 % 3, 7 V1, V2 Rise, Fall Times tV1r, tV1f 5 10 % 3 V1 − V2 Cross−over VVCR 1 H1 − H2 Cross−over VHCR −3.0 VH1LCR −2.0 tHS 1 H1L Rise − H2 Fall Crossover H1, H2 Setup Time RG Clock Pulse Width tRGw 5 tRGr, tRGf 5 V1, V2 Clock Pulse Width tVw Flush Clock Off Time Pixel Period (1 Count) RG Rise, Fall Times H1L − VOUT Delay V V 1.0 V ns 4 % 3 11 ms 2, 6 toff 4 ms 2, 6 te 42 ns 2 5 5 treadout 505 ns ns ms Integration Time tint Line Time tline 140 ms Fast Flush Time tflush 88 ms 1. 2. 3. 4. 5. 6. 7. 8. 9. 9 ms 10 tRV Readout Time 0 5 tHV RG − VOUT Delay −1.5 6, 8 5, 6 50% duty cycle values. CTE will degrade above the nominal frequency. Relative to the pulse width (based on 50% of high/low levels). RG should be clocked continuously. Integration time is user specified. Longer times will degrade noise performance. The maximum specification or 10 nsec whichever is greater based on the frequency of the horizontal clocks. treadout = tline * 3610 lines The charge capacity near the output could be degraded if the voltage at the clock cross over point is outside this range. Edge Alignment H1 VHCR V1 V2 VVCR V1,V2 Figure 10. Timing Edge Alignment www.onsemi.com 14 6 KAF−18500 Frame Timing 1 Frame = 3610 Lines t readout t int V2 Line V1 1 2 3 3609 3610 H2 H1, H1L Figure 11. Frame Timing Frame Timing Detail 90% V1 10% tVw tV1f tV1r 90% V2 10% tV2r tV2f Figure 12. Frame Timing Detail Line Timing (Each Output) ÄÇ ÄÇ ÄÇ Line Timing Detail t line V2 V1 H2 tV t HS te tV ÄÄ ÄÄ 2711 Line Content 2635 Active Pixels/Line 77 − 2711 57− 76 21− 56 1 − 20 Dummy Pixels H1, H1L Dark Reference Pixels* RG Figure 13. Line Timing www.onsemi.com 15 H1 / H2 count values ÇÇ ÇÇ Active Buffer Pixels Photoactive Pixels ** KAF−18500 Pixel Timing Pixel Timing Detail t RG te 1 Count RG H1,H1L H2 t RV tHV Vdark+Voft VOUTX X=L or R Vodc VRG VSUB Vsat Figure 14. Pixel Timing www.onsemi.com 16 KAF−18500 Pixel Timing Detail 90 RG t RGw RGH 10 RGL t RGf t RGr 90 H1, H2 H1L, H2 L 50 H1 , H2 amp amp 10 te 2 t t H12 H12f 90 H1L 50 H1 high 10 H1Low t e 2 t t H1Lr H1Lf Figure 15. Pixel Timing Detail MODE OF OPERATION Power−up Flush Cycle tint tVflush V2 V1 3610 (min) H2 2711 H1,H1L Figure 16. Power−up Flush Cycle www.onsemi.com 17 treadout KAF−18500 STORAGE AND HANDLING For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. www.onsemi.com 18 KAF−18500 MECHANICAL INFORMATION Completed Assembly Figure 17. Completed Assembly Drawing www.onsemi.com 19 KAF−18500 Cover Glass Specification MAR Coated−IR Absorbing Cover Glass 1. Dust/Scratch/Digs/Defects: 20 micron max 2. Substrate material: Schott S8612 whose performance is as published and specifications controlled by Schott, North America. The cover glass supplied for this device is as shown in Figure 17. Data supplied in the graph below is a typical transmission of the AR coated material at 0.8 mm thickness. S8612 with MAR coating (0.8mm) Transmission 100 90 80 70 %T 60 50 40 30 20 10 0 200 300 400 500 600 700 800 900 Wavelength (nm) Figure 18. Cover Glass Substrate Transmission 3. Multilayer anti−reflective coating on two sides: Two−sided reflectance: Table 15. Wavelength Transmission 420 − 450 nm < 2% 450 − 630 nm < 1% 630 − 680 nm < 2% ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 20 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative KAF−18500/D