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KAI-16070
4864 (H) x 3232 (V)
Interline CCD Image Sensor
Description
The KAI−16070 Image Sensor is a 16−megapixel CCD in a 35 mm
optical format. Based on the TRUESENSE 7.4 micron Interline
Transfer CCD Platform, the sensor provides very high smear rejection
and up to 82 dB linear dynamic range through the use of a unique
dual−gain amplifier. Flexible readout architecture enables use of 1, 2,
or 4 outputs for full resolution readout up to 8 frames per second,
while a vertical overflow drain structure suppresses image blooming
and enables electronic shuttering for precise exposure control.
The sensor is available with the TRUESENSE Sparse Color Filter
Pattern, a technology which provides a 2x improvement in light
sensitivity compared to a standard color Bayer part.
The sensor shares common pin−out and electrical configurations
with a full family of ON Semiconductor Interline Transfer CCD image
sensors, allowing a single camera design to be leveraged in support of
multiple devices.
www.onsemi.com
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Typical Value
Interline CCD; Progressive Scan
4932 (H) x 3300 (V)
4888 (H) x 3256 (V)
4864 (H) x 3232 (V) (15.7 M)
7.4 mm (H) x 7.4 mm (V)
36.0 mm (H) x 23.9 mm (V)
43.2 mm (diag.) 35 mm Optical Format
3:2
1, 2, or 4
44,000 electrons
9.7 mV/e− (low), 33 mV/e− (high)
Aspect Ratio
Number of Outputs
Charge Capacity
Output Sensitivity
Quantum Efficiency
Mono (−AAA)
10%
Mono (−AXA, −PXA, −QXA)
48%
R, G, B (−CXA)
32%, 41%, 39%
R, G, B (−FXA)
33%, 40%, 40%
Base ISO
−AXA
350
−CXA, −PXA
130, 310 (respectively)
−FXA, −PXA
130, 310 (respectively)
Read Noise (f = 40 MHz)
12 electrons rms
Dark Current
Photodiode / VCCD
1 / 145 electrons/s
Dark Current Doubling Temp.
Photodiode / VCCD
7°C / 9°C
Dynamic Range
High Gain Amp (40 MHz)
70 dB
Dual Amp, 2x2 Bin (40 MHz)
82 dB
Charge Transfer Efficiency
0.999999
Blooming Suppression
> 1000 X
Smear
−115 dB
Image Lag
< 10 electrons
Maximum Pixel Clock Speed
40 MHz
Maximum Frame Rates
Quad / Dual / Single Output
8 / 4 / 2 fps
Package
72 pin PGA
Cover Glass
AR Coated, 2 Sides or Clear Glass
NOTE: All parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
November, 2016 − Rev. 4
1
Figure 1. KAI−16070 CCD Image Sensor
Features
• Superior Smear Rejection
• Up to 82 dB Linear Dynamic Range
• Bayer Color Pattern, TRUESENSE Sparse
•
•
•
•
Color Filter Pattern, and Monochrome
Configurations
Progressive Scan & Flexible Readout
Architecture
High Frame Rate
High Sensitivity − Low Noise Architecture
Package Pin Reserved for Device
Identification
Applications
• Industrial Imaging and Inspection
• Traffic
• Aerial Photography
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Publication Order Number:
KAI−16070/D
KAI−16070
ORDERING INFORMATION
Table 2. ORDERING INFORMATION
Part Number
Description
KAI−16070−AAA−JP−B1
Monochrome, No Microlens, PGA Package, Taped Clear Cover
Glass, no coatings, Standard Grade
KAI−16070−AAA−JP−AE
Monochrome, No Microlens, PGA Package, Taped Clear Cover
Serial Number Glass, no coatings, Engineering Grade
KAI−16070−AXA−JD−B1
Monochrome, Special Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides), Grade 1
KAI−16070−AXA−JD−B2
Monochrome, Special Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides), Grade 2
KAI−16070−AXA−JD−AE
Monochrome, Special Microlens, PGA Package, Sealed Clear
Cover Glass with AR coating (both sides), Engineering Grade
KAI−16070−FXA−JD−B1
Gen2 Color (Bayer RGB), Special Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides), Grade 1
KAI−16070−FXA−JD−B2
Gen2 Color (Bayer RGB), Special Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides), Grade 2
KAI−16070−FXA−JD−AE
Gen2 Color (Bayer RGB), Special Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides),
Engineering Grade
KAI−16070−QXA−JD−B1
Gen2 Color (TRUESENSE Sparse CFA), Special Microlens, PGA
Package, Sealed Clear Cover Glass with AR coating (both
sides), Grade 1
KAI−16070−QXA−JD−B2
Gen2 Color (TRUESENSE Sparse CFA), Special Microlens, PGA
Package, Sealed Clear Cover Glass with AR coating (both
sides), Grade 2
KAI−16070−QXA−JD−AE
Gen2 Color (TRUESENSE Sparse CFA), Special Microlens, PGA
Package, Sealed Clear Cover Glass with AR coating (both
sides), Engineering Grade
KAI−16070−CXA−JD−B1*
Gen1 Color (Bayer RGB), Special Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides), Grade 1
KAI−16070−CXA−JD−B2*
Gen1 Color (Bayer RGB), Special Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides), Grade 2
KAI−16070−CXA−JD−AE*
Gen1 Color (Bayer RGB), Special Microlens, PGA Package,
Sealed Clear Cover Glass with AR coating (both sides),
Engineering Grade
KAI−16070−PXA−JD−B1*
Gen1 Color (TRUESENSE Sparse CFA), Special Microlens,
PGA Package, Sealed Clear Cover Glass with AR coating (both
sides), Grade 1
KAI−16070−PXA−JD−B2*
Gen1 Color (TRUESENSE Sparse CFA), Special Microlens,
PGA Package, Sealed Clear Cover Glass with AR coating (both
sides), Grade 2
KAI−16070−PXA−JD−AE*
Gen1 Color (TRUESENSE Sparse CFA), Special Microlens,
PGA Package, Sealed Clear Cover Glass with AR coating (both
sides), Engineering Grade
Marking Code
KAI−16070−AAA
Serial Number
KAI−16070−AXA
Serial Number
KAI−16070−FXA
Serial Number
KAI−16070−QXA
Serial Number
KAI−16070−CXA
Serial Number
KAI−16070−PXA
Serial Number
*Not recommended for new designs.
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
www.onsemi.com
2
KAI−16070
DEVICE DESCRIPTION
Architecture
1 10 22 12
8
H2Bd
H2Sd
H1Bd
H1Sd
FDGcd
Rc
VDDc
VOUTc
SUB
FDGcd
H2Bc
H2Sc
H1Bc
H1Sc
RDc
R2cd
2432
2432
RDd
R2cd
DevID
Rd
VDDd
VOUTd
12
8 22 10 1
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
FLD
22
12
GND
OGc
H2SLc
V1T
V2T
V3T
V4T
V1T
V2T
V3T
V4T
ESD
4864H x 3232V
7.4 mm x 7.4 mm Pixels
22 12
12 22
V1B
V2B
V3B
V4B
RDa
R2ab
Ra
VDDa
VOUTa
GND
OGd
H2SLd
ESD
V1B
V2B
V3B
V4B
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
12 Buffer
22 Dark
(Last VCCD Phase = V1 → H1S)
FLD
1 10 22 12
8
2432
H2Bb
H2Sb
H1Bb
H1Sb
FDGab
SUB
FDGab
H2Ba
H2Sa
H1Ba
H1Sa
GND
OGa
H2SLa
2432
12
8 22 10 1
RDb
R2ab
Rb
VDDb
VOUTb
GND
OGb
H2SLb
Figure 2. Block Diagram
Dark Reference Pixels
Active Buffer Pixels
There are 22 dark reference rows at the top and 22 dark
rows at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 22 dark columns on the left or right side of the
image sensor as a dark reference.
Under normal circumstances use only the center 20
columns of the 22 column dark reference due to potential
light leakage.
12 unshielded pixels adjacent to any leading or trailing
dark reference regions are classified as active buffer pixels.
These pixels are light sensitive but are not tested for defects
and non−uniformities.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron−hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non−linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
Dummy Pixels
Within each horizontal shift register there are 11 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level.
In addition, there is one dummy row of pixels at the top
and bottom of the image.
www.onsemi.com
3
KAI−16070
ESD Protection
power−down sequences may cause damage to the sensor.
See Power−Up and Power−Down Sequence section.
Adherence to the power−up and power−down sequence is
critical. Failure to follow the proper power−up and
Bayer Color Filter Pattern
H2Bd
H2Sd
H1Bd
H1Sd
FDGcd
SUB
FDGcd
H2Bc
H2Sc
H1Bc
H1Sc
RDc
R2cd
RDd
R2cd
DevID
Rc
VDDc
VOUTc
1 10 22 12
8
2432
2432
Rd
VDDd
VOUTd
12
8 22 10 1
FLD
22
12
GND
OGc
H2SLc
BG
G R
V1T
V2T
V3T
V4T
ESD
4864H x 3232V
7.4 mm x 7.4 mm Pixels
V1T
V2T
V3T
V4T
12 22
1 10 22 12
8
2432
RDb
R2ab
Rb
VDDb
VOUTb
12
8 22 10 1
GND
OGb
H2SLb
H2Bb
H2Sb
H1Bb
H1Sb
FDGab
SUB
FDGab
H2Ba
H2Sa
H1Ba
H1Sa
GND
OGa
H2SLa
2432
ESD
V1B
V2B
V3B
V4B
BG
G R
12 Buffer
22 Dark
(Last VCCD Phase = V1 → H1S)
FLD
BG
G R
RDa
R2ab
Ra
VDDa
VOUTa
BG
G R
22 12
V1B
V2B
V3B
V4B
GND
OGd
H2SLd
Figure 3. Bayer Color Filter Pattern
TRUESENSE Sparse Color Filter Pattern
2432
1 10 22 12
8
Rd
VDDd
VOUTd
12
8 22 10 1
FLD
22
12
G
P
B
P
V1T
V2T
V3T
V4T
ESD
P
G
P
B
R
P
G
P
GND
OGd
H2SLd
P
R
P
G
G
P
B
P
P
G
P
B
R
P
G
P
P
R
P
G
4864H x 3232V
7.4 mm x 7.4 mm Pixels
22 12
V1B
V2B
V3B
V4B
G
P
B
P
P
G
P
B
R
P
G
P
P
R
P
G
V1T
V2T
V3T
V4T
12 22
G
P
B
P
RDa
R2ab
P
G
P
B
R
P
G
P
1 10 22 12
8
2432
2432
RDb
R2ab
12
8 22 10 1
H2Bb
H2Sb
H1Bb
H1Sb
FDGab
SUB
Figure 4. TRUESENSE Sparse Color Filter Pattern
www.onsemi.com
4
ESD
V1B
V2B
V3B
V4B
P
R
P
G
12 Buffer
22 Dark
(Last VCCD Phase = V1 → H1S)
FLD
FDGab
H2Ba
H2Sa
H1Ba
H1Sa
GND
OGa
H2SLa
RDd
R2cd
DevID
2432
GND
OGc
H2SLc
Ra
VDDa
VOUTa
H2Bd
H2Sd
H1Bd
H1Sd
FDGcd
Rc
VDDc
VOUTc
SUB
FDGcd
H2Bc
H2Sc
H1Bc
H1Sc
RDc
R2cd
Rb
VDDb
VOUTb
GND
OGb
H2SLb
KAI−16070
PHYSICAL DESCRIPTION
Pin Description and Device Orientation
V3T
V1T
GND
VDDd
Rd
H2SLd
H1Bd
H2Sd
SUB
R2cd
H2Sc
H1Bc
H2SLc
Rc
GND
VDDc
V1T
V3T
71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37
72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38
DevID
ESD
RDb
V4B
RDd
OGb
V4T
OGd
H2Bb
V2B
H2Bd
H1Sb
V2T
H1Sd
FDGab
VOUTd
FDGcd
H1Sa
FDGab
H2Ba
FDGcd
H2Bc
OGa
H1Sc
OGc
RDa
VOUTa
RDc
V2B
VOUTc
V2T
V4B
ESD
V4T
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
Pixel
(1,1)
VOUTb
www.onsemi.com
5
V3B
Figure 5. Package Pin Designations − Top View
V1B
VDDb
GND
Ra
Rb
GND
H2SLb
VDDa
H1Bb
V1B
H2Sb
V3B
R2ab
9 11 13 15 17 19 21 23 25 27 29 31 33 35
SUB
7
H2Sa
5
H1Ba
3
H2SLa
1
KAI−16070
Pin
Name
72
ESD
ESD Protection Disable
Vertical CCD Clock, Phase 3, Bottom
71
V3T
Vertical CCD Clock, Phase 3, Top
[No Pin − Keyed]
70
V4T
Vertical CCD Clock, Phase 4, Top
V1T
Vertical CCD Clock, Phase 1, Top
Vertical CCD Clock, Phase 2, Top
Table 3. PIN DESCRIPTION
Pin
Name
1
V3B
[2]
Description
Description
3
V1B
Vertical CCD Clock, Phase 1, Bottom
69
4
V4B
Vertical CCD Clock, Phase 4, Bottom
68
V2T
VDDc
Output Amplifier Supply, Quadrant c
Video Output, Quadrant c
5
VDDa
Output Amplifier Supply, Quadrant a
67
6
V2B
Vertical CCD Clock, Phase 2, Bottom
66
VOUTc
Ground
65
GND
Ground
Video Output, Quadrant a
64
RDc
Reset Drain, Quadrant c
Reset Gate, Standard (High) Gain,
Quadrant a
63
Rc
Reset Drain, Quadrant a
62
OGc
Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant a
61
H2SLc
Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant c
7
GND
8
VOUTa
9
Ra
10
RDa
Reset Gate, Standard (High) Gain,
Quadrant c
Output Gate, Quadrant c
11
H2SLa
12
OGa
Output Gate, Quadrant a
60
H2Bc
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant c
13
H1Ba
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant a
59
H1Bc
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant c
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant a
58
H1Sc
Horizontal CCD Clock, Phase 1,
Storage, Quadrant c
Horizontal CCD Clock, Phase 2,
Storage, Quadrant a
57
H2Sc
Horizontal CCD Clock, Phase 2,
Storage, Quadrant c
Horizontal CCD Clock, Phase 1,
Storage, Quadrant a
56
FDGcd
Substrate
55
R2cd
Fast Line Dump Gate, Bottom
54
FDGcd
Reset Gate, Low Gain, Quadrants a & b
53
SUB
Substrate
Fast Line Dump Gate, Bottom
52
H1Sd
Horizontal CCD Clock, Phase 1,
Storage, Quadrant d
Horizontal CCD Clock, Phase 2,
Storage, Quadrant b
51
H2Sd
Horizontal CCD Clock, Phase 2,
Storage, Quadrant d
Horizontal CCD Clock, Phase 1,
Storage, Quadrant b
50
H2Bd
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant d
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant b
49
H1Bd
Horizontal CCD Clock, Phase 1, Barrier,
Quadrant d
Horizontal CCD Clock, Phase 2, Barrier,
Quadrant b
48
OGd
Output Gate, Quadrant d
Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant b
47
H2SLd
Output Gate, Quadrant b
46
RDd
Reset Gate, Standard (High) Gain,
Quadrant b
45
Rd
Reset Drain, Quadrant b
44
VOUTd
Ground
43
GND
Ground
Video Output, Quadrant b
42
V2T
Vertical CCD Clock, Phase 2, Top
Output Amplifier Supply, Quadrant b
41
VDDd
V4T
Vertical CCD Clock, Phase 4, Top
Vertical CCD Clock, Phase 1, Top
14
15
16
17
H2Ba
H2Sa
H1Sa
SUB
18
FDGab
19
R2ab
20
FDGab
21
H2Sb
22
23
24
H1Sb
H1Bb
H2Bb
25
H2SLb
26
OGb
27
Rb
28
RDb
29
GND
30
VOUTb
31
VDDb
32
V2B
Vertical CCD Clock, Phase 2, Bottom
40
33
V1B
Vertical CCD Clock, Phase 1, Bottom
39
V1T
38
DevID
37
V3T
34
V4B
Vertical CCD Clock, Phase 4, Bottom
35
V3B
Vertical CCD Clock, Phase 3, Bottom
36
ESD
Fast Line Dump Gate, Top
Reset Gate, Low Gain, Quadrants c & d
Fast Line Dump Gate, Top
Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant d
Reset Drain, Quadrant d
Reset Gate, Standard (High) Gain,
Quadrant d
Video Output, Quadrant d
Output Amplifier Supply, Quadrant d
Device Identification
Vertical CCD Clock, Phase 3, Top
1. Liked named pins are internally connected and should have
a common drive signal.
ESD Protection Disable
www.onsemi.com
6
KAI−16070
IMAGING PERFORMANCE
Table 4. TYPICAL OPERATION CONDITIONS
Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.
Description
Condition
Notes
Light Source
Continuous red, green and blue LED illumination
Operation
Nominal operating voltages and timing
For monochrome sensor, only
green LED used.
Table 5. SPECIFICATIONS − ALL CONFIGURATIONS
Description
Dark Field Global Non−Uniformity
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
DSNU
−
−
5
mVpp
Die
27, 40
−
2
12
%rms
Die
27, 40
1
−
10
30
%pp
Die
27, 40
1
−
1
2
%rms
Die
27, 40
1
%
Design
2
2
Bright Field Global Non−Uniformity
Bright Field Global Peak to Peak Non−
Uniformity
PRNU
Bright Field Center Non−Uniformity
Maximum Photo−response Nonlinearity
High Gain (4,000 to 20,000 electrons)
High Gain (4,000 to 40,000 electrons)
Low Gain (8,000 to 80,000 electrons)
NL_HG1
NL_HG2
NL_LG1
−
−
−
2
3
6
−
−
−
Maximum Gain Difference Between
Outputs
DG
−
10
−
%
Design
Horizontal CCD Charge Capacity
HNe
−
90
−
ke−
Design
Design
Temperature
Tested At
(5C)
Vertical CCD Charge Capacity
VNe
−
60
−
ke−
Photodiode Charge Capacity
PNe
−
44
−
ke−
Die
27, 40
Floating Diffusion Capacity − High Gain
Fne_HG
40
−
−
ke−
Die
27, 40
Floating Diffusion Capacity − Low Gain
Fne_LG
160
−
−
ke−
Die
27, 40
Linear Saturation Level − High Gain
Lsat_HG
−
40
−
ke−
Design
Linear Saturation Level − Low Gain
Lsat_LG
−
160
−
ke−
Design
Horizontal CCD Charge Transfer
Efficiency
HCTE
0.999995
0.999999
−
Die
Vertical CCD Charge Transfer
Efficiency
VCTE
0.999995
0.999999
−
Die
Photodiode Dark Current
Ipd
−
2
70
e/p/s
Die
40
Vertical CCD Dark Current
Ivd
−
200
600
e/p/s
Die
40
e−
Design
Notes
3
Image Lag
Lag
−
−
10
Antiblooming Factor
Xab
1000
−
−
Vertical Smear
Smr
−
−115
−
dB
Design
Read Noise (High Gain / Low Gain)
ne−T
−
12 / 45
−
e−rms
Design
4
Dynamic Range, Standard
DR
−
70.5
−
dB
Design
4, 5
XLDR
−
82.5
−
dB
Design
4, 5
Output Amplifier DC Offset
Vodc
5
9.0
14
V
Die
Output Amplifier Bandwidth
f−3db
−
250
−
MHz
Design
Output Amplifier Impedance
ROUT
100
127
200
W
Die
Output Amplifier Sensitivity
High Gain
Low Gain
DV/DN
mV/e−
Design
−
−
33
9.7
−
−
Dynamic Range, Extended Linear
Dynamic Range Mode (XLDR)
Design
27, 40
6
27, 40
1. Per color
2. Value is over the range of 10% to 90% of photodiode saturation.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode
charge capacity is 1450 mV. This value is determined while operating the device in the low gain mode. VAB level assigned is valid for both modes; high gain or
low gain.
4. At 40 MHz
5. Uses 20LOG (PNe/ ne−T)
6. Assumes 5 pF load.
www.onsemi.com
7
KAI−16070
Table 6. KAI−16070−AAA CONFIGURATION WITH NO GLASS
Temperature
Tested At
(5C)
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Peak Quantum Efficiency
QEmax
−
10
−
%
Design
1
Peak Quantum Efficiency
Wavelength
lQE
−
500
−
nm
Design
1
Description
Notes
1. Measurement taken without cover glass.
Table 7. KAI−16070−AXA, KAI−16070−PXA, AND KAI−16070−QXA CONFIGURATIONS
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Peak Quantum Efficiency
QEmax
−
48
−
%
Design
Peak Quantum Efficiency
Wavelength
lQE
−
500
−
nm
Design
Description
Temperature
Tested At
(5C)
Notes
1. This color filter set configuration (Gen1) is not recommended for new designs.
Table 8. KAI−16070−FXA AND KAI−16070−QXA GEN2 COLOR CONFIGURATIONS WITH MAR GLASS
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Peak Quantum Efficiency
Blue
Green
Red
QEmax
−
40
40
34
−
%
Design
Peak Quantum Efficiency
Wavelength
Blue
Green
Red
lQE
−
460
535
605
−
nm
Design
Description
Temperature
Tested At
(5C)
Notes
Table 9. KAI−16070−CXA AND KAI−16070−PXA GEN1 COLOR CONFIGURATIONS WITH MAR GLASS
Description
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Temperature
Tested At
(5C)
Notes
Peak Quantum Efficiency
Blue
Green
Red
QEmax
−
39
41
32
−
%
Design
1
Peak Quantum Efficiency
Wavelength
Blue
Green
Red
lQE
−
470
540
620
−
nm
Design
1
1. This color filter set configuration (Gen1) is not recommended for new designs.
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8
KAI−16070
Linear Signal Range
High Gain
Low Gain
Output of Sensor Not Verified or
Guaranteed
Output of Sensor Not Verified or
Guaranteed
4,000
1,600
990
120,000
1,200
330
132
0
40,000
8,000
0
0
800
80,000
Linearity Guaranteed to 6%
660
80
0
0
Light or Exposure (arbitrary)
0
Figure 6. High Gain Linear Signal Range
Light or Exposure (arbitrary)
Figure 7. Low Gain Linear Signal Range
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9
400
Output Signal (mV)
160,000
Output Signal (electrons)
10,000
1,320
Output Signal (mV)
20,000
Linearity Guaranteed to 3%
30,000
Linearity Guaranteed to 2%
Output Signal (electrons)
40,000
KAI−16070
TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome without Microlens
Figure 8. Monochrome without Microlens Quantum Efficiency
Monochrome with Microlens
Figure 9. Monochrome with Microlens Quantum Efficiency
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10
KAI−16070
Color (Bayer RGB) with Microlens (Gen2 and Gen1 CFA)
Figure 10. Color (Bayer) with Microlens Quantum Efficiency
Color (TRUESENSE Sparse CFA) with Microlens (Gen2 and Gen1 CFA)
Figure 11. Color (TRUESENSE Sparse CFA) with Microlens Quantum Efficiency
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11
KAI−16070
Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light
angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle
is varied in a plane parallel to the VCCD.
Monochrome with Microlens
1.0
Normalized Quantum Efficiency
0.9
Horizontal
0.8
Vertical
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
−40
−30
−20
−10
0
10
20
30
40
Angle (degrees)
Figure 12. Monochrome with Microlens Angular Quantum Efficiency
Dark Current versus Temperature
PD
VCCD
1000.000
Dark Current (e/s)
100.000
10.000
70 C
60 C
1.000
50 C
40 C
30 C
0.100
20 C
10 C
0.010
2.90
3.00
3.10
3.20
3.30
3.40
3.50
1000/ T(K)
Figure 13. Dark Current versus Temperature
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12
3.60
KAI−16070
Power − Estimated
Figure 14. Power
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13
KAI−16070
Frame Rates
Figure 15. Frame Rates
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14
KAI−16070
DEFECT DEFINITIONS
Table 10. OPERATION CONDITIONS FOR DEFECT TESTING AT 405C
Description
Condition
Notes
Operational Mode
One output using VOUTa, continuous readout
HCCD Clock Frequency
20 MHz
Pixels Per Line
5000
1
Lines Per Frame
3354
2
Line Time
266 msec
Frame Time
894 msec
Photodiode Integration Time
PD_Tint = Frame Time = 894 msec, no electronic shutter used
Temperature
40°C
Light Source
Continuous red, green and blue LED illumination
Operation
Nominal operating voltages and timing
3
1. Horizontal overclocking used.
2. Vertical overclocking used.
3. For monochrome sensor, only the green LED is used.
Table 11. DEFECT DEFINITIONS FOR TESTING AT 405C
Description
Definition
Grade 1
Grade 2
Mono
Grade 2
Color
Notes
150
300
300
1
1500
3000
3000
Major dark field defective bright pixel
PD_Tint = Frame Time; Defect ≥ 325 mV
Major bright field defective dark pixel
Defect ≥ 15%
Minor dark field defective bright pixel
PD_Tint = Frame Time; Defect ≥ 163 mV
Cluster defect
A group of 2 to 19 contiguous major
defective pixels, but no more than 4
adjacent defects horizontally.
30
30
30
2
Column defect
A group of more than 10 contiguous major
defective pixels along a single column
0
4
15
2
1. For the color devices (KAI−16070−FXA, KAI−16070−QXA, KAI−16070−CXA, and KAI−16070−PXA), a bright field defective pixel deviates
by 12% with respect to pixels of the same color.
2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).
3. Tested at 40°C with no electronic shutter used.
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KAI−16070
Table 12. OPERATION CONDITIONS FOR DEFECT TESTING AT 275C
Description
Condition
Notes
Operational Mode
Two outputs, using VOUTa and VOUTc, continuous readout
HCCD Clock Frequency
20 MHz
Pixels Per Line
5000
1
Lines Per Frame
3354
2
Line Time
266 msec
Frame Time
894 msec
Photodiode Integration Time
(PD_Tint)
PD_Tint = Frame Time = 894 msec, no electronic shutter used
Temperature
27°C
Light Source
Continuous red, green and blue LED illumination
Operation
Nominal operating voltages and timing
3
1. Horizontal overclocking used.
2. Vertical overclocking used.
3. For monochrome sensor, only the green LED is used.
Table 13. DEFECT DEFINITIONS FOR TESTING AT 275C
Description
Definition
Grade 1
Grade 2
Mono
Grade 2
Color
Notes
Major dark field defective bright pixel
PD_Tint = Frame Time → Defect ≥ 100 mV
150
300
300
1
Major bright field defective dark pixel
Defect ≥ 15%
Minor dark field defective bright pixel
PD_Tint = Frame Time; Defect ≥ 52 mV
1500
3000
3000
Cluster defect
A group of 2 to 19 contiguous major
defective pixels, but no more than 4
adjacent defects horizontally.
30
30
30
2
Column defect
A group of more than 10 contiguous major
defective pixels along a single column
0
4
15
2
1. For the color devices (KAI−16070−FXA, KAI−16070−QXA, KAI−16070−CXA, and KAI−16070−PXA), a bright field defective pixel deviates
by 12% with respect to pixels of the same color.
2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).
3. Tested at 27°C with no electronic shutter used.
4. Defectivity levels for a unit with the Taped Cover Glass configuration (non−sealed cover glass) of this device cannot be guaranteed after final
testing at the factory. Image sensors are tested for defects and are mapped prior to shipment. Additional pixel defects and clusters may
appear for devices purchased without a sealed cover glass.
Defect Map
defects are not included in the defect map. All defective
pixels are reference to pixel 1, 1 in the defect maps. See
Figure 16: Regions of interest for the location of pixel 1,1.
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
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16
KAI−16070
TEST DEFINITIONS
Test Regions of Interest
Image Area ROI:
Pixel (1, 1) to Pixel (4888, 3256)
Active Area ROI:
Pixel (13, 13) to Pixel (4876, 3244)
Center ROI:
Pixel (2345, 1527) to Pixel (2444, 1628)
Only the Active Area ROI pixels are used for performance and defect tests.
Overclocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 16 for a pictorial representation of the regions of
interest.
VOUTc
12 dark rows
12 buffer rows
12 buffer rows
12 dark rows
VOUTa
Figure 16. Regions of Interest
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17
Horizontal Overclock
1, 1
22 dark columns
Pixel
12 buffer columns
12 buffer columns
22 dark columns
Pixel
13,
13
Active Pixels
4864 (H) x 3232 (V)
KAI−16070
Tests
Dark Field Global Non−Uniformity
This test is performed under dark field conditions. The
sensor is partitioned into 1 mm x 1 mm sub regions, each of
which is 135 by 135 pixels in size. The average signal level
of each of the sub regions of interest is calculated. The signal
level of each of the sub regions of interest is calculated using
the following formula:
minimum signal levels are found. The dark field global
uniformity is then calculated as the maximum signal found
minus the minimum signal level found.
Units: mVpp (millivolts peak to peak)
Global Non−Uniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 924 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 1320 mV. Global non−uniformity is
defined as
Signal of ROI[i] = (ROI Average in counts − Horizontal
overclock average in counts) * mV per count
Where i = 1 to total # of sub regions. During this
calculation on the sub regions of interest, the maximum and
GlobalNon−Uniformity + 100
ǒActiveAreaStandardDeviation
Ǔ
ActiveAreaSignal
pixels in size. The average signal level of each of the before
mentioned sub regions of interest (ROI) is calculated. The
signal level of each of the sub regions of interest is calculated
using the following formula:
Units: %rms.
Active Area Signal = Active Area Average − Dark Column
Average
Global Peak to Peak Non−Uniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 924 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 1320 mV. The sensor is partitioned
into sub regions of interest, each of which is 135 by 135
GlobalUniformity + 100
Signal of ROI[i] = (ROI Average in counts − Horizontal
overclock average in counts) * mV per count
Where i = 1 to total # of sub regions. During this
calculation on the sub regions of interest, the maximum and
minimum signal levels are found. The global peak to peak
uniformity is then calculated as:
MaximumSignal * MinimumSignal
ActiveAreaSignal
the substrate voltage has been set such that the charge
capacity of the sensor is 1320 mV. Defects are excluded for
the calculation of this test. This test is performed on the
center 100 by 100 pixels of the sensor. Center uniformity is
defined as:
Units: %pp
Center Non−Uniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 924 mV). Prior to this test being performed
Center ROI Uniformity + 100
ROI Standard Deviation
ǒCenterCenter
Ǔ
ROI Signal
to this test being performed the substrate voltage has been set
such that the charge capacity of the sensor is 1320 mV. The
average signal level of all active pixels is found. The bright
and dark thresholds are set as:
Units: %rms.
Center ROI Signal = Center ROI Average − Dark Column
Average
Dark Field Defect Test
This test is performed under dark field conditions. The
sensor is partitioned into 1 mm x 1 mm sub regions, each of
which is 135 by 135 pixels in size. In each region of interest,
the median value of all pixels is found. For each region of
interest, a pixel is marked defective if it is greater than or
equal to the median value of that region of interest plus the
defect threshold specified in the “Defect Definitions”
section.
Dark defect threshold = Active Area Signal * threshold
Bright defect threshold = Active Area Signal * threshold
The sensor is then partitioned into 1 mm x 1 mm sub
regions of interest, each of which is 135 by 135 pixels in size.
In each region of interest, the average value of all pixels is
found. For each region of interest, a pixel is marked
defective if it is greater than or equal to the median value of
that region of interest plus the bright threshold specified or
if it is less than or equal to the median value of that region
of interest minus the dark threshold specified.
Bright Field Defect Test
This test is performed with the imager illuminated to a
level such that the output is at approximately 924 mV. Prior
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18
KAI−16070
Example for major bright field defective pixels:
• Average value of all active pixels is found to be
924 mV
• Dark defect threshold: 924 mV * 15% = 138 mV
• Bright defect threshold: 924 mV * 15% = 138 mV
• Region of interest #1 selected. This region of interest is
pixels 13, 13 to pixels 147, 147.
♦ Median of this region of interest is found to be
918 mV.
♦ Any pixel in this region of interest that
is ≥ (918 + 138 mV) 1062 mV in intensity will be
marked defective.
♦ Any pixel in this region of interest that
is ≤ (918 − 138 mV) 780 mV in intensity will be
marked defective.
• All remaining sub regions of interest are analyzed for
defective pixels in the same manner. Any remaining
factor of pixels less than 135 pixels that are not covered
by this moving ROI is placed over the remaining pixels
at the active area boundary. A portion of pixels that
were tested in the previous ROI will be retested to keep
the test ROI at a full 135 by 135 pixels.
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19
KAI−16070
OPERATION
Table 14. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Units
Notes
Operating Temperature
TOP
−50
+70
°C
1
Humidity
RH
+5
+90
%
2
Output Bias Current
Iout
60
mA
3
Off−chip Load
CL
10
pF
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during
operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).
Table 15. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
Description
Minimum
Maximum
Units
Notes
VDDa, VOUTa
−0.4
17.5
V
1
RDa
−0.4
15.5
V
1
V1B, V1T
ESD − 0.4
ESD + 24.0
V
V2B, V2T, V3B, V3T, V4B, V4T
ESD − 0.4
ESD + 14.0
V
FDGab, FDGcd
ESD − 0.4
ESD + 14.0
V
H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, Ra, OGa
ESD − 0.4
ESD + 14.0
V
ESD
−10.0
0.0
V
SUB
−0.4
+40.0
V
1
2
1. a denotes a, b, c or d
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
KAI−29050 Compatibility
5. The number of horizontal and vertical CCD clock
cycles is reduced as appropriate.
6. In addition, if the intent is to operate the
KAI−16070 image sensor in a camera designed for
the KAI−29050 sensor that has been modified to
accept and process the full 40,000 e− (1,320 mV)
output, the following changes to the following
voltage bias must be made:
The KAI−16070 is pin−for−pin compatible with a camera
designed for the KAI−29050 image sensor with the
following accommodations:
1. To operate in accordance with a system designed
for KAI−29050, the target substrate voltage should
be set to be 2.0 V higher than the value recorded
on the KAI−16070 shipping container. This setting
will cause the charge capacity to be limited to
20 Ke− (or 660 mV).
2. On the KAI−16070, pins 19 (R2ab) and 55 (R2cd)
should be left floating per the KAI−29050 Device
Performance Specification.
3. The KAI−16070 will operate in only the high gain
mode (33 mV/e).
4. All timing and voltages are taken from the
KAI−29050 specification sheet.
Voltage Bias Differences
Pins 10, 28, 46, and 64
KAI−29050
KAI−16070
12.0 V per the
specification
Increase this
value to 12.6 V
NOTE: To make use of the low gain mode or dual gain
mode the KAI−16070 voltages and timing
specification must be used.
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20
KAI−16070
Reset Pin, Low Gain (R2ab and R2cd)
The R2ab and R2bc (pins 19 and 55) each have an internal
circuit to bias the pins to 4.3 V. This feature assures the
device is set to operate in the high gain mode when pins 19
VDD
(+15 V)
and 55 are not connected in the application to a clock driver
(for KAI−29050 compatibility). Typical capacitor coupled
drivers will not drive this structure.
VDD
(+15 V)
R2
4.3 V
68 kW
68 kW
20 kW
20 kW
27 kW
27 kW
GND
GND
Figure 17. Equivalent Circuit for Reset Gate, Low Gain (R2ab and R2cd)
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21
KAI−16070
Power−Up and Power−Down Sequence
Adherence to the power−up and power−down sequence is critical. Failure to follow the proper power−up and power−down
sequences may cause damage to the sensor.
Do not pulse the electronic shutter
until ESD is stable
V+
VDD
SUB
time
ESD
V−
VCCD
Low
HCCD
Low
Activate all other biases when
ESD is stable and sub is above 3V
Figure 18. Power−Up and Power−Down Sequence
The VCCD clock waveform must not have a negative
overshoot more than 0.4 V below the ESD voltage.
Notes:
7. Activate all other biases when ESD is stable and
SUB is above 3 V
8. Do not pulse the electronic shutter until ESD is
stable
9. VDD cannot be +15 V when SUB is 0 V
10. The image sensor can be protected from an
accidental improper ESD voltage by current
limiting the SUB current to less than 10 mA. SUB
and VDD must always be greater than GND. ESD
must always be less than GND. Placing diodes
between SUB, VDD, ESD and ground will protect
the sensor from accidental overshoots of SUB,
VDD and ESD during power on and power off.
See the figure below.
0.0V
ESD
ESD − 0.4V
All VCCD and FDG Clocks absolute
maximum overshoot of 0.4 V
Figure 19.
Example of external diode protection for SUB, VDD and
ESD. a denotes a, b, c or d
VDDa
SUB
GND
ESD
Figure 20.
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22
KAI−16070
Table 16. DC BIAS OPERATING CONDITIONS
Pins
Symbol
Minimum
Nominal
Maximum
Units
Maximum DC
Current
Notes
Reset Drain
RDa
RD
+12.4
+12.6
+12.8
V
10 mA
1, 9
Output Gate
OGa
OG
−2.2
−2.0
−1.8
V
10 mA
1
Output Amplifier Supply
VDDa
VDD
+14.5
+15.0
+15.5
V
11.0 mA
1,2
Ground
GND
GND
0.0
0.0
0.0
V
−1.0 mA
Substrate
SUB
VSUB
+5.0
VAB
VDD
V
50 mA
3, 8
ESD Protection Disable
ESD
ESD
−9.5
−9.0
Vx_L
V
50 mA
6, 7, 10
VOUTa
Iout
−3.0
−5.0
−10.0
mA
Description
Output Bias Current
1, 4, 5
VDDa
RDa
Ra
R2a
1. a denotes a, b, c or d
2. The maximum DC current is for one output. Idd = Iout + Iss. See Figure 21.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such
that the photodiode charge capacity is the nominal PNe (see Specifications).
4. An output load sink must be applied to each VOUT pin to activate each output amplifier.
5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise.
6. Adherence to the power−up and power−down sequence is critical. See Power−Up and Power−Down Sequence section.
7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V
8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions
9. 12.0 V may be used if the total output signal desired is 20,000 e− or less.
10. Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application.
Idd
HCCD
Floating
Diffusion
Iout
OGa
VOUTa
Iss
Source
Follower
#1
Source
Follower
#2
Figure 21. Output Amplifier − Showing Dual Reset Pins
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23
Source
Follower
#3
KAI−16070
AC Operating Conditions
Table 17. CLOCK LEVELS
Description
Pins
Vertical CCD Clock, Phase 1
V2B, V2T
1
Vertical CCD Clock, Phase 3
V3B, V3T
1
Vertical CCD Clock, Phase 4
V4B, V4T 1
Vertical CCD Clock, Phase 2
Horizontal CCD Clock, Phase 1
Storage
H1Sa 1
Horizontal CCD Clock, Phase 1
Barrier
H1Ba
1
Horizontal CCD Clock, Phase 2
Storage
H2Sa 1
Horizontal CCD Clock, Phase 2
Barrier
H2Ba 1
Horizontal CCD Clock, Last
Phase 2
Reset Gate
H2SLa
Ra
Reset Gate
1
1
4
SUB
Fast Line Dump Gate
FDGa
Symbol
Level
Minimum
Nominal
1
Maximum
Units
V
V1_L
Low
−8.2
−8.0
−7.8
V1_M
Mid
−0.2
0.0
+0.2
V1_H
High
+12.8
+13.0
+14.0
V2_L
Low
−8.2
−8.0
−7.8
V2_H
High
−0.2
0.0
+0.2
V3_L
Low
−8.2
−8.0
−7.8
V3_H
High
−0.2
0.0
+0.2
V4_L
Low
−8.2
−8.0
−7.8
V4_H
High
−0.2
0.0
+0.2
H1S_L
Low
−5.0 (5)
−4.4
−4.2
H1S_A
Amplitude
+4.2
+4.4
+5.0 (5)
H1B_L
Low
−5.0 (5)
−4.4
−4.2
H1B_A
Amplitude
+4.2
+4.4
+5.0 (5)
H2S_L
Low
−5.0 (5)
−4.4
−4.2
H2S_A
Amplitude
+4.2
+4.4
+5.0 (5)
H2B_L
Low
−5.0 (5)
−4.4
−4.2
H2B_A
Amplitude
+4.2
+4.4
+5.0 (5)
H2SL_L
Low
−5.2
−5.0
−4.8
H2SL_A
Amplitude
+4.8
+5.0
+5.2
−3.0
R_L
R2ab, R2cd
Electronic Shutter
1.
2.
3.
4.
5.
V1B, V1T
1
3
−2.8
V
V
V
V
V
V
V
V
V
Low
−3.2
R_A
Amplitude
+6.0
R_L 3
Low
−2.0
R_A
Amplitude
+6.0
VES
High
+29.0
+30.0
+40.0
V
FDG_L
Low
−8.2
−8.0
−7.8
V
FDG_H
High
+4.5
+5.0
+5.5
+6.4
−1.8
−1.6
V
+6.4
a denotes a, b, c or d
Use separate clock driver for improved speed performance.
Reset low should be set to –3 volts for signal levels greater than 40,000 electrons.
Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions
If the minimum horizontal clock low level is used (–5.0 V), then the maximum horizontal clock amplitude should be used (5 V amplitude) to
create a –5.0 V to 0.0 V clock.
The figure below shows the DC bias (VSUB) and AC
clock (VES) applied to the SUB pin. Both the DC bias and
AC clock are referenced to ground.
VES
VSUB
GND
GND
Figure 22.
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24
KAI−16070
Capacitance
Table 18. CAPACITANCE
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
GND
All Pins
Units
V1B
X
17
11
14
6
5
6
4
24
88
nF
V2B
X
X
21
10
5
3
4
3
7
74
nF
V3B
X
X
X
19
6
5
6
4
8
83
nF
V4B
X
X
X
X
5
4
5
3
23
76
nF
V1T
X
X
X
X
X
14
11
17
24
86
nF
V2T
X
X
X
X
X
X
16
6
22
75
nF
V3T
X
X
X
X
X
X
X
19
11
84
nF
V4T
X
X
X
X
X
X
X
X
5
73
nF
FDGT
0.6
0.5
0.5
0.4
16
3.1
1.0
1.1
94
117
pF
FDGB
0.6
0.5
0.5
0.4
16
3.1
1.0
1.1
94
117
pF
VSUB
2
2
2
2
2
2
2
2
11
11
nF
H2S
H1B
H2B
GND
All Pins
Units
H1S
45
75
44
196
360
pF
H2S
X
47
41
281
368
pF
H1B
X
X
12
313
324
pF
H2B
X
X
X
293
293
pF
1. Tables show typical cross capacitance between pins of the device.
2. Capacitance is total for all like named pins.
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25
KAI−16070
Device Identification
The device identification pin (DevID) may be used to identify different members of the ON Semiconductor 5.5 micron and
7.4 micron Interline Transfer CCD Platforms.
Table 19. DEVICE IDENTIFICATION
Description
Device Identification
Pins
Symbol
Minimum
Nominal
Maximum
Units
Maximum DC
Current
Notes
DevID
DevID
32,000
40,000
48,000
W
50 mA
1, 2, 3
1. Nominal value subject to verification and/or change during release of preliminary specifications.
2. If the Device Identification is not used, it may be left disconnected.
3. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent
localized heating of the sensor due to current flow through the R_DeviceID resistor.
Recommended Circuit
Note that V1 must be a different value than V2.
V1
V2
R_external
DevID
ADC
R_DeviceID
GND
KAI−16070
Figure 23. Device Identification Recommended Circuit
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26
KAI−16070
TIMING
Table 20. REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
Minimum
Nominal
Maximum
Units
Photodiode Transfer
tpd
6
−
−
ms
VCCD Leading Pedestal
t3p
16
−
−
ms
VCCD Trailing Pedestal
t3d
16
−
−
ms
VCCD Transfer Delay
td
2
−
−
ms
VCCD Transfer
tv
4
−
−
ms
tVR, tVF
5
−
10
%
FDG Delay
tfdg
2
−
−
ms
HCCD Delay
ths
2
−
−
ms
HCCD Transfer
te
25.0
−
−
ns
Shutter Transfer
tsub
2
−
−
ms
Shutter Delay
thd
2
−
−
ms
Reset Pulse
tr
2.5
−
−
ns
Reset – Video Delay
trv
−
2.2
−
ns
H2SL – Video Delay
thv
−
2.2
−
ns
Line Time
tline
77.9
−
−
ms
140
−
−
129
−
−
257
−
−
Dual HCCD Readout
461
−
−
Single HCCD Readout
124.9
−
−
217.4
−
−
133
−
−
267
−
−
Dual HCCD Readout
466
−
−
Single HCCD Readout
103
−
−
206
−
−
Dual HCCD Readout
359
−
−
Single HCCD Readout
VCCD Rise, Fall Times
Frame Time
Line Time (XLDR Bin 2x2)
Frame Time (XLDR Bin 2x2)
Constant HCCD Timing
Frame Time (XLDR Bin 2x2)
Variable HCCD Timing
tframe
tline
tframe
tframe
1. Refer to Figure 41: VCCD Clock Rise Time and Fall Time.
2. Relative to the pulse width, tV.
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27
Notes
1, 2
Dual HCCD Readout
Single HCCD Readout
ms
ms
Quad HCCD Readout
Dual HCCD Readout
Single HCCD Readout
ms
ms
Quad HCCD Readout
Quad HCCD Readout
KAI−16070
Timing Flow Charts
In the timing flow charts the number of HCCD clock cycles per row, NH, and the number of VCCD clock cycles per frame,
NV, are shown in the following table.
Table 21. VALUES FOR NH AND NV WHEN OPERATING THE SENSOR IN THE VARIOUS MODES OF RESOLUTION
Full Resolution
1/4 Resolution
XLDR
NV
NH
NV
NH
NV
NH
Quad
1650
2477
825
1238
825
1238
Dual VOUTa, VOUTc
1650
4943
825
2471
825
2471
Dual VOUTa, VOUTb
3278
2477
1639
1238
1639
1238
Single VOUTa
3278
4943
1639
2471
1639
2471
1.
2.
3.
4.
5.
The time to read out one line tLINE = Line Timing + NH / (Pixel Frequency).
The time to read out one frame tFRAME = NV ⋅ tLINE + Frame Timing.
Line Timing: See Table 23: Line Timing.
Frame Timing: See Table 22: Frame Timing.
XLDR: eXtended Linear Dynamic Range.
No Electronic Shutter
In this case the photodiode exposure time is equal to the time to read out an image. This flow chart applies to both full and
1/4 resolution modes.
Frame Timing
(see Table 22)
Line Timing
(see Table 23)
Pixel Timing
(see Table 24)
Repeat NH
Times
Repeat NV
Times
Figure 24. Timing Flow when Electronic Shutter is Not Used
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28
KAI−16070
Using the Electronic Shutter
This flow chart applies to both the full and 1/4 resolution
modes. The exposure time begins on the falling edge of the
electronic shutter pulse on the SUB pin. The exposure time
ends on the falling edge of the +13 V to 0 V transition of the
V1T and V1B pins. NEXP is varied to change the exposure
time in increments of the line time. The electronic shutter
timing is obtained from Figure 33.
Frame Timing
(see Table 22)
Line Timing
(see Table 23)
Pixel Timing
(see Table 24)
Repeat NH
Times
Repeat NV−NEXP
Times
Electronic
Shutter Timing
Line Timing
(see Table 23)
Pixel Timing
(see Table 24)
Repeat NH
Times
Repeat NEXP
Times
NOTE: NEXP: Exposure time in increments of number of lines.
Figure 25. Timing Flow Chart using the Electronic Shutter for Exposure Control
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29
KAI−16070
Window Readout Using the Fast Dump
This timing quickly dumps NV1 lines, then reads out NV2
lines, and then quickly dumps another NV3 lines. NV1 +
NV2 + NV3 must be greater than or equal to NV. Note when
operating in quad or dual VOUTa + VOUTc modes the NV2
valid image lines must be in the center of the pixel array or
contained entirely within the bottom half or top half of the
pixel array. This is due to the top and bottom middle split of
the VCCD. In the single output or dual VOUTa + VOUTb
modes the NV2 valid image lines may be located anywhere
within the pixel array.
The line timing with the FDGab and FDGcd pins disabled
means those pins are held at a constant −9 V. When they are
enabled, they are held at +5 V during a line transfer.
Frame Timing
(see Table 22)
Line Timing
FDGab, FDGcd
enabled
(see Table 23)
Line Timing
FDGab, FDGcd
disabled
(see Table 23)
NV1 Lines
Pixel Timing
(see Table 24)
NV2 Lines
NV3 Lines
Repeat NH
Times
KAI−16070
Repeat NV2
Times
Line Timing
FDGab, FDGcd
enabled
(see Table 23)
Repeat NV3
Times
Figure 26. Sub Window Timing Flow Chart
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30
charge transfer
Repeat NV1
Times
KAI−16070
Line Sampling Readout Using the Fast Dump
This timing repeats the process of dumping NV4 lines and
reading NV5 lines. The total NV6 x (NV4 + NV5) must be
greater than or equal to NV. This timing can be used for
alternately skipping and reading lines. For example, if
NV4 = 2 and NV5 = 1 then every third line will be read out
(skip 2 read 1).
Frame Timing
(see Table 22)
Line Timing
FDGab, FDGcd
enabled
(see Table 23)
Repeat NV4
Times
Line Timing
FDGab, FDGcd
disabled
(see Table 23)
Pixel Timing
(see Table 24)
Repeat NH
Times
Repeat NV5
Times
Repeat NV6
Times
Figure 27. Timing Flow Chart to Alternately Skip and Read Rows for Subsampling
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31
KAI−16070
Timing Tables
Frame Timing
This timing table is for transferring charge from the photodiodes to the VCCD.
Table 22. FRAME TIMING
Full Resolution, High Gain or Low Gain
Device
Pin
Dual
VOUTa
VOUTc
Quad
Dual
VOUTa
VOUTb
Single
VOUTa
1/4 Resolution, High Gain or Low Gain
Dual
VOUTa
VOUTc
Quad
Dual
VOUTa
VOUTb
Single
VOUTa
1/4 Resolution XLDR
Dual
VOUTa
VOUTc
Quad
Dual
VOUTa
VOUTb
Single
VOUTa
V1T
F1T
F1B
F1T
F1B
F1T
F1B
V2T
F2T
F4B
F2T
F4B
F2T
F4B
V3T
F3T
F3B
F3T
F3B
F3T
F3B
V4T
F4T
F2B
F4T
F2B
F4T
F2B
V1B
F1B
F1B
F1B
V2B
F2B
F2B
F2B
V3B
F3B
F3B
F3B
V4B
F4B
F4B
F4B
H1Sa
P1
P1Q
P1XL
H1Ba
P1
P1Q
P1XL
H2Sa
P2
P2Q
P2XL
H2Ba
P2
P2Q
P2XL
Ra
RHG/RLG
RHGQ/RLGQ
RXL
H1Sb
P1
P1Q
P1XL
H1Bb
P1
P2
P1
H2Sb
P2
P1Q
P2Q
P2
P1Q
P2Q
P1XL
P2XL
P2Q
P1XL
P2XL
P2XL
H2Bb
P2
P1
P2
P1
P2Q
P1Q
P2Q
P1Q
P2XL
P1XL
P2XL
P1XL
Rb
RHG/
RLG
(Note 1)
RHG/
RLG
(Note 1)
RHGQ/
RLGQ
(Note 1)
RHGQ/
RLGQ
(Note 1)
RXL
(Note 1)
RXL
(Note 1)
R2ab
R2HG/R2LG
FDGab
R2HGQ/R2LGQ
−9 V
R2XL
−9 V
−9 V
H1Sc
P1
(Note 1)
P1Q
(Note 1)
P1XL
(Note 1)
H1Bc
P1
(Note 1)
P1Q
(Note 1)
P1XL
(Note 1)
H2Sc
P2
(Note 1)
P2Q
(Note 1)
P2XL
(Note 1)
H2Bc
P2
(Note 1)
P2Q
(Note 1)
P2XL
(Note 1)
Rc
RHG/RLG
(Note 1)
RHGQ/RLGQ
(Note 1)
RXL
(Note 1)
H1Sd
P1
(Note 1)
P1Q
(Note 1)
P1XL
(Note 1)
H1Bd
P1
H2Sd
P2
(Note 1)
P2
P1Q
(Note 1)
P2Q
(Note 1)
P2Q
P1XL
(Note 1)
P2XL
(Note 1)
P2XL
(Note 1)
H2Bd
P2
P1
(Note 1)
P2Q
P1Q
(Note 1)
P2XL
P1XL
(Note 1)
Rd
RHG/
RLG
(Note 1)
(Note 1)
RHGQ/
RLGQ
(Note 1)
(Note 1)
RXL
(Note 1)
(Note 1)
R2cd
R2HG/R2LG
(Note 1)
R2HGQ/R2LGQ
(Note 1)
R2XL
(Note 1)
FDGcd
−9 V
−9 V
−9 V
SHP
SHP1
SHPQ
(Note 4)
SHD
SHD1
SHDQ
(Note 5)
1. This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interline Transfer
CCD family of products.
2. SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
3. This note left intentionally empty.
4. Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
5. Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
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32
KAI−16070
Line Timing
This timing is for transferring one line of charge from the VCCD to the HCCD.
Table 23. LINE TIMING
Full Resolution, High Gain or Low Gain
Device
Pin
Dual
VOUTa
VOUTc
Quad
Dual
VOUTa
VOUTb
Single
VOUTa
1/4 Resolution, High Gain or Low Gain
Dual
VOUTa
VOUTc
Quad
Dual
VOUTa
VOUTb
Single
VOUTa
1/4 Resolution XLDR
Dual
VOUTa
VOUTc
Quad
Dual
VOUTa
VOUTb
Single
VOUTa
V1T
L1T
L1B
2 × L1T
2 × L1B
2 × L1T
2 × L1B
V2T
L2T
L4B
2 × L2T
2 × L4B
2 × L2T
2 × L4B
V3T
L3T
L3B
2 × L3T
2 × L3B
2 × L3T
2 × L3B
V4T
L4T
L2B
2 × L4T
2 × L2B
2 × L4T
2 × L2B
V1B
L1B
2 × L1B
2 × L1B
V2B
L2B
2 × L2B
2 × L2B
V3B
L3B
2 × L3B
2 × L3B
V4B
L4B
2 × L4B
H1Sa
P1L
P1LQ
P3XL
H1Ba
P1L
P1LQ
P3XL
H2Sa
P2L
P2LQ
P4XL
H2Ba
P2L
P2LQ
P4XL
Ra
RHG/RLG
RHGQ/RLGQ
RXL
H1Sb
P1L
P1LQ
P3XL
H1Bb
P1L
P2L
P1L
H2Sb
P2L
P1LQ
P2LQ
P2L
2 × L4B
P1LQ
P2LQ
P3XL
P4XL
P2LQ
P3XL
P4XL
P4XL
H2Bb
P2L
P1L
P2L
P1L
P2LQ
P1LQ
P2LQ
P1LQ
P4XL
P3XL
P4XL
P3XL
Rb
RHG/
RLG
(Note 1)
RHG/
RLG
(Note 1)
RHGQ/
RLGQ
(Note 1)
RHGQ/
RLGQ
(Note 1)
RXL
(Note 1)
RXL
(Note 1)
R2ab
R2HG/R2LG
FDGab
R2HGQ/R2LGQ
−9 V
R2XL
−9 V
−9 V
H1Sc
P1L
(Note 1)
P1LQ
(Note 1)
P3XL
(Note 1)
H1Bc
P1L
(Note 1)
P1LQ
(Note 1)
P3XL
(Note 1)
H2Sc
P2L
(Note 1)
P2LQ
(Note 1)
P4XL
(Note 1)
H2Bc
P2L
(Note 1)
P2LQ
(Note 1)
P4XL
(Note 1)
Rc
RHG/RLG
(Note 1)
RHGQ/RLGQ
(Note 1)
RXL
(Note 1)
H1Sd
P1L
(Note 1)
P1LQ
(Note 1)
P3XL
(Note 1)
H1Bd
P1L
H2Sd
P2L
(Note 1)
P2L
P1LQ
(Note 1)
P2LQ
(Note 1)
P2LQ
P3XL
(Note 1)
P4XL
(Note 1)
P4XL
(Note 1)
H2Bd
P2L
P1L
(Note 1)
P2LQ
P1LQ
(Note 1)
P4XL
P3XL
(Note 1)
Rd
RHG/
RLG
(Note 1)
(Note 1)
RHGQ/
RLGQ
(Note 1)
(Note 1)
RXL
(Note 1)
(Note 1)
R2cd
R2HG/R2LG
(Note 1)
R2HGQ/R2LGQ
(Note 1)
R2XL
(Note 1)
FDGcd
−9 V
−9 V
−9 V
SHP
SHP1
SHPQ
(Note 4)
SHD
SHD1
SHDQ
(Note 5)
1. This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interline Transfer
CCD family of products.
2. SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
3. The notation 2× L1B means repeat the L1B timing twice for every line. This sums two rows into the HCCD.
4. Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
5. Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
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33
KAI−16070
Pixel Timing
This timing is for transferring one pixel from the HCCD to the output amplifier.
Table 24. PIXEL TIMING
Full Resolution, High Gain or Low Gain
Device
Pin
Dual
VOUTa
VOUTc
Quad
Dual
VOUTa
VOUTb
Single
VOUTa
1/4 Resolution, High Gain or Low Gain
Dual
VOUTa
VOUTc
Quad
Dual
VOUTa
VOUTb
Single
VOUTa
1/4 Resolution XLDR
Dual
VOUTa
VOUTc
Quad
Dual
VOUTa
VOUTb
V1T
−9 V
−9 V
−9 V
V2T
−9 V
−9 V
−9 V
V3T
0V
0V
0V
V4T
0V
0V
0V
V1B
−9 V
−9 V
−9 V
V2B
0V
0V
0V
V3B
0V
0V
0V
V4B
−9 V
−9 V
−9 V
H1Sa
P1
P1Q
P1XL
H1Ba
P1
P1Q
P1XL
H2Sa
P2
P2Q
P2XL
H2Ba
P2
P2Q
P2XL
Ra
RHG/RLG
RHGQ/RLGQ
RXL
H1Sb
P1
P1Q
P1XL
H1Bb
P1
P2
P1
H2Sb
P2
P1Q
P2Q
P2
P1Q
P2Q
P1XL
P2XL
P2Q
Single
VOUTa
P1XL
P2XL
P2XL
H2Bb
P2
P1
P2
P1
P2Q
P1Q
P2Q
P1Q
P2XL
P1XL
P2XL
P1XL
Rb
RHG/
RLG
(Note 1)
RHG/
RLG
(Note 1)
RHGQ/
RLGQ
(Note 1)
RHGQ/
RLGQ
(Note 1)
RXL
(Note 1)
RXL
(Note 1)
R2ab
R2HG/R2LG
R2ab
R2HGQ/R2LGQ
−9 V
R2XL
−9 V
−9 V
H1Sc
P1
(Note 1)
P1Q
(Note 1)
P1XL
(Note 1)
H1Bc
P1
(Note 1)
P1Q
(Note 1)
P1XL
(Note 1)
H2Sc
P2
(Note 1)
P2Q
(Note 1)
P2XL
(Note 1)
H2Bc
P2
(Note 1)
P2Q
(Note 1)
P2XL
(Note 1)
Rc
RHG/RLG
(Note 1)
RHGQ/RLGQ
(Note 1)
RXL
(Note 1)
H1Sd
P1
(Note 1)
P1Q
(Note 1)
P1XL
(Note 1)
H1Bd
P1
H2Sd
P2
(Note 1)
P2
P1Q
(Note 1)
P2Q
(Note 1)
P2Q
P1XL
(Note 1)
P2XL
(Note 1)
P2XL
(Note 1)
H2Bd
P2
P1
(Note 1)
P2Q
P1Q
(Note 1)
P2XL
P1XL
(Note 1)
Rd
RHG/
RLG
(Note 1)
(Note 1)
RHGQ/
RLGQ
(Note 1)
(Note 1)
RXL
(Note 1)
(Note 1)
R2cd
R2HG/R2LG
(Note 1)
R2HGQ/R2LGQ
(Note 1)
R2XL
(Note 1)
R2ab
−9 V
−9 V
−9 V
SHP
(Note 2)
SHP1
SHPQ
(Note 4)
SHD
(Note 2)
SHD1
SHDQ
(Note 5)
1. This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interline Transfer
CCD family of products.
2. SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
3. This note intentionally left empty.
4. Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
5. Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
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34
KAI−16070
Timing Diagrams
Frame TimingDiagrams
NOTE: See Table 22 for pin assignments.
Figure 28. Frame Timing Diagram
The charge in the photodiodes begins its transfer to the
VCCD on the rising edge of the +13 V pulse and is
completed by the falling edge of the +13 V pulse on F1T and
F1B. During the time period when F1T and F1B are at +13 V
antiblooming protection is disabled. The photodiode
integration time ends on the falling edge of the +13 V pulse.
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35
KAI−16070
Line Timing Diagrams
NOTE: See Table 23 for device pin assignments.
Figure 29. Line Timing Diagram
If the line is to be dumped then clock the FDGab and
FDGcd pins as shown. This dumping process eliminates a
line of charge and the HCCD does not have to be clocked.
To transfer a line from the VCCD to the HCCD without
dumping the charge, hold the FDGab and FDGcd pins at a
constant −9 V.
4Tv
L4B, L1T
L1B, L2T
FDGab,
FDGcd
Detail A
NOTE: See Table 23 for device pin assignments.
Figure 30. Fast Dump Gate Timing Detail A
FDG pin must not begin its transition from +5 V back to
−9 V until the last VCCD timing edge has completed its
transition.
When the VCCD is clocked while the FDGab and FDGcd
pins are at +5 V, charge is diverted to a drain instead of
transferring to the HCCD. The FDG pins must be at +5 V
before the first VCCD timing edge begins its transition. The
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36
KAI−16070
1/4 Resolution Line Timing
Time duration is 8Tv
+3 V
RHGQ
−2 V
P1Q
P2Q
P1Q
P1LQ
P2Q
P2LQ
0V
−4.4 V
This extra clock cycle is important!
NOTE: See Table 23 center column for pin assignments.
Figure 31. 1/4 Resolution Line Timing Diagram
The HCCD 1/4 resolution timing has one HCCD clock
cycle added. This does a one pixel shift of the HCCD before
the 2− pixel charge summing starts on the output amplifier.
The one pixel shift is necessary because of the odd number
(11 pixels) of dummy pixels at the start of the HCCD.
Without the one pixel shift the last dark reference columns
would be summed with the first photoactive column instead
of adding together the first two photoactive columns.
XLDR Line Timing
Time duration is 8Tv
+3 V
RXL
−2 V
P1XL
P3XL
P1XL
P2XL
P4XL
P2XL
0V
−4.4 V
This extra clock cycle is important!
NOTE: See Table 23 right columns for pin assignments.
Figure 32. XLDR Line Timing Diagram
Like the 1/4 resolution mode, the XLDR timing also sums two pixels on the output amplifier sense node. Therefore it also
requires one HCCD clock cycle within the line timing.
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KAI−16070
Electronic Shutter Timing Diagram
tV
2
tV
2
tSUB
VES
SUB
VAB
0V
VCCD Clock
−9 V
Figure 33. Electronic Shutter Timing Diagram
shutter pulse as long as the HCCD does not contain valid
image data.
For short exposures less than one line time, the electronic
shutter pulse can appear inside the frame timing diagram of
Figure 28. Any electronic shutter pulse transition should be
tV/2 away from any VCCD clock transition.
The electronic shutter pulse can be inserted at the end of
any line of the HCCD timing. The HCCD should be empty
when the electronic shutter is pulsed. A recommended
position for the electronic shutter is just after the last pixel
is read out of a line. The VCCD clocks should not resume
until at least tV/2 ms after the electronic shutter pulse has
finished. The HCCD clocks can be run during the electronic
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KAI−16070
Pixel Timing Diagrams
High Gain Pixel Timing
Te
Video
+3 V
RHG
−2 V
+3 V
R2HG
−2 V
SHP1
SHD1
0V
P1
−4.4 V
0V
P2
−4.4 V
NOTE: See Table 24 left columns for pin assignments.
Figure 34. High Gain Pixel Timing
Use this pixel timing to read out every pixel at high gain.
If the sensor is to be permanently operated at high gain, the
R2ab and R2cd pins can be left floating or set to any DC
voltage between +3 V and +5 V. They are internally biased
to +4.3 V. The SHP1 and SHD1 pulses indicate where the
camera electronics should sample the video waveform. The
SHP1 and SHD1 pulses are not applied to the image sensor.
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KAI−16070
Low Gain Pixel Timing
Te
Video
+3 V
RLG
−2 V
+3 V
R2LG
−2 V
SHP1
SHD1
0V
P1
−4.4 V
0V
P2
−4.4 V
NOTE: See Table 24 left columns for pin assignments.
Figure 35. Low Gain Pixel Timing
Use this timing to read out every pixel at low gain. If the
sensor is to be permanently operated at low gain, the Ra, Rb,
Rc, and Rd pins can be set to any DC voltage between +3 V
and +5 V. The SHP1 and SHD1 pulses indicate where the
camera electronics should sample the video waveform. The
SHP1 and SHD1 pulses are not applied to the image sensor.
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KAI−16070
1/4 Resolution High Gain Pixel Timing
Te
Video
+3 V
RHGQ
−2 V
+3 V
R2HGQ
−2 V
SHPQ
SHDQ
0V
P1Q
−4.4 V
0V
P2Q
−4.4 V
NOTE: See Table 24 center columns for pin assignments.
Figure 36. 1/4 Resolution High Gain Pixel Timing
Use this pixel timing to read out every pixel at high gain.
If the sensor is to be permanently operated at high gain, the
R2ab and R2cd pins can be left floating or set to any DC
voltage between +3 V and +5 V. They are internally biased
to +4.3 V. The SHPQ and SHDQ pulses indicate where the
camera electronics should sample the video waveform. The
SHPQ and SHDQ pulses are not applied to the image sensor.
The Ra, Rb, Rc, and Rd pins are pulsed at half the
frequency of the HCCD clocks. This causes two pixels to be
summed on the output amplifier sense node. The SHPQ and
SHDQ clocks are also half the frequency of the HCCD
clocks.
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KAI−16070
1/4 Resolution Low Gain Pixel Timing
Te
Video
+3 V
RHGQ
−2 V
+3 V
R2HGQ
−2 V
SHPQ
SHDQ
0V
P1Q
−4.4 V
0V
P2Q
−4.4 V
NOTE: See Table 24 center columns for pin assignments.
Figure 37. 1/4 Resolution Low Gain Pixel Timing
Use this timing to read out every pixel at low gain. If the
sensor is to be permanently operated at low gain, the Ra, Rb,
Rc, and Rd pins can be set to any DC voltage between +3 V
and +5 V. The SHPQ and SHDQ pulses indicate where the
camera electronics should sample the video waveform. The
SHPQ and SHDQ pulses are not applied to the image sensor.
The R2ab, and R2cd pins are pulsed at half the frequency
of the HCCD clocks. This causes two pixels to be summed
on the output amplifier sense node. The SHPQ and SHDQ
clocks are also half the frequency of the HCCD clocks.
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KAI−16070
NOTE: See Table 24 right columns for pin assignments.
Figure 38. XLDR Timing with Constant HCCD. Operating at 20 MHz
NOTE: See Table 24 right columns for pin assignments.
Figure 39. XLDR Timing with Variable HCCD Clocking
Use this pixel timing to operate the image sensor in the
extended linear dynamic range mode (XLDR). This mode
requires two sets of analog front end (AFE) signal
processing electronics for each output. As shown in
Figure 39, one AFE samples the pixel at low gain (SHPLG
and SHDLG) and the other AFE samples the pixel at high
gain (SHPHG and SHDHG).
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KAI−16070
SHPLG
SHDLG
sensor. Lens flare caused by inexpensive optics or even dust
on the lens will limit the dynamic range.
This timing shows the HCCD in Figure 39, not being
clocked at a constant frequency. If this is a problem for the
HCCD timing generator, then the HCCD may be clocked at
a constant frequency at the expense of about 33% slower
frame rate.
Two HCCD pixels are summed on the output amplifier to
obtain enough charge to fully use the 82 dB dynamic range
of the XLDR timing. Combined with two−line VCCD
summing, a total of 160,000 electrons of signal (4x 40,000)
can be sampled with 12 electrons or less noise. 82 db linear
dynamic range is very large. Make certain the camera optics
is capable of focusing an 82 dB dynamic range image on the
Low gain
Low Gain AFE
digital out
Sensor output
SHPHG
CAUTION: In the XDR mode this output of
the CCD can produce large signals that
may damage some AFE devices and
should be electrically attenuated!
High gain
digital out
SHDHG
High Gain AFE
Figure 40. Block Diagram Showing the AFE Connections for XLDR Timing
VCCD Clock Rise and Fall Time
90%
tV
10%
tVF
tVR
tV
tVF
tVR
Figure 41. VCCD Clock Rise Time and Fall Time
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KAI−16070
MECHANICAL INFORMATION
Completed Assembly
Notes:
1. See Ordering Information for marking code.
2. Cover glass not to overhang package holes or outer ceramic edges.
3. Glass epoxy not to extend over image array.
4. No materials to interfere with clearance through package holes.
5. Units: IN [MM]
Figure 42. Completed Assembly of Sealed Cover Glass Configuration (1 of 2)
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KAI−16070
Notes:
1. Units IN [MM]
Figure 43. Completed Assembly of Sealed Cover Glass Configuration (2 of 2)
SHOWN WITH TAPED−ON COVER GLASS
Figure 44. Completed Assembly View of Taped Cover Glass Configuration
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46
KAI−16070
Cover Glass, AR Coated, 2 Sides
Notes:
1. Substrate = Schott D263T eco
2. Dust, Scratch, Inclusion Specification:
a.) 20 mm Max size in Zone A
b.) Zone A = 1.474 x 1.000 [16.43 x 10.08] Centered
3. MAR coated both sides
4. Spectral Transmission
a.) 350 − 365 nm: T ≥ 88%
b.) 365 − 405 nm: T ≥ 94%
c.) 405 − 450 nm: T ≥ 98%
d.) 450 − 650 nm: T ≥ 99%
e.) 650 − 690 nm: T ≥ 98%
f.) 690 − 770 nm: T ≥ 94%
g.) 770 − 870 nm: T ≥ 88%
5. Units: IN [MM]
Figure 45. Cover Glass, AR Coated, 2 Sides
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47
KAI−16070
Cover Glass, Clear No Coatings (Taped)
Notes:
1.
2.
3.
4.
Substrate = Schott D263T eco
Dust, Scratch, Inclusion Specification: None
No Optical Coatings on this Glass
Units: MM
Figure 46. Cover Glass, Clear No Coatings (Taped)
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48
KAI−16070
Cover Glass Transmission
Figure 47. Cover Glass Transmission
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
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KAI−16070/D