KAI-2001
1600 (H) x 1200 (V) Interline
CCD Image Sensor
Description
The KAI−2001 Image Sensor is a high-performance 2-million pixel
sensor designed for a wide range of medical, scientific and machine
vision applications. The 7.4 mm square pixels with microlenses
provide high sensitivity and the large full well capacity results in high
dynamic range. The split horizontal register offers a choice of single or
dual output allowing either 15 or 30 frame per second (fps) video rate
for the progressively scanned images. Also included is a fast line
dump for sub-sampling at higher frame rates. The vertical overflow
drain structure provides anti-blooming protection and enables
electronic shuttering for precise exposure control. Other features
include low dark current, negligible lag and low smear.
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Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Interline CCD, Progressive Scan
Total Number of Pixels
1640 (H) × 1214 (V)
Number of Effective Pixels
1608 (H) × 1208 (V)
Number of Active Pixels
1600 (H) × 1200 (V)
Pixel Size
7.4 mm (H) × 7.4 mm (V)
Active Image Size
13.38 mm (H) × 9.52 mm (V),
14.803 mm (Diagonal),
1″ Optical Format
Aspect Ratio
4:3
Number of Outputs
1 or 2
Saturation Signal
40,000 e−
Quantum Efficiency
−ABA
−CBA (RGB)
55%
45%, 42%, 35%
Output Sensitivity
16 mV/e−
Total System Noise
40 MHz
20 MHz
40 e−
23 e−
Dark Current
< 0.5 nA/cm2
Dark Current Doubling Temp.
7°C
Dynamic Range
60 dB
Charge Transfer Efficiency
> 0.999999
Blooming Suppression
300X
Smear
80 dB
Image Lag
< 10 e−
Maximum Data Rate
40 MHz
Package
32-pin, CERDIP
Figure 1. KAI−2001 Interline CCD
Image Sensor
Features
•
•
•
•
•
•
•
High Resolution
High Sensitivity
High Dynamic Range
Low Noise Architecture
High Frame Rate
Binning Capability for Higher Frame Rate
Electronic Shutter
Applications
• Machine Vision
• Scientific
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 3
1
Publication Order Number:
KAI−2001/D
KAI−2001
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−2001 IMAGE SENSOR
Part Number
Description
KAI−2001−AAA−CF−BA
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Quartz Cover Glass (No Coatings), Standard Grade
KAI−2001−AAA−CF−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Quartz Cover Glass (No Coatings), Engineering Sample
KAI−2001−AAA−CP−BA
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, Standard Grade
KAI−2001−AAA−CP−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, Engineering Sample
KAI−2001−AAA−CR−BA*
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade
KAI−2001−AAA−CR−AE*
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample
KAI−2001−ABA−CD−BA
Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−2001−ABA−CD−AE
Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−2001−ABA−CP−BA
Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, Standard Grade
KAI−2001−ABA−CP−AE
Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass, Engineering Sample
KAI−2001−CBA−CD−BA*
Color Gen1 (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−2001−CBA−CD−AE*
Color Gen1 (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Marking Code
KAI−2001
Serial Number
KAI−2001M
Serial Number
KAI−2001CM
Serial Number
*Not recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
Description
KAI−2020−12−20−A−EVK
Evaluation Board, 12 Bit, 20 MHz (Complete Kit)
KAI−2020−10−40−A−EVK
Evaluation Board, 10 Bit, 40 MHz (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAI−2001
DEVICE DESCRIPTION
Architecture
4 Dark Rows
1600 (H) x 1200 (V)
Active Pixels
16 Dark Columns
G R
4 Buffer Columns
B G
G R
4 Buffer Columns
16 Dark Columns
4 Buffer Rows
B G
B G
4 Dummy Pixels
4 Dummy Pixels
Pixel
1,1
B G
G R
G R
4 Buffer Rows
2 Dark Rows
Video L
Video R
Single
4
16
4
or
Dual
Output
4
16
4
1600
800
800
4
16
4
4
16
4
Figure 2. Sensor Architecture
out Video R. Each row consists of 4 empty pixels followed
by 16 light shielded pixels followed by 800 photosensitive
pixels. When reconstructing the image, data from Video R
will have to be reversed in a line buffer and appended to the
Video L data.
There are 4 dark reference rows at the top and 2 dark rows
at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 16 dark columns on the left or right side of the
image sensor as a dark reference.
Of the 16 dark columns, the first and last dark columns
should not be used for determining the zero signal level.
Some light does leak into the first and last dark columns.
Only use the center 14 columns of the 16 column dark
reference.
There are 2 light shielded rows followed 1,208
photoactive rows and finally 4 more light shielded rows.
The first 4 and the last 4 photoactive rows are buffer rows
giving a total of 1,200 lines of image data.
In the single output mode all pixels are clocked out of the
Video L output in the lower left corner of the sensor. The first
4 empty pixels of each line do not receive charge from the
vertical shift register. The next 16 pixels receive charge from
the left light shielded edge followed by 1,608 photosensitive
pixels and finally 16 more light shielded pixels from the
right edge of the sensor. The first and last 4 photosensitive
pixels are buffer pixels giving a total of 1,600 pixels of
image data.
In the dual output mode the clocking of the right half of the
horizontal CCD is reversed. The left half of the image is
clocked out Video L and the right half of the image is clocked
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3
KAI−2001
Pixel
ÉÉÉÉÉÉÉÉÉ
ËËËËË
ÉÉÉÉÉÉÉÉÉ
ËËËËË
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
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ËËËËË
ÉÉÉÉÉÉÉÉÉ
ËËËËË
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
Top View
Direction
of
Charge
Transfer
Cross Section Down Through VCCD
V1
V2
V1
7.4 mm
V1
Photodiode
Transfer
Gate
ÉÉ
ÉÉ
ÉÉ
ÉÉ
n−
V2
n−
ÉÉ
ÉÉ
n−
n
p Well (GND)
Direction of
Charge
Transfer
7.4 mm
n Substrate
True Two Phase Burried Channel VCCD
Lightshield over VCCD not shown
Cross Section Through
Photodiode and VCCD Phase 1
Cross Section Through Photodiode
and VCCD Phase 2 at Transfer Gate
Light Shield
Light Shield
É
É
p
Photodiode
ÉÉ
ÏÏÏÏÏÏÏ
É
ÉÉ
ÉÉÏÏÏÏÏÏÏÉ ÉÉ
V1
p+
n
p
n
Transfer
Gate
p+
p
p
n
p
ÏÏÏÏÏÏ
ÉÉ
ÏÏÏÏÏÏÉÉ
V2
n
p
p
p
n Substrate
n Substrate
NOTE: Drawings not scale.
p
Cross Section Showing Lenslet
Lenslet
Red Color Filter
Light Shield
Light Shield
VCCD
VCCD
Photodiode
Figure 3. Pixel Architecture
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
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KAI−2001
Vertical to Horizontal Transfer
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË
ËË ËË
ËË ËË
Top View
Direction of
Vertical
Charge
Transfer
V1
Photodiode
Transfer
Gate
V2
V1
Fast
Line
Dump
V2
H2B
H2S
H1B
Lightshield
Not Shown
H1S
Direction of
Horizontal
Charge Transfer
Figure 4. Vertical to Horizontal Transfer Architecture
When the V1 and V2 timing inputs are pulsed, charge in
every pixel of the VCCD is shifted one row towards the
HCCD. The last row next to the HCCD is shifted into the
HCCD. When the VCCD is shifted, the timing signals to the
HCCD must be stopped. H1 must be stopped in the high state
and H2 must be stopped in the low state. The HCCD
clocking may begin tHD ms after the falling edge of the V1
and V2 pulse.
Charge is transferred from the last vertical CCD phase into
the H1S horizontal CCD phase. Refer to Figure 27 for an
example of timing that accomplishes the vertical to
horizontal transfer of charge.
If the fast line dump is held at the high level (FDH) during
a vertical to horizontal transfer, then the entire line is
removed and not transferred into the horizontal register.
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KAI−2001
Horizontal Register to Floating Diffusion
RD
R
n+
n
OG
n+
Floating
Diffusion
H2B
H1S
H1B
ÏÏ
ÏÏÏ
n−
H2S
n−
n (burried channel)
H2B
ÏÏÏ
n−
H1S
H1B
ÏÏÏÏ
n−
p (GND)
n (SUB)
Figure 5. Horizontal Register to Floating Diffusion Architecture
When the HCCD is shifting valid image data, the timing
inputs to the electronic shutter (SUB), VCCD (V1, V2),
and fast line dump (FD) should be not be pulsed. This
prevents unwanted noise from being introduced. The HCCD
is a type of charge coupled device known as a pseudo-two
phase CCD. This type of CCD has the ability to shift charge
in two directions. This allows the entire image to be shifted
out to the video L output, or to the video R output (left/right
image reversal). The HCCD is split into two equal halves of
824 pixels each. When operating the sensor in single output
mode the two halves of the HCCD are shifted in the same
direction. When operating the sensor in dual output mode
the two halves of the HCCD are shifted in opposite
directions. The direction of charge transfer in each half is
controlled by the H1BL, H2BL, H1BR, and H2BR timing
inputs.
The HCCD has a total of 1,648 pixels. The 1,640 vertical
shift registers (columns) are shifted into the center 1,640
pixels of the HCCD. There are 4 pixels at both ends of the
HCCD, which receive no charge from a vertical shift
register. The first 4 clock cycles of the HCCD will be empty
pixels (containing no electrons). The next 16 clock cycles
will contain only electrons generated by dark current in the
VCCD and photodiodes. The next 1,608 clock cycles will
contain photo-electrons (image data). Finally, the last 16
clock cycles will contain only electrons generated by dark
current in the VCCD and photodiodes. Of the 16 dark
columns, the first and last dark columns should not be used
for determining the zero signal level. Some light does leak
into the first and last dark columns. Only use the center 14
columns of the 16 column dark reference.
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KAI−2001
Horizontal Register Split
H1
H2
H2
H1
H1
H2
H2
H1BL
H2SL
H2BL
H1SL
H1BL
H2SL
H1BR
Pixel
824
H1
H1SR
H1
H2
H2BR
H2SR
Pixel
825
Single Output
H1
H2
H2
H1
H1
H2
H1
H1
H2
H2
H1BL
H2SL
H2BL
H1SL
H1BL
H2SL
H1BR
H1SR
H2BR
H2SR
Pixel
824
Pixel
825
Dual Output
Figure 6. Horizontal Register
Dual Output Operation
In dual output mode the connections to the H1BR and
H2BR pins are swapped from the single output mode to
change the direction of charge transfer of the right side
horizontal shift register. In dual output mode both VDDL
and VDDR (pins 25, 24) should be connected to 15 V.
The H1 timing from the timing diagrams should be applied
to H1SL, H1BL, H1SR, H1BR, and the H2 timing should be
applied to H2SL, H2BL, H2SR, and H2BR. The clock driver
generating the H1 timing should be connected to pins 4, 3,
13, and 14. The clock driver generating the H2 timing should
be connected to pins 5, 2, 12, and 15. The horizontal CCD
should be clocked for 4 empty pixels plus 16 light shielded
pixels plus 804 photoactive pixels for a total of 824 pixels.
If the camera is to have the option of dual or single output
mode, the clock driver signals sent to H1BR and H2BR may
be swapped by using a relay. Another alternative is to have
two extra clock drivers for H1BR and H2BR and invert the
signals in the timing logic generator. If two extra clock
drivers are used, care must be taken to ensure the rising and
falling edges of the H1BR and H2BR clocks occur at the
same time (within 3 ns) as the other HCCD clocks.
Single Output Operation
When operating the sensor in single output mode all pixels
of the image sensor will be shifted out the Video L output
(pin 31). To conserve power and lower heat generation the
output amplifier for Video R may be turned off by
connecting VDDR (pin 24) and VOUTR (pin 24) to GND
(zero volts).
The H1 timing from the timing diagrams should be
applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing
should be applied to H2SL, H2BL, H2SR, and H1BR. In
other words, the clock driver generating the H1 timing
should be connected to pins 4, 3, 13, and 15. The clock driver
generating the H2 timing should be connected to pins 5, 2,
12, and 14. The horizontal CCD should be clocked for 4
empty pixels plus 16 light shielded pixels plus 1,608
photoactive pixels plus 16 light shielded pixels for a total of
1,644 pixels.
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KAI−2001
Output
H1S
HCCD
Charge
Transfer
H2B
H2S
H1B
H1S
H2B
VDD
OG
R
RD
VDD
Floating
Diffusion
VOUT
Source
Follower
#1
VSS
Source
Follower
#2
Source
Follower
#3
Figure 7. Output Architecture
Charge packets contained in the horizontal register are
dumped pixel by pixel onto the floating diffusion (FD)
output node whose potential varies linearly with the quantity
of charge in each packet. The amount of potential charge is
determined by the expression DVFD = DQ / CFD.
A three-stage source-follower amplifier is used to buffer
this signal voltage off chip with slightly less than unity gain.
The translation from the charge domain to the voltage
domain is quantified by the output sensitivity or charge to
voltage conversion in terms of microvolts per electron
(mV/e−). After the signal has been sampled off chip, the reset
clock (R) removes the charge from the floating diffusion and
resets its potential to the reset drain voltage (RD).
When the image sensor is operated in the binned or
summed interlaced modes there will be more than 40,000 e−
in the output signal. The image sensor is designed with
a 16 mV/e charge to voltage conversion on the output. This
means a full signal of 40,000 electrons will produce
a 640 mV change on the output amplifier. The output
amplifier was designed to handle an output swing of 640 mV
at a pixel rate of 40 MHz. If 80,000 electron charge packets
are generated in the binned or summed interlaced modes
then the output amplifier output will have to swing
1,280 mV. The output amplifier does not have enough
bandwidth (slew rate) to handle 1,280 mV at 40 MHz.
Hence, the pixel rate will have to be reduced to 20 MHz if
the full dynamic range of 80,000 electrons is desired.
The charge handling capacity of the output amplifier is
also set by the reset clock voltage levels. The reset clock
driver circuit is very simple if an amplitude of 5 V is used.
But the 5 V amplitude restricts the output amplifier charge
capacity to 40,000 electrons. If the full dynamic range of
80,000 electrons is desired then the reset clock amplitude
will have to be increased to 7 V.
If you only want a maximum signal of 40,000 electrons in
binned or summed interlaced modes, then a 40 MHz pixel
rate with a 5 V reset clock may be used. The output of the
amplifier will be unpredictable above 40,000 electrons so be
sure to set the maximum input signal level of your analog to
digital converter to the equivalent of 40,000 electrons
(640 mV).
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KAI−2001
VSS
VOUTL
ESD
fV2
fV1
VSUB
GND
VDDL
VDDR
GND
VSUB
fV1
fV2
GND
VOUTR
VSS
Pin Description and Physical Orientation
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
9
fH1SL
fH2SL
GND
OGL
RDL
RDR
10
11
12
13
14
15
16
fRR
8
fH2BR
7
fH1BR
6
fH1SR
5
fH2SR
4
fFD
3
OGR
2
fH1BL
fRL
1
fH2BL
Pixel1,1
1, 1
Pixel
Figure 8. Package Pin Designations − Top View
Table 4. PIN DESCRIPTION
Pin
Name
1
fRL
2
Pin
Description
Name
Description
Reset Gate, Left
17
VSS
fH2BL
H2 Barrier, Left
18
VOUTR
3
fH1BL
H1 Barrier, Left
19
GND
Ground
4
fH1SL
H1 Storage, Left
20
fV2
Vertical Clock, Phase 2
5
fH2SL
H2 Storage, Left
21
fV1
Vertical Clock, Phase 1
6
GND
Ground
22
VSUB
Substrate
7
OGL
Output Gate, Left
23
GND
Ground
8
RDL
Reset Drain, Left
24
VDDR
VDD, Right
9
RDR
Reset Drain, Right
25
VDDL
VDD, Left
10
ORG
Output Gate, Right
26
GND
Ground
11
FD
Fast Line Dump Gate
27
VSUB
Substrate
12
fH2SR
H2 Storage, Right
28
fV1
Vertical Clock, Phase 1
13
fH1SR
H1 Storage, Right
29
fV2
Vertical Clock, Phase 2
14
fH1BR
H1 Barrier, Right
30
ESD
ESD
15
fH2BR
H2 Barrier, Right
31
VOUTL
16
fRR
Reset Gate, Right
32
VSS
NOTE: The pins are on a 0.070″ spacing.
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9
Output Amplifier Return
Video Output, Right
Video Output, Left
Output Amplifier Return
KAI−2001
IMAGING PERFORMANCE
Table 5. TYPICAL OPERATIONAL CONDITIONS
(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)
Condition
Description
Notes
Frame Time
237 ms
1
Horizontal Clock Frequency
10 MHz
Light Source
Continuous Red, Green and Blue LED Illumination Centered at 450, 530 and 650 nm
Operation
Nominal Operating Voltages and Timing
2, 3
1. Electronic shutter is not used. Integration time equals frame time.
2. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP−8115.
3. For monochrome sensor, only green LED used.
Specifications
Table 6. PERFORMANCE SPECIFICATIONS
Temperature
Tested at
(5C)
Min.
Nom.
Max.
Unit
Sampling
Plan
Dark Center Uniformity
N/A
N/A
20
e− rms
Die
27, 40
Dark Global Uniformity
N/A
N/A
5.0
mVpp
Die
27, 40
Global Uniformity (Note 1)
N/A
2.5
5.0
% rms
Die
27, 40
N/A
10
20
% pp
Die
27, 40
27, 40
Description
Symbol
ALL CONFIGURATIONS
Global Peak to Peak Uniformity
(Note 1)
PRNU
Center Uniformity (Note 1)
N/A
1.0
2.0
% rms
Die
Maximum Photoresponse
Non-Linearity (Notes 2, 3)
NL
N/A
2
−
%
Design
Maximum Gain Difference between
Outputs (Notes 2, 3)
DG
N/A
10
−
%
Design
Max. Signal Error due to Non-Linearity
Dif. (Notes 2, 3)
DNL
N/A
1
−
%
Design
Horizontal CCD Charge Capacity
HNe
N/A
100
N/A
ke−
Design
N/A
ke−
Die
ke−
Die
Vertical CCD Charge Capacity
Photodiode Charge Capacity
VNe
N/A
50
PNe
38
40
N/A
Horizontal CCD Charge Transfer
Efficiency
HCTE
0.99999
N/A
N/A
Design
Vertical CCD Charge Transfer
Efficiency
VCTE
0.99999
N/A
N/A
Design
Photodiode Dark Current
IPD
N/A
N/A
40
0.01
350
0.1
e/p/s
nA/cm2
Die
27, 40
Vertical CCD Dark Current
IVD
N/A
N/A
400
0.12
1,711
0.5
e/p/s
nA/cm2
Die
27, 40
Image Lag
Lag
N/A
< 10
50
e−
Design
Anti-Blooming Factor
XAB
100
300
N/A
Vertical Smear
Smr
N/A
80
75
Total Noise (Note 4)
ne−T
−
23
Design
dB
Design
−
e−
rms
Design
e−
rms
Design
Total Noise (Note 5)
ne−T
−
40
−
Dynamic Range (Notes 5, 6)
DR
−
60
−
dB
Design
VODC
4
8.5
14
V
Die
Output Amplifier DC Offset
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10
KAI−2001
Table 6. PERFORMANCE SPECIFICATIONS (continued)
Symbol
Min.
Nom.
Max.
Unit
Sampling
Plan
Output Amplifier Bandwidth
f−3DB
−
140
−
MHz
Design
Output Amplifier Impedance
ROUT
100
130
200
W
Die
Output Amplifier Sensitivity
DV/DN
−
16
−
mV/e−
Design
QEMAX
45
55
N/A
%
Design
lQE
N/A
500
N/A
nm
Design
%
Design
−
−
−
35
42
45
N/A
N/A
N/A
nm
Design
−
−
−
620
540
470
N/A
N/A
N/A
Description
ALL CONFIGURATIONS
KAI−2001−ABA CONFIGURATION
Peak Quantum Efficiency
Peak Quantum Efficiency Wavelength
KAI−2001−CBA CONFIGURATION
Peak Quantum Efficiency
Red
Green
Blue
Peak Quantum Efficiency Wavelength
Red
Green
Blue
QEMAX
lQE
NOTE: N/A = Not Applicable.
1. Per color.
2. Value is over the range of 10% to 90% of photodiode saturation.
3. Value is for the sensor operated without binning.
4. Includes system electronics noise, dark pattern noise and dark current shot noise at 20 MHz.
5. Includes system electronics noise, dark pattern noise and dark current shot noise at 40 MHz.
6. Uses 20LOG (PNe / ne−T).
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11
Temperature
Tested at
(5C)
KAI−2001
TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome with Microlens
0.6
Measured with Glass
Absolute Quantum Efficiency
0.5
0.4
0.3
0.2
0.1
0.0
400
500
600
700
800
900
1000
Wavelength (nm)
Figure 9. Monochrome with Microlens Quantum Efficiency
Monochrome without Microlens
0.12
Absolute Quantum Efficiency
0.10
0.08
0.06
0.04
0.02
0.00
240
340
440
540
640
740
840
Wavelength (nm)
Figure 10. Monochrome without Microlens Quantum Efficiency
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12
940
KAI−2001
Color (Bayer RGB) with Microlens
0.50
0.45
Measured
with Glass
Absolute Quantum Efficiency
0.40
Red
0.35
Green
Blue
0.30
0.25
0.20
0.15
0.10
0.05
0.00
400
500
600
700
800
Wavelength (nm)
Figure 11. Color (Bayer RGB) Quantum Efficiency
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13
900
1000
KAI−2001
Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Monochrome with Microlens
100
Relative Quantum Efficiency (%)
90
Vertical
80
70
60
50
Horizontal
40
30
20
10
0
0
5
10
15
20
25
30
Angle (degress)
Figure 12. Angular Quantum Efficiency
Dark Current vs. Temperature
100,000
10,000
Electrons/Second
VCCD
1,000
100
Photodiodes
10
1
1000/T(K)
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
T (C)
97
84
72
60
50
40
30
21
Figure 13. Dark Current vs. Temperature
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14
KAI−2001
Power-Estimated
Right Output Disabled
500
450
Output Power One Output (mW)
Vertical Power One Output (mW)
400
Horizonatl Power (mW)
Total Power One Output (mW)
Power (mW)
350
300
250
200
150
100
50
0
0
5
10
15
20
25
30
35
40
Horizontal Clock Frequency (MHz)
Figure 14. Power
Frame Rates
70
Dual 2×2 Binning
60
Frame Rate (fps)
50
Dual Output or Single
2×2 Binning
40
30
20
Single Output
10
0
10
15
20
25
Pixel Clock (MHz)
Figure 15. Frame Rates
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15
30
35
40
KAI−2001
DEFECT DEFINITIONS
Table 7. DEFECT DEFINITIONS
Definition
Maximum
Temperature(s)
Tested at (5C)
Notes
Major Dark Field Defective Pixel
Defect ≥ 179 mV
20
27, 40
1
Major Bright Field Defective Pixel
Defect ≥ 15%
20
27, 40
1
Minor Dark Field Defective Pixel
Defect ≥ 57 mV
200
27, 40
Cluster Defect
A group of 2 to 10 contiguous major
defective pixels, but no more than 2 adjacent
defects horizontally.
8
27, 40
1
Column Defect
A group of more than 10 contiguous major
defective pixels along a single column.
0
27, 40
1
Description
1. There will be at least two non-defective pixels separating any two major defective pixels.
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
defects are not included in the defect map. All defective
pixels are reference to pixel 1, 1 in the defect maps.
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16
KAI−2001
TEST DEFINITIONS
Test Regions of Interest
Active Area ROI:
Center 100 by 100 ROI:
Overclocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 16 for a pictorial representation of the regions.
Pixel (1, 1) to Pixel (1600, 1200)
Pixel (750, 550) to
Pixel (849, 649)
Only the active pixels are used for performance and defect
tests.
Horizontal Overclock
Pixel 1,1
Vertical Overclock
Figure 16. Overclock Regions of Interest
Tests
Dark Field Center Non-Uniformity
This test is performed under dark field conditions. Only
the center 100 by 100 pixels of the sensor are used for this
test − pixel (750, 550) to pixel (849, 649).
Dark Field Center Uniformity + Standard Deviation of Center 100 by 100 Pixels in Electrons @
ǒ
Ǔ
DPS Integration Time
Actual Integration Time Used
Units: mV rms. DPS Integration Time: Device Performance Specification Integration Time = 33 ms.
Dark Field Global Non-Uniformity
This test is performed under dark field conditions.
The sensor is partitioned into 192 sub regions of interest,
each of which is 100 by 100 pixels in size. See Figure 17.
The average signal level of each of the 192 sub regions of
interest is calculated. The signal level of each of the sub
regions of interest is calculated using the following formula:
are found. The dark field global uniformity is then calculated
as the maximum signal found minus the minimum signal
level found.
Global Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 80% of saturation
(approximately 32,000 electrons). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 40,000 electrons. Global
uniformity is defined as:
Signal of ROI[i] + (ROI Average in ADU *
* Horizontal Overclock Average in ADU) @
@ mV per Count
Global Uniformity + 100 @
Units : mVpp (millivolts Peak to Peak)
Where i = 1 to 192. During this calculation on the 192 sub
regions of interest, the maximum and minimum signal levels
ǒ
Active Area Standard Deviation
Active Area Signal
Ǔ
Units : % rms
Active Area Signal = Active Area Average − H. Overclock Average
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17
KAI−2001
Bright Field Defect Test
This test is performed with the imager illuminated to
a level such that the output is at 80% of saturation
(approximately 32,000 electrons). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 40,000 electrons.
The average signal level of all active pixels is found.
The bright and dark thresholds are set as:
Global Peak to Peak Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 80% of saturation
(approximately 32,000 electrons). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 40,000 electrons. The sensor
is partitioned into 192 sub regions of interest, each of which
is 100 by 100 pixels in size. See Figure 17. The average
signal level of each of the 192 sub regions of interest (ROI)
is calculated. The signal level of each of the sub regions of
interest is calculated using the following formula:
Dark Defect Threshold = Active Area Signal @ Threshold
Bright Defect Threshold = Active Area Signal @ Threshold
The sensor is then partitioned into 192 sub regions of
interest, each of which is 100 by 100 pixels in size (see
Figure 17). In each region of interest, the average value of
all pixels is found. For each region of interest, a pixel is
marked defective if it is greater than or equal to the median
value of that region of interest plus the bright threshold
specified or if it is less than or equal to the median value of
that region of interest minus the dark threshold specified.
Example for major bright field defective pixels:
• Average value of all active pixels is found to be
416 mV (32,000 electrons).
• Dark defect threshold: 416 mV ⋅ 15% = 62.4 mV.
• Bright defect threshold: 416 mV ⋅ 15% = 62.4 mV.
• Region of interest #1 selected. This region of interest is
pixels 1, 1 to pixels 100, 100.
♦ Median of this region of interest is found to be
416 mV.
♦ Any pixel in this region of interest that is
≥ (416 + 62.4 mV) 478.4 mV in intensity will be
marked defective.
♦ Any pixel in this region of interest that is
≥ (416 − 62.4 mV) 353.6 mV in intensity will be
marked defective.
• All remaining 191 sub regions of interest are analyzed
for defective pixels in the same manner.
Signal of ROI[i] + (ROI Average in ADU *
* Horizontal Overclock Average in ADU) @
@ mV per Count
Where i = 1 to 192. During this calculation on the 192 sub
regions of interest, the maximum and minimum signal levels
are found. The global peak to peak uniformity is then
calculated as:
Global Uniformity +
Max. Signal * Min. Signal
Active Area Signal
Units : % pp
Center Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 80% of saturation
(approximately 32,000 electrons). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 40,000 electrons. Defects are
excluded for the calculation of this test. This test is
performed on the center 100 by 100 pixels of the sensor (see
Figure 17). Center uniformity is defined as:
Center ROI Uniformity + 100 @
ǒ
Center ROI Standard Deviation
Center ROI Signal
Ǔ
Units : % rms
Center ROI Signal = Center ROI Average − H. Overclock Average
Dark Field Defect Test
This test is performed under dark field conditions.
The sensor is partitioned into 192 sub regions of interest,
each of which is 100 by 100 pixels in size (see Figure 17).
In each region of interest, the median value of all pixels is
found. For each region of interest, a pixel is marked
defective if it is greater than or equal to the median value of
that region of interest plus the defect threshold specified in
“Defect Definitions” section.
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18
KAI−2001
Test Sub Regions of Interest
Pixel
(1,1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
Pixel
(1600,1200)
Figure 17. Test Sub Regions of Interest
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19
KAI−2001
OPERATION
Absolute Maximum Ratings
Absolute maximum rating is defined as a level or
condition that should not be exceeded at any time per the
description. If the level or the condition is exceeded,
the device will be degraded and may be damaged.
Table 8. ABSOLUTE MAXIMUM RATINGS
Description
Operating Temperature
Symbol
Minimum
Maximum
Unit
Notes
TOP
−50
70
°C
1
Humidity
RH
5
90
%
2
Output Bias Current
IOUT
0.0
10
mA
3
CL
−
10
pF
4
Off-Chip Load
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for both outputs. Current is 5 mA for each output. Note that the current bias affects the amplifier bandwidth.
4. With total output load capacitance of CL = 10 pF between the outputs and AC ground.
Table 9. MAXIMUM VOLTAGE RATINGS BETWEEN PINS
Description
Minimum
Maximum
Unit
RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, H1BR,
OGL, OGR to ESD
0
17
V
−17
17
V
0
25
V
Pin to Pin with ESD Protection
VDDL, VDDR to GND
Notes
1
1. Pins with ESD protection are: RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGL, and OGR.
Table 10. DC BIAS OPERATING CONDITIONS
Symbol
Min.
Nom.
Max.
Unit
Maximum
DC Current
Output Gate
OG
−3.0
−2.5
−2.0
V
1 mA
Reset Drain
RD
11.5
12.0
12.5
V
1 mA
Output Amplifier Supply
VDD
14.5
15.0
15.5
V
1 mA
Ground
GND
0.0
0.0
0.0
V
Substrate
SUB
8.0
VAB
17.0
V
2, 4
ESD Protection
ESD
−8.0
−7.0
−6.0
V
3
Output Amplifier Return
VSS
0.0
0.7
1.0
V
Description
Notes
1
1. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value VAB is set such that
the photodiode charge capacity is 40,000 electrons.
2. VESD must be at least 1 V more negative than H1L, H2L and RL during sensors operation AND during camera power turn on.
3. One output, unloaded.
4. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
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20
KAI−2001
AC Operating Conditions
Table 11. CLOCK LEVELS
Description
Symbol
Min.
Nom.
Max.
Unit
V2H
7.5
8.0
8.5
V
Vertical CCD Clocks Midlevel
V1M, V2M
−0.2
0.0
0.2
V
Vertical CCD Clocks Low
V1L, V2L
−9.5
−9.0
−8.5
V
Horizontal CCD Clocks Amplitude
H1H, H2H
4.5
5.0
5.5
V
Horizontal CCD Clocks Low
H1L, H2L
−5.0
−4.0
−3.8
V
RH
−
5.0
−
V
1
Vertical CCD Clock High
Reset Clock Amplitude
Reset Clock Low
Notes
RL
−4.0
−3.5
−3.0
V
2
VSHUTTER
44
48
52
V
3
Fast Dump High
FDH
4.8
5.0
5.2
V
Fast Dump Low
FDL
−9.5
−9.0
−8.0
V
Electronic Shutter Voltage
1. Reset amplitude must be set to 7.0 V for 80,000 electrons output in summed interlaced or binning modes.
2. Reset low level must be set to –5.0 V for 80,000 electrons output in summed interlaced or binning modes.
3. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Clock Line Capacitances
V1
H1SL+H1BL
25 nF
66 pF
5 nF
20 pF
V2
H2SL+H2BL
25 nF
H1SR+H1BR
58 pF
66 pF
GND
20 pF
H2SR+H2BR
58 pF
GND
Reset
SUB
FD
10 pF
GND
2 nF
GND
21 pF
GND
Figure 18. Clock Line Capacitances
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21
KAI−2001
TIMING
Table 12. TIMING REQUIREMENTS
Description
Symbol
Min.
Nom.
Max.
Unit
tHD
1.3
1.5
10.0
ms
VCCD Transfer Time
tVCCD
1.3
1.5
20.0
ms
Photodiode Transfer Time
HCCD Delay
tV3rd
8.0
12.0
15.0
ms
VCCD Pedestal Time
t3P
20.0
25.0
50.0
ms
VCCD Delay
t3D
15.0
20.0
100.0
ms
Reset Pulse Time
tR
5.0
10.0
−
ns
Shutter Pulse Time
tS
3.0
5.0
10.0
ms
Shutter Pulse Delay
tSD
1.0
1.6
10.0
ms
HCCD Clock Period
tH
25.0
50.0
200.0
ns
VCCD Rise/Fall Time
tVR
0.0
0.1
1.0
ms
Fast Dump Gate Delay
tFD
0.0
0.0
0.5
ms
Vertical Clock Edge Alignment
tVE
0.0
−
100.0
ns
Timing Modes
Progressive Scan
Photodiode
CCD Shift Register
7
6
5
4
3
2
1
0
Output
HCCD
Figure 19. Progressive Scan Operation
In progressive scan read out every pixel in the image
sensor is read out simultaneously. Each charge packet is
transferred from the photodiode to the neighboring vertical
CCD shift register simultaneously. The maximum useful
signal output is limited by the photodiode charge capacity to
40,000 electrons.
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22
KAI−2001
Vertical Frame
Timing
Line Timing
Repeat for 1214
Lines
Figure 20. Progressive Scan Flow Chart
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23
KAI−2001
Frame Timing
Frame Timing without Binning − Progressive Scan
V1
tL
tV3rd
tL
V2
Line 1213
t3P
Line 1214
t3D
Line 1
H1
H2
Figure 21. Frame Timing without Binning
Frame Timing for Vertical Binning by 2 − Progressive Scan
V1
tL
tV3rd
tL
3 × tVCCD
V2
t3P
Line 606
t3D
Line 1
Line 607
H1
H2
Figure 22. Frame Timing for Vertical Binning by 2
Frame Timing Edge Alignment
V1M
V1
V1L
V2H
V2M
V2
tVE
V2L
Figure 23. Frame Timing Edge Alignment
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24
KAI−2001
Line Timing
Line Timing Single Output − Progressive Scan
tL
V1
tVCCD
V2
tHD
H1
H2
1642
1643
1644
824
825
1630
821
823
1629
820
1627
1628
819
1626
1625
24
23
22
21
19
20
7
6
5
4
3
1
Pixel Count
2
R
Figure 24. Line Timing Single Output
Line Timing Dual Output − Progressive Scan
tL
V1
tVCCD
V2
tHD
H1
H2
Figure 25. Line Timing Dual Output
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25
822
818
817
816
24
23
22
21
19
20
7
6
5
4
3
1
Pixel Count
2
R
KAI−2001
Line Timing Vertical Binning by 2 − Progressive Scan
tL
V1
3 × tVCCD
V2
tHD
H1
H2
Figure 26. Line Timing Vertical Binning by 2
Line Timing Detail − Progressive Scan
V1
tVCCD
V2
1/2 tH
tHD
H1
H2
R
Figure 27. Line Timing Detail
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26
1644
1642
1643
1630
1629
1628
1627
1626
1625
24
23
22
21
19
20
7
6
4
5
3
1
Pixel Count
2
R
KAI−2001
Line Timing Binning by 2 Detail − Progressive Scan
V1
V2
tVCCD
1/2 tH
tVCCD
tVCCD
tHD
H1
H2
R
Figure 28. Line Timing Binning by 2 Detail
Line Timing Edge Alignment
tVCCD
V1
V2
tVE
tVE
NOTE: Applies to all modes.
Figure 29. Line Timing Edge Alignment
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27
KAI−2001
Pixel Timing
V1
V2
H1
H2
Pixel
Count
1
2
3
5
4
19
20
21
R
VOUT
Dummy Pixels
Light Shielded Pixels
Photosensitive Pixels
Figure 30. Pixel Timing
Pixel Timing Detail
tR
RH
R
RL
H1H
H1
H1L
H2H
H2
H2L
VOUT
Figure 31. Pixel Timing Detail
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28
KAI−2001
Fast Line Dump Timing
fFD
fV1
fV2
tFD
tVCCD
tFD
tVCCD
fH1
fH2
Figure 32. Fast Line Dump Timing
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29
KAI−2001
Electronic Shutter
Electronic Shutter Line Timing
fV1
tVCCD
fV2
tHD
VSHUTTER
tS
VSUB
tSD
fH1
fH2
fR
Figure 33. Electronic Shutter Line Timing
Electronic Shutter − Integration Time Definition
fV2
Integration Time
VSHUTTER
VSUB
Figure 34. Integration Time Definition
Electronic Shutter − DC and AC Bias Definition
The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock
are referenced to ground.
VSHUTTER
SUB
GND
GND
Figure 35. DC Bias and AC Clock Applied to the SUB Pin
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30
KAI−2001
Large Signal Output
Electronic Shutter Description
The voltage on the substrate (SUB) determines the charge
capacity of the photodiodes. When SUB is 8 V the
photodiodes will be at their maximum charge capacity.
Increasing VSUB above 8 V decreases the charge capacity
of the photodiodes until 48 V when the photodiodes have
a charge capacity of zero electrons. Therefore, a short pulse
on SUB, with a peak amplitude greater than 48 V, empties
all photodiodes and provides the electronic shuttering
action.
It may appear the optimal substrate voltage setting is 8 V
to obtain the maximum charge capacity and dynamic range.
While setting VSUB to 8 V will provide the maximum
dynamic range, it will also provide the minimum
anti-blooming protection.
The KAI−2001 VCCD has a charge capacity of
55,000 electrons (55 ke−). If the SUB voltage is set such that
the photodiode holds more than 55 ke−, then when the
charge is transferred from a full photodiode to VCCD,
the VCCD will overflow. This overflow condition manifests
itself in the image by making bright spots appear elongated
in the vertical direction. The size increase of a bright spot is
called blooming when the spot doubles in size.
The blooming can be eliminated by increasing the voltage
on SUB to lower the charge capacity of the photodiode. This
ensures the VCCD charge capacity is greater than the
photodiode capacity. There are cases where an extremely
bright spot will still cause blooming in the VCCD. Normally,
when the photodiode is full, any additional electrons
generated by photons will spill out of the photodiode.
The excess electrons are drained harmlessly out to the
substrate. There is a maximum rate at which the electrons
can be drained to the substrate. If that maximum rate is
exceeded, (for example, by a very bright light source) then
it is possible for the total amount of charge in the photodiode
to exceed the VCCD capacity. This results in blooming.
The amount of anti-blooming protection also decreases
when the integration time is decreased. There is
a compromise between photodiode dynamic range
(controlled by VSUB) and the amount of anti-blooming
protection. A low VSUB voltage provides the maximum
dynamic range and minimum (or no) anti-blooming
protection. A high VSUB voltage provides lower dynamic
range and maximum anti-blooming protection. The optimal
setting of VSUB is written on the container in which each
KAI−2001 is shipped. The given VSUB voltage for each
sensor is selected to provide anti-blooming protection for
bright spots at least 100 times saturation, while maintaining
at least 40 ke− of dynamic range.
The electronic shutter provides a method of precisely
controlling the image exposure time without any
mechanical components. If an integration time of tINT is
desired, then the substrate voltage of the sensor is pulsed to
at least 40 V tINT seconds before the photodiode to VCCD
transfer pulse on V2. Use of the electronic shutter does not
have to wait until the previously acquired image has been
completely read out of the VCCD.
When the image sensor is operated in the binned or
summed interlaced modes there will be more than
40,000 electrons in the output signal. The image sensor is
designed with a 16 mV/e charge to voltage conversion on the
output. This means a full signal of 40,000 electrons will
produce a 640 mV change on the output amplifier.
The output amplifier was designed to handle an output
swing of 640 mV at a pixel rate of 40 MHz. If 80,000
electron charge packets are generated in the binned or
summed interlaced modes then the output amplifier output
will have to swing 1,280 mV. The output amplifier does not
have enough bandwidth (slew rate) to handle 1,280 mV at
40 MHz. Hence, the pixel rate will have to be reduced to
20 MHz if the full dynamic range of 80,000 electrons is
desired.
The charge handling capacity of the output amplifier is
also set by the reset clock voltage levels. The reset clock
driver circuit is very simple if an amplitude of 5 V is used.
But the 5 V amplitude restricts the output amplifier charge
capacity to 40,000 electrons. If the full dynamic range of
80,000 electrons is desired then the reset clock amplitude
will have to be increased to 7 V.
If you only want a maximum signal of 40,000 electrons in
binned or summed interlaced modes, then a 40 MHz pixel
rate with a 5 V reset clock may be used. The output of the
amplifier will be unpredictable above 40,000 electrons so be
sure to set the maximum input signal level of your analog to
digital converter to the equivalent of 40,000 electrons
(640 mV).
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31
KAI−2001
STORAGE AND HANDLING
Table 13. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Unit
Notes
Storage Temperature
TST
−55
80
°C
1
Humidity
RH
5
90
%
2
1. Long-term exposure toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade MTTF.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
www.onsemi.com
32
KAI−2001
MECHANICAL DRAWINGS
Completed Assembly
Notes:
1. See Ordering Table for marking code.
2. Cover glass is manually placed and visually aligned
over die − Location accuracy is not guaranteed.
Dimensions Units: IN [MM]
Tolerances: Unless otherwise specified
Ceramic ±1% no less than 0.005″
L/F ±1% no more than 0.005″
Figure 36. Completed Assembly
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33
KAI−2001
Die to Package Alignment
Notes:
1. Center of image is offset from center of package
by (0.00, 0.00) mm nominal.
2. Die is aligned within ±2 degree of any package
cavity edge.
Dimensions Units: IN [MM]
Tolerances: Unless otherwise specified
Ceramic ±1% no less than 0.005″
L/F ±1% no more than 0.005″
Figure 37. Die to Package Alignment
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34
KAI−2001
Glass
Notes:
Double Sided AR Coated Glass
1. Materials: Substrate − Schott D236T eco or equivalent
Epoxy: NCO−150HB
Thickness: 0.002″−0.005″
2. Dust, Scratch Count − 10 microns max.
3. Reflectance:
420−435 nm < 2%
435−630 nm < 0.8%
630−680 nm < 2%
Clear Glass
1.
2.
3.
4.
Materials: Substrate − Schott D236T eco or equivalent
No Epoxy
Dust, Scratch Count − 10 microns max.
Reflectance:
420−435 nm < 10%
435−630 nm < 10%
630−680 nm < 10%
Units: IN [MM]
Tolerance: Unless otherwise specified
±1% no less than 0.005″
Figure 38. Glass Drawing
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35
KAI−2001
Glass Transmission
100
90
Transmission (%)
80
70
60
50
40
30
Clear
20
MAR
10
0
200
300
400
500
600
700
800
900
800
900
Wavelength (nm)
Figure 39. Glass Transmission
100
90
Transmission (%)
80
70
60
50
40
30
20
10
0
200
300
400
500
600
700
Wavelength (nm)
Figure 40. Quartz Glass Transmission
ON Semiconductor and the
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SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
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