KAI-4011
2048 (H) x 2048 (V) Interline
CCD Image Sensor
Description
The KAI−4011 Image Sensor is a high-performance 4-million pixel
sensor designed for a wide range of medical, scientific and machine
vision applications. The 7.4 mm square pixels with microlenses
provide high sensitivity and the large full well capacity results in high
dynamic range. The two high-speed outputs and binning capabilities
allow for 16−50 frames per second (fps) video rate for the
progressively scanned images. The vertical overflow drain structure
provides antiblooming protection and enables electronic shuttering for
precise exposure control. Other features include low dark current,
negligible lag and low smear.
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Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Interline CCD, Progressive Scan
Total Number of Pixels
2112 (H) × 2072 (V)
Number of Effective Pixels
2056 (H) × 2062 (V)
Number of Active Pixels
2048 (H) × 2048 (V)
Features
Pixel Size
7.4 mm (H) × 7.4 mm (V)
Active Image Size
15.15 mm (H) × 15.15 mm (V),
21.43 mm (Diagonal),
Aspect Ratio
1:1
Number of Outputs
1 or 2
Saturation Signal
40,000 e−
Peak Quantum Efficiency
−ABA
−CBA (BGR)
55%
45%, 42%, 35%
•
•
•
•
•
•
•
Total System Noise
40 MHz
20 MHz
40 e−
23 e−
Dark Current
< 0.5 nA/cm2
Dark Current Doubling
Temperature
7°C
Dynamic Range
60 dB
Charge Transfer Efficiency
> 0.99999
Blooming Suppression
300X
Smear
80 dB
Image Lag
< 10 e−
Maximum Data Rate
40 MHz
Package
34-pin, cerDIP
Cover Glass
AR Coated, 2 Sides
Figure 1. KAI−4011 Interline CCD
Image Sensor
High Resolution
High Sensitivity
High Dynamic Range
Low Noise Architecture
High Frame Rate
Binning Capability for Higher Frame Rate
Electronic Shutter
Applications
• Machine Vision
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: All parameters above are specified at T = 40°C.
© Semiconductor Components Industries, LLC, 2014
March, 2017 − Rev. 2
1
Publication Order Number:
KAI−4011/D
KAI−4011
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−4011 IMAGE SENSOR
Part Number
Description
KAI−4011−AAA−CR−BA
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade
KAI−4011−AAA−CR−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample
KAI−4011−ABA−CD−BA
Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−4011−ABA−CD−AE
Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−4011−ABA−CR−BA
Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade
KAI−4011−ABA−CR−AE
Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample
KAI−4011−CBA−CD−BA*
Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−4011−CBA−CD−AE*
Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
Marking Code
KAI−4011
Serial Number
KAI−4011M
Serial Number
KAI−4011CM
Serial Number
*Not recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
Description
KAI−4011−10−40−A−EVK
Evaluation Board, (Complete Kit)
KAI−4021−10−40−A−EVK
Evaluation Board, (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAI−4011
DEVICE DESCRIPTION
Architecture
Single
or
Dual
Output
G R
2048 (H) x 2048 (H)
Active Pixels
28 Dark Columns
B G
G R
4 Buffer Columns
B G
B G
G R
12 Dummy Pixels
Pixel
1,1
12 Dummy Pixels
Video L
B G
G R
8 Buffer Rows
4Buffer Rows
4 Buffer
Columns
28 Dark Columns
B G
G R
B G
G R
B G
G R
B G
G R
6 Buffer Rows
10 Dark Rows
12
28
4
12
28
4
2048
1024
1024
4
28
12
4
28
12
Video R
Figure 2. Sensor Architecture
out Video R. Each row consists of 12 empty pixels followed
by 28 light shielded pixels followed by 1028 photosensitive
pixels. When reconstructing the image, data from Video R
will have to be reversed in a line buffer and appended to the
Video L data.
There are no dark reference rows at the top and 10 dark
rows at the bottom of the image sensor. The 10 dark rows are
not entirely dark and so should not be used for a dark
reference level. Use the 28 dark columns on the left or right
side of the image sensor as a dark reference.
Of the 28 dark columns, the first and last dark columns
should not be used for determining the zero signal level.
Some light does leak into the first and last dark columns.
Only use the center 26 columns of the 28 column dark
reference.
There are 10 light shielded rows followed 2062
photoactive rows. The first 6 and the last 8 photoactive rows
are buffer rows giving a total of 2048 lines of image data.
In the single output mode all pixels are clocked out of the
Video L output in the lower left corner of the sensor. The first
12 empty pixels of each line do not receive charge from the
vertical shift register. The next 28 pixels receive charge from
the left light−shielded edge followed by 2056
photo−sensitive pixels and finally 28 more light shielded
pixels from the right edge of the sensor. The first and last 4
photosensitive pixels are buffer pixels giving a total of 2048
pixels of image data.
In the dual output mode the clocking of the right half of the
horizontal CCD is reversed. The left half of the image is
clocked out Video L and the right half of the image is clocked
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3
KAI−4011
Pixel
ÉÉÉÉÉÉÉÉÉ
ËËËËË
ÉÉÉÉÉÉÉÉÉ
ËËËËË
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ËËËËË
ÉÉÉÉÉÉÉÉÉ
ËËËËË
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
Top View
Direction
of
Charge
Transfer
Cross Section Down Through VCCD
V1
7.4 mm
V1
Photodiode
Transfer
Gate
V2
ÉÉ
ÉÉ
ÉÉ
ÉÉ
n−
V2
V1
n−
ÉÉ
ÉÉ
n−
n
p Well (GND)
Direction of
Charge
Transfer
7.4 mm
n Substrate
True Two Phase Burried Channel VCCD
Lightshield over VCCD not shown
Cross Section Through
Photodiode and VCCD Phase 1
É
É
p
Photodiode
Cross Section Through Photodiode
and VCCD Phase 2 at Transfer Gate
Light Shield
ÉÉÏÏÏÏÏÏÏÉ ÉÉ
ÉÉÏÏÏÏÏÏÏÉ ÉÉ
V1
p+
n
p
n
Gate
Light Shield
ÏÏÏÏÏÏÉÉ
ÏÏÏÏÏÏÉÉ
V2
p+
p
p
p
Transfer
n
n
p
p
p
n Substrate
n Substrate
NOTE: Drawings not scale.
p
Cross Section Showing Lenslet
Lenslet
Red Color Filter
Light Shield
Light Shield
VCCD
VCCD
Photodiode
Figure 3. Pixel Architecture
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron−hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non−linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
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4
KAI−4011
Vertical to Horizontal Transfer
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ËËËËËË
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ËË
ËË
ËË
ËË
ËË ËË
ËË
ËË ËË
ËË
ËË
ËË
ËË ËË
Top View
Direction of
Vertical
Charge
Transfer
V1
Photodiode
Transfer
Gate
V2
V1
Fast
Line
Dump
V2
H2B
H2S
H1B
Lightshield
Not Shown
H1S
Direction of
Horizontal
Charge Transfer
Figure 4. Vertical to Horizontal Transfer Architecture
When the V1 and V2 timing inputs are pulsed, charge in
every pixel of the VCCD is shifted one row towards the
HCCD. The last row next to the HCCD is shifted into the
HCCD. When the VCCD is shifted, the timing signals to the
HCCD must be stopped. H1 must be stopped in the high state
and H2 must be stopped in the low state. The HCCD
clocking may begin THD ms after the falling edge of the V1
and V2 pulse.
Charge is transferred from the last vertical CCD phase into
the H1S horizontal CCD phase. Refer to Figure 36 for an
example of timing that accomplishes the vertical to
horizontal transfer of charge.
If the fast line dump is held at the high level (FDH) during
a vertical to horizontal transfer, then the entire line is
removed and not transferred into the horizontal register.
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KAI−4011
Horizontal Register to Floating Diffusion
RD
R
n+
n
OG
n+
H2S
H2B
H1S
n−
H1B
H2S
n−
H2B
H1S
n−
n (burried channel)
Floating
Diffusion
p (GND)
n (SUB)
Figure 5. Horizontal Register to Floating Diffusion Architecture
When the HCCD is shifting valid image data, the timing
inputs to the electronic shutter (SUB), VCCD (V1, V2), and
fast line dump (FD) should be not be pulsed. This prevents
unwanted noise from being introduced. The HCCD is a type
of charge coupled device known as a pseudo−two phase
CCD. This type of CCD has the ability to shift charge in two
directions. This allows the entire image to be shifted out to
the video L output, or to the video R output (left/right image
reversal). The HCCD is split into two equal halves of 1068
pixels each. When operating the sensor in single output
mode the two halves of the HCCD are shifted in the same
direction. When operating the sensor in dual output mode
the two halves of the HCCD are shifted in opposite
directions. The direction of charge transfer in each half is
controlled by the H1BL, H2BL, H1BR, and H2BR timing
inputs.
The HCCD has a total of 2124 pixels. The 2112 vertical
shift registers (columns) are shifted into the center 2112
pixels of the HCCD. There are 12 pixels at both ends of the
HCCD, which receive no charge from a vertical shift
register. The first 12 clock cycles of the HCCD will be empty
pixels (containing no electrons). The next 28 clock cycles
will contain only electrons generated by dark current in the
VCCD and photodiodes. The next 2056 clock cycles will
contain photo−electrons (image data). Finally, the last 28
clock cycles will contain only electrons generated by dark
current in the VCCD and photodiodes. Of the 28 dark
columns, the first and last dark columns should not be used
for determining the zero signal level. Some light does leak
into the first and last dark columns. Only use the center 26
columns of the 28 column dark reference.
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KAI−4011
Horizontal Register Split
H1
H2
H2
H1
H1
H2
H2
H1BL
H2SL
H2BL
H1SL
H1BL
H2SL
H1BR
Pixel
1068
H1
H1SR
H1
H2
H2BR
H2SR
Pixel
1069
Single Output
H1
H2
H2
H1
H1
H2
H1
H1
H2
H2
H1BL
H2SL
H2BL
H1SL
H1BL
H2SL
H1BR
H1SR
H2BR
H2SR
Pixel
1068
Pixel
1069
Dual Output
Figure 6. Horizontal Register
Dual Output Operation
In dual output mode the connections to the H1BR and
H2BR pins are swapped from the single output mode to
change the direction of charge transfer of the right side
horizontal shift register. In dual output mode both VDDL
and VDDR (pins 11, 24) should be connected to 15 V. The
H1 timing from the timing diagrams should be applied to
H1SL, H1BL, H1SR, H1BR, and the H2 timing should be
applied to H2SL, H2BL, H2SR, and H2BR. The clock driver
generating the H1 timing should be connected to pins 16, 15,
19, and 20. The clock driver generating the H2 timing should
be connected to pins 17, 14, 18, and 21. The horizontal CCD
should be clocked for 12 empty pixels plus 28 light shielded
pixels plus 1028 photoactive pixels for a total of 1068 pixels.
If the camera is to have the option of dual or single output
mode, the clock driver signals sent to H1BR and H2BR may
be swapped by using a relay. Another alternative is to have
two extra clock drivers for H1BR and H2BR and invert the
signals in the timing logic generator. If two extra clock
drivers are used, care must be taken to ensure the rising and
falling edges of the H1BR and H2BR clocks occur at the
same time (within 3 ns) as the other HCCD clocks.
Single Output Operation
When operating the sensor in single output mode all pixels
of the image sensor will be shifted out the Video L output
(pin 12). To conserve power and lower heat generation the
output amplifier for Video R may be turned off by
connecting VDDR (pin 24) and VOUTR (pin 23) to GND
(zero volts).
The H1 timing from the timing diagrams should be
applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing
should be applied to H2SL, H2BL, H2SR, and H1BR. In
other words, the clock driver generating the H1 timing
should be connected to pins 16, 15, 19, and 21. The clock
driver generating the H2 timing should be connected to pins
17, 14, 18, and 20. The horizontal CCD should be clocked
for 12 empty pixels plus 28 light shielded pixels plus 2056
photoactive pixels plus 28 light shielded pixels for a total of
2124 pixels.
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KAI−4011
Output
H2B
H2S
HCCD
Charge
Transfer
H1B
H1S
H2B
H2S
VDD
OG
R
RD
Floating
Diffusion
VOUT
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Figure 7. Output Architecture
are generated in the binned or summed interlaced modes
then the output amplifier output will have to swing
1,280 mV. The output amplifier does not have enough
bandwidth (slew rate) to handle 1,280 mV at 40 MHz.
Hence, the pixel rate will have to be reduced to 20 MHz if
the full dynamic range of 80,000 electrons is desired.
The charge handling capacity of the output amplifier is
also set by the reset clock voltage levels. The reset clock
driver circuit is very simple, if an amplitude of 5 V is used.
But the 5 V amplitude restricts the output amplifier charge
capacity to 40,000 electrons. If the full dynamic range of
80,000 electrons is desired then the reset clock amplitude
will have to be increased to 7 V.
If you only want a maximum signal of 40,000 electrons in
binned or summed interlaced modes, then a 40 MHz pixel
rate with a 5 V reset clock may be used. The output of the
amplifier will be unpredictable above 40,000 electrons so be
sure to set the maximum input signal level of your analog to
digital converter to the equivalent of 40,000 electrons
(640 mV).
Charge packets contained in the horizontal register are
dumped pixel by pixel onto the floating diffusion (FD)
output node whose potential varies linearly with the quantity
of charge in each packet. The amount of potential charge is
determined by the expression DVFD = DQ / CFD.
A three-stage source-follower amplifier is used to buffer
this signal voltage off chip with slightly less than unity gain.
The translation from the charge domain to the voltage
domain is quantified by the output sensitivity or charge to
voltage conversion in terms of microvolts per electron
(mV/e−). After the signal has been sampled off chip, the reset
clock (R) removes the charge from the floating diffusion and
resets its potential to the reset drain voltage (RD).
When the image sensor is operated in the binned or
summed interlaced modes there will be more than 40,000 e−
in the output signal. The image sensor is designed with
a 16 mV/e− charge to voltage conversion on the output. This
means a full signal of 40,000 electrons will produce
a 640 mV change on the output amplifier. The output
amplifier was designed to handle an output swing of 640 mV
at a pixel rate of 40 MHz. If 80,000 electron charge packets
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KAI−4011
ESD Protection
D2
D2
RL
D2
H1SL
D2
H2SL
D2
H1BL
D2
H2BL
OGL
ESD
D1
VSUB
D2
D2
RR
D2
H1SR
D2
H2SR
D2
H1BR
D2
H2BR
OGR
Figure 8. ESD Protection
to forward bias these junctions then diodes D1 and D2
should be added to protect the image sensor. Put one diode
D1 between the ESD and VSUB pins. Put one diode D2 on
each pin that may forward bias the base−emitter junction.
The diodes will prevent large currents from flowing through
the image sensor. Note that external diodes D1 and D2 are
optional and are only needed if it is possible to forward bias
any of the junctions.
Note that diodes D1 and D2 are added external to the
KAI−4011.
The ESD protection on the KAI−4011 is implemented
using bipolar transistors. The substrate (VSUB) forms the
common collector of all the ESD protection transistors. The
ESD pin is the common base of all the ESD protection
transistors. Each protected pin is connected to a separate
emitter as shown in Figure 8.
The ESD circuit turns on if the base−emitter junction
voltage exceeds 17 V. Care must be taken while operating
the image sensor, especially during the power on sequence,
to not forward bias the base−emitter or base−collector
junctions. If it is possible for the camera power up sequence
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KAI−4011
Pin Description and Physical Orientation
SUB
1
34
GND
V2E
2
33
V2E
V2O
3
32
V2O
V1E
4
31
V1E
V1O
5
30
V1O
ESD
6
29
SUB
GND
7
28
FD
OGL
8
27
OGR
GND
9
26
GND
RDL
10
25
RDR
VDDL
11
24
VDDR
VOUTL
12
23
VOUTR
RL
13
22
RR
H2BL
14
21
H2BR
H1BL
15
20
H1BR
H1SL
16
19
H1SR
H2SL
17
18
H2SR
Pixel 1,1
Figure 9. Package Pin Designations − Top View
Table 4. PIN DESCRIPTION
Pin
Name
Substrate
18
H2SR
H2 Storage, Right
Vertical Clock, Phase 2, Even
19
H1SR
H1 Storage, Right
V2O
Vertical Clock, Phase 2, Odd
20
H1BR
H1 Barrier, Right
V1E
Vertical Clock, Phase 1, Even
21
H2BR
H2 Barrier, Right
5
V1O
Vertical Clock, Phase 1, Odd
22
RR
Reset Gate, Right
6
ESD
ESD
23
VOUTR
7
GND
Ground
24
VDDR
8
OGL
Output Gate, Left
25
RDR
Reset Drain, Right
Pin
Name
1
SUB
2
V2E
3
4
Description
Description
Video Output, Right
VDD, Right
9
GND
Ground
26
GND
Ground
10
RDL
Reset Drain, Left
27
OGR
Output Gate, Right
11
VDDL
VDD, Left
28
FD
Video Output, Left
29
SUB
Substrate
V1O
Vertical Clock, Phase 1, Odd
Fast Line Dump Gate
12
VOUTL
13
RL
Reset Gate, Left
30
14
H2BL
H2 Barrier, Left
31
V1E
Vertical Clock, Phase 1, Even
15
H1BL
H1 Barrier, Left
32
V2O
Vertical Clock, Phase 2, Odd
16
H1SL
H1 Storage, Left
33
V2E
Vertical Clock, Phase 2, Even
17
H2SL
H2 Storage, Left
34
GND
Ground
NOTE: The pins are on a 0.070″ spacing.
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10
KAI−4011
IMAGING PERFORMANCE
Table 5. TYPICAL OPERATIONAL CONDITIONS
(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)
Condition
Description
Notes
Frame Time
538 ms
1
Horizontal Clock Frequency
10 MHz
Light Source
Continuous Red, Green and Blue LED Illumination Centered at 450, 530 and 650 nm
Operation
Nominal Operating Voltages and Timing
2, 3
1. Electronic shutter is not used. Integration time equals frame time.
2. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP−8115.
3. For monochrome sensor, only green LED used.
Specifications
Table 6. PERFORMANCE SPECIFICATIONS
Temperature
Tested at
(5C)
Min.
Nom.
Max.
Units
Sampling
Plan
Dark Center Non-Uniformity
N/A
N/A
1
mVrms
Die
27, 40
Dark Global Non-Uniformity
N/A
N/A
5.0
mVpp
Die
27, 40
Global Non-Uniformity (Note 1)
N/A
2.5
5.0
% rms
Die
27, 40
N/A
10
20
% pp
Die
27, 40
N/A
1.0
2.0
% rms
Die
27, 40
Description
Symbol
ALL CONFIGURATIONS
Global Peak to Peak Non-Uniformity
(Note 1)
PRNU
Center Non-Uniformity (Note 1)
Maximum Photoresponse
Non-Linearity (Notes 2, 3)
NL
N/A
2
%
Design
Maximum Gain Difference between
Outputs (Notes 2, 3)
DG
N/A
10
%
Design
Maximum Signal Error due to
Non-Linearity Dif. (Notes 2, 3)
DNL
N/A
1
%
Design
Horizontal CCD Charge Capacity
HNe
100
ke−
Design
Vertical CCD Charge Capacity
VNe
50
60
ke−
Die
Photodiode Charge Capacity
PNe
38
40
ke−
Die
Horizontal CCD Charge Transfer
Efficiency
HCTE
0.99999
N/A
Design
Vertical CCD Charge Transfer
Efficiency
VCTE
0.99999
N/A
Design
Photodiode Dark Current
IPD
N/A
N/A
40
0.01
350
0.1
e/p/s
nA/cm2
Die
Vertical CCD Dark Current
IVD
N/A
N/A
400
0.12
1711
0.5
e/p/s
nA/cm2
Die
Image Lag
Lag
N/A
< 10
50
e−
Design
Anti-Blooming Factor
XAB
100
300
N/A
Vertical Smear
Smr
N/A
−80
−75
dB
Total Noise (Note 4)
ne−T
23
e−
rms
Design
Total Noise (Note 5)
ne−T
40
e− rms
Design
Dynamic Range (Notes 5, 6)
DR
60
dB
Design
V
Die
Output Amplifier DC Offset
VODC
4
8.5
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11
14
KAI−4011
Table 6. PERFORMANCE SPECIFICATIONS (continued)
Description
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
MHz
Design
W
Die
mV/e−
Design
ALL CONFIGURATIONS
Output Amplifier Bandwidth
f−3DB
Output Amplifier Impedance
ROUT
Output Amplifier Sensitivity
140
100
130
200
16
DV/DN
KAI−4011−ABA CONFIGURATION
Peak Quantum Efficiency
Peak Quantum Efficiency Wavelength
QEMAX
45
55
N/A
%
Design
lQE
N/A
500
N/A
nm
Design
−
−
−
35
42
45
N/A
N/A
N/A
%
Design
−
−
−
620
540
470
N/A
N/A
N/A
nm
Design
KAI−4011−CBA CONFIGURATION*
Peak Quantum Efficiency
Red
Green
Blue
Peak Quantum Efficiency Wavelength
Red
Green
Blue
QEMAX
lQE
NOTE: N/A = Not Applicable.
*Not recommended for new designs.
1. Per color.
2. Value is over the range of 10% to 90% of photodiode saturation.
3. Value is for the sensor operated without binning.
4. Includes system electronics noise, dark pattern noise and dark current shot noise at 20 MHz.
5. Includes system electronics noise, dark pattern noise and dark current shot noise at 40 MHz.
6. Uses 20LOG (PNe / ne−T).
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12
Temperature
Tested at
(5C)
KAI−4011
TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome with Microlens
Absolute Quantum Efficiency
0.60
0.50
Measured with glass
0.40
0.30
0.20
0.10
0.00
300
400
500
600
700
800
900
Wavelength (nm)
Figure 10. Monochrome with Microlens Quantum Efficiency
Monochrome without Microlens
0.12
Absolute Quantum Efficiency
0.10
0.08
0.06
0.04
0.02
0.00
240
340
440
540
640
740
840
Wavelength (nm)
Figure 11. Monochrome without Microlens Quantum Efficiency
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13
940
1000
KAI−4011
Color (Bayer RGB) with Microlens*
0.50
0.45
Measured
with Glass
Absolute Quantum Efficiency
0.40
Red
0.35
Green
Blue
0.30
0.25
0.20
0.15
0.10
0.05
0.00
400
500
600
700
800
Wavelength (nm)
Figure 12. Color Quantum Efficiency
*Not recommended for new designs.
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14
900
1000
KAI−4011
Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Monochrome with Microlens
100
Relative Quantum Efficiency (%)
90
Vertical
80
70
60
50
Horizontal
40
30
20
10
0
0
5
10
15
20
25
30
Angle (degress)
Figure 13. Angular Quantum Efficiency
Dark Current vs. Temperature
100,000
10,000
Electrons/Second
VCCD
1,000
100
Photodiodes
10
1
1000/T(K)
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
T (C)
97
84
72
60
50
40
30
21
Figure 14. Dark Current vs. Temperature
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15
KAI−4011
Power-Estimated
Right Output Disabled
400
Output Power One Output (mW)
350
Vertical Power (mW)
Horizonatl Power (mW)
Power (mW)
300
Total Power One Output (mW)
250
200
150
100
50
0
0
5
10
15
20
25
30
Horizontal Clock Frequency (MHz)
Figure 15. Power
Frame Rates
30
25
Dual 2x2 binning
Frame Rate (fps)
20
15
Dual output or
Single 2x2 binning
10
Single output
5
0
10
15
20
25
Pixel Clock (MHz)
Figure 16. Frame Rates
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16
30
35
40
KAI−4011
DEFECT DEFINITIONS
Table 7. DEFECT DEFINITIONS
Definition
Maximum
Temperature(s)
Tested at (5C)
Notes
Major Dark Field Defective Pixel
Defect ≥ 74 mV
40
27, 40
1
Major Bright Field Defective Pixel
Defect ≥ 10%
40
27, 40
1
Minor Dark Field Defective Pixel
Defect ≥ 38 mV
400
27, 40
Defect ≥ 80%
5
27, 40
1
Description
Dead Pixel
Starurated Pixel
Defect ≥ 170 mV
10
27, 40
1
Cluster Defect
A group of 2 to 10 contiguous major
defective pixels, but no more than 2 adjacent
defects horizontally.
8
27, 40
1
Column Defect
A group of more than 10 contiguous major
defective pixels along a single column.
0
27, 40
1
1. There will be at least two non-defective pixels separating any two major defective pixels or clusters.
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
defects are not included in the defect map. All defective
pixels are reference to pixel (1, 1) in the defect maps.
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17
KAI−4011
TEST DEFINITIONS
Test Regions of Interest
Active Area ROI:
Center 100 by 100 ROI:
Overclocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 17 for a pictorial representation of the regions.
Pixel (1, 1) to Pixel (2048, 2048)
Pixel (974, 974) to
Pixel (1073, 1073)
Only the active pixels are used for performance and defect
tests.
H
Horizontal Overclock
Pixel 1,1
V
Vertical Overclock
Figure 17. Overclock Regions of Interest
Tests
Dark Field Center Non-Uniformity
This test is performed under dark field conditions. Only
the center 100 by 100 pixels of the sensor are used for this
test − pixel (974, 974) to pixel (1073, 1073).
Dark Field Center Uniformity + Standard Deviation of Center 100 by 100 Pixels in mW
Units: mV rms
calculated as the maximum signal found minus the
minimum signal level found.
Dark Field Global Non-Uniformity
This test is performed under dark field conditions.
The sensor is partitioned into 256 sub regions of interest,
each of which is 128 by 128 pixels in size. The average signal
level of each of the 256 sub regions of interest is calculated.
The signal level of each of the sub regions of interest is
calculated using the following formula:
Global Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 448 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 640 mV. Global non−uniformity is
defined as:
Signal of ROI[i] + (ROI Average in ADU *
* Horizontal Overclock Average in ADU) @
@ mV per Count
Global Non−Uniformity + 100 @
Units : mVpp (millivolts Peak to Peak)
ǒ
Active Area Standard Deviation
Active Area Signal
Units : % rms
Active Area Signal = Active Area Average −
− Horizontal Overclock Average
Where i = 1 to 256. During this calculation on the 256 sub
regions of interest, the maximum and minimum signal levels
are found. The dark field global non−uniformity is then
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18
Ǔ
KAI−4011
Global Peak to Peak Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 448 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 640 mV. The sensor is partitioned
into 256 sub regions of interest, each of which is 128 by 128
pixels in size. The average signal level of each of the 256 sub
regions of interest (ROI) is calculated. The signal level of
each of the sub regions of interest is calculated using the
following formula:
Bright Field Defect Test
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 28,000 electrons). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 40,000 electrons.
The average signal level of all active pixels is found.
The bright and dark thresholds are set as:
A[i] + (ROI Average * Horizontal Overclock Average)
The sensor is then partitioned into 256 sub regions of
interest, each of which is 128 by 128 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is greater than or equal to the median value of that region of
interest plus the bright threshold specified or if it is less than
or equal to the median value of that region of interest minus
the dark threshold specified.
Example for major bright field defective pixels:
• Average value of all active pixels is found to be
448 mV (28,000 electrons).
• Dark defect threshold: 448 mV ⋅ 15% = 67.2 mV.
• Bright defect threshold: 448 mV ⋅ 15% = 67.2 mV.
• Region of interest #1 selected. This region of interest is
pixels 1, 1 to pixels 128, 128.
♦ Median of this region of interest is found to be
448 mV.
♦ Any pixel in this region of interest that is
≥ (448 + 67.2 mV) 515.2 mV in intensity will be
marked defective.
♦ Any pixel in this region of interest that is
≤ (448 − 67.2 mV) 380.8 mV in intensity will be
marked defective.
• All remaining 255 sub regions of interest are analyzed
for defective pixels in the same manner.
Dark Defect Threshold = Active Area Signal @ Threshold
Bright Defect Threshold = Active Area Signal @ Threshold
Where i = 1 to 256. During this calculation on the 256 sub
regions of interest, the maximum and minimum average
signal levels are found. The global peak to peak
non−uniformity is then calculated as:
Global NonUniformity + 100 @
A[i] Max. Signal * A[i] Min. Signal
Active Area Signal
Units : % pp
Active Area Signal = Active Area Average −
− Horizontal Overclock Average
Center Non-Uniformity
This test is performed with the imager illuminated to
a level such that the output is at 70% of saturation
(approximately 448 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 640 mV. Defects are excluded for
the calculation of this test. This test is performed on the
center 100 by 100 pixels (see Test Regions of Interest) of the
sensor. Center non−uniformity is defined as:
Center ROI Non−Uniformity +
+ 100 @
ǒ
Center ROI Standard Deviation
Center ROI Signal
Ǔ
Units : % rms
Center ROI Signal = Center ROI Average −
− Horizontal Overclock Average
Dark Field Defect Test
This test is performed under dark field conditions.
The sensor is partitioned into 256 sub regions of interest,
each of which is 128 by 128 pixels in size. In each region of
interest, the median value of all pixels is found. For each
region of interest, a pixel is marked defective if it is greater
than or equal to the median value of that region of interest
plus the defect threshold specified in “Defect Definitions”
section.
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19
KAI−4011
OPERATION
Absolute Maximum Ratings
Absolute maximum rating is defined as a level or
condition that should not be exceeded at any time per the
description. If the level or the condition is exceeded,
the device will be degraded and may be damaged.
Table 8. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Units
Notes
Operating Temperature
TOP
−50
70
°C
1
Humidity
RH
5
90
%
2
Output Bias Current
IOUT
0.0
10
mA
3
10
pF
4
Off-Chip Load
CL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Each output. See Figure 18: Output Amplifier. Note that the current bias affects the amplifier bandwidth.
4. With total output load capacitance of CL = 10 pF between the outputs and AC ground.
Table 9. MAXIMUM VOLTAGE RATINGS BETWEEN PINS
Description
Minimum
Maximum
Units
RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGR,
OGL to ESD
0
17
V
−17
17
V
0
25
V
Pin to Pin with ESD Protection
VDDL, VDDR to GND
Notes
1
1. Pins with ESD protection are: RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGL, and OGR.
Table 10. DC BIAS OPERATING CONDITIONS
Symbol
Min.
Nom.
Max.
Units
Maximum
DC Current
Output Gate
OG
−4.0
−3.5
−3.0
V
1 mA
Reset Drain
RD
11.5
12.0
12.5
V
1 mA
Output Amplifier Supply
VDD
14.5
15.0
15.5
V
1 mA
Ground
GND
0.0
0.0
0.0
V
Substrate
SUB
8.0
VAB
17.0
V
1, 5
ESD Protection
ESD
−9.5
−9.0
−8.0
V
2
Output Bias Current
IOUT
0.0
5.0
10.0
mA
4
Description
Notes
3
1. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value VAB is set such that
the photodiode charge capacity is 40,000 electrons.
2. VESD must be equal to FDL and more negative than H1L, H2L and RL during sensors operation AND during camera power turn on.
3. One output, unloaded. The maximum DC current is for one output unloaded and is shown as Iss in Figure 18. This is the maximum current
that the first two stages of one output amplifier will draw. This value is with Vout disconnected.
4. One output.
5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
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20
KAI−4011
VDD
Idd
Floating
Diffusion
Iout
VOUT
Iss
Source
Follower
#1
Source
Follower
#2
Figure 18. Output Amplifier
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21
Source
Follower
#3
KAI−4011
AC Operating Conditions
Table 11. CLOCK LEVELS
Description
Symbol
Min.
Nom.
Max.
Unit
V2H
8.5
9.0
9.5
V
Vertical CCD Clocks Midlevel
V1M, V2M
−0.2
0.0
0.2
V
Vertical CCD Clocks Low
V1L, V2L
−9.5
−9.0
−8.5
V
Horizontal CCD Clocks High
H1H, H2H
0.0
0.5
1.0
V
Horizontal CCD Clocks Low
H1L, H2L
−5.0
−4.5
−4.0
V
Vertical CCD Clock High
Reset Clock Amplitude
RH
V
1
Reset Clock Low
RL
−3.5
−3.0
−2.5
V
2
VSHUTTER
44
48
52
V
3
Fast Dump High
FDH
4
5
5
V
Fast Dump Low
FDL
−9.5
−9
−8
V
Electronic Shutter Voltage
5.0
Notes
1. Reset amplitude must be set to 7.0 V for 80,000 electrons output in summed interlaced or binning modes.
2. Reset low level must be set to –5.0 V for 80,000 electrons output in summed interlaced or binning modes.
3. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Clock Line Capacitances
V1E
H1SL+H1BL
5nF
20nF
50pF
25pF
V1O
H2SL+H2BL
20nF
5nF
20nF
5nF
50pF
V2E
H1SR+H1BR
50pF
25pF
V2O
H2SR+H2BR
5nF
20nF
50pF
GND
GND
Reset
SUB
FD
10pF
GND
4nF
GND
40pF
GND
Figure 19. Clock Line Capacitances
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22
KAI−4011
TIMING
Table 12. TIMING REQUIREMENTS
Description
Symbol
Min.
Nom.
Max.
Units
HCCD Delay
tHD
1.3
1.5
10.0
ms
VCCD Transfer Time
tVCCD
1.3
1.5
20.0
ms
Photodiode Transfer Time
tV3rd
3.0
5.0
15.0
ms
VCCD Pedestal Time
t3P
50.0
60.0
80.0
ms
VCCD Delay
t3D
10.0
20.0
80.0
Reset Pulse Time
tR
2.5
5.0
Shutter Pulse Time
tS
3.0
4.0
10.0
ms
Shutter Pulse Delay
tSD
1.0
1.5
10.0
ms
HCCD Clock Period
tH
25.0
50.0
200.0
ns
VCCD Rise/Fall Time
tVR
0.0
0.1
1.0
ms
Fast Dump Gate Delay
tFD
0.5
Vertical Clock Edge Alignment
tVE
0.0
100.0
ns
ms
ns
ms
Timing Modes
Progressive Scan
Photodiode
CCD Shift Register
7
6
5
4
3
2
1
0
Output
HCCD
Figure 20. Progressive Scan Operation
In progressive scan read out every pixel in the image
sensor is read out simultaneously. Each charge packet is
transferred from the photodiode to the neighboring vertical
CCD shift register simultaneously. The maximum useful
signal output is limited by the photodiode charge capacity to
40,000 electrons.
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23
KAI−4011
Vertical Frame
Timing
Line Timing
Repeat for
2072 Lines
Figure 21. Progressive Scan Flow Chart
Summed Interlaced Scan
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
even field
odd field
Figure 22. Summed Interlaced Scan Operation
(equivalent to binning). To recover the full resolution of the
image sensor two fields, even and odd, are read out. In the
even field rows 0+1, 2+3, 4+5, … are summed together. In
the odd field rows 1+2, 3+4, 5+6, … are summed together.
The modulation transfer function (MTF) of the summed
interlaced scan mode is less in the vertical direction than the
progressive scan. But the dynamic range is twice that of
progressive scan. The vertical MTF is better than a simple
binning operation. In this mode the VCCD needs to be
clocked for only 1037 rows to read out each field.
In the summed interlaced scan read out mode, charge from
two photodiodes is summed together inside the vertical
CCD. The clocking of the VCCD is such that one pixel
occupies the space equivalent to two pixels in the
progressive scan mode. This allows the VCCD to hold twice
as many electrons as in progressive scan mode. Now the
maximum useful signal is limited by the charge capacity of
two photodiodes at 80,000 electrons. If only one field is read
out of the image sensor the apparent vertical resolution will
be 1024 rows instead of the 2048 rows in progressive scan
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24
KAI−4011
Summed
Interlaced Even
Frame
Timing
Summed
Interlaced Odd
Frame
Timing
Interlaced Line
Timing
Interlaced Line
Timing
Repeat for
1037 Lines
Repeat for
1037 Lines
Figure 23. Summed Interlaced Scan Flow Chart
Non−Summed Interlaced Scan
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
even field
odd field
Figure 24. Non−Summed Interlaced Scan Operation
maximum usable signal is still only 40,000 electrons. The
large extra capacity of the VCCD causes the anti−blooming
protection to be increased dramatically compared to the
progressive scan. The vertical MTF is the same between the
non−summed interlaced scan and progressive scan. There
will be motion related artifacts in the images read out in the
interlaced modes because the two fields are acquired at
different times.
In the non−summed interlaced scan mode only half the
photodiode are read out in each field. In the even field rows
0, 2, 4, … are transferred to the VCCD. In the odd field rows
1, 3, 5, … are transferred to the VCCD. When the charge
packet is transferred from a photodiode is occupies the
equivalent of two rows in progressive scan mode. This
allows the VCCD to hold twice as much charge a
progressive scan mode. However, since only one
photodiode for each row is transferred to the VCCD the
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25
KAI−4011
Non−Summed
Interlaced Even
Frame
Timing
Non−Summed
Interlaced Odd
Frame
Timing
Interlaced Line
Timing
Interlaced Line
Timing
Repeat for
1037 Lines
Repeat for
1037 Lines
Figure 25. Non−Summed Interlaced Scan Flow Chart
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26
KAI−4011
Frame Timing
Frame Timing without Binning − Progressive Scan
V1
tL
tV3rd
tL
V2
Line 2071
Line 2072
t3P
t3D
Line 1
H1
H2
Figure 26. Frame Timing without Binning
Frame Timing for Vertical Binning by 2 − Progressive Scan
V1
tL
tV3rd
tL
3 × tVCCD
V2
Line 1035
Line 1036
t3P
t3D
H1
H2
Figure 27. Frame Timing for Vertical Binning by 2
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27
Line 1
KAI−4011
Frame Timing Non−Summed Interlaced Scan (Even)
V1M
V1E
V1L
V2H
V2M
V2E
V2L
V1M
V1O
V1L
V2M
V2O
V2L
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
t V3rd
H2
last odd line
readout
t V3rd
t
V3rd
t VCCD
horizontal retrace
even frame timing
vertical retrace
Figure 28. Non−Summed Interlaced Scan Even Frame Timing
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28
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
first even line
readout
KAI−4011
Frame Timing Non−Summed Interlaced Scan (Odd)
V1M
V1E
V1L
V2M
V2E
V2L
V1M
V1O
V1L
V2H
V2O
V2M
V2L
t V3rd
t V3rd
t V3rd
t
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
VCCD
H2
last even line
readout
horizontal retrace
odd frame timing
vertical retrace
Figure 29. Non−Summed Interlaced Scan Odd Frame Timing
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29
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
first odd line
readout
KAI−4011
Frame Timing Summed Interlaced Scan (Even)
V1M
V1E
V1L
V2H
V2M
V2E
V2L
V1M
V1O
V1L
V2H
V2O
V2M
V2L
t
H2
3P
t
V3rd
t 3D
t VCCD t VCCD t VCCD t VCCD t VCCD t VCCD t VCCD
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
last odd line
readout
ÉÉÉÉ
ÉÉÉÉ
horizontal retrace
even frame timing
vertical retrace
Figure 30. Summed Interlaced Scan Even Frame Timing
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30
first even line
readout
KAI−4011
Frame Timing Summed Interlaced Scan (Odd)
V1M
V1E
V1L
V2H
V2M
V2E
V2L
V1M
V1O
V1L
V2H
V2O
V2M
V2L
t 3P
t V3rd
t 3D
t VCCD t VCCD t VCCD t VCCD t VCCD t VCCD t VCCD
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
H2
last even line
readout
odd frame timing
vertical retrace
horizontal retrace
ÉÉÉÉ
ÉÉÉÉ
first odd line
readout
Figure 31. Summed Interlaced Scan Odd Frame Timing
Frame Timing Edge Alignment
V1M
V1
V1L
V2H
V2M
V2
tVE
V2L
Figure 32. Frame Timing Edge Alignment
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31
KAI−4011
Line Timing
Line Timing Single Output − Progressive Scan
tL
V1
tVCCD
V2
tHD
H1
H2
2122
2123
2124
1067
1068
2098
1063
1065
2097
1062
2095
2096
1061
2094
2093
44
43
42
41
39
40
14
13
11
12
1
Pixel Count
2
R
Figure 33. Line Timing Single Output
Line Timing Dual Output − Progressive Scan
tL
V1
tVCCD
V2
tHD
H1
H2
Figure 34. Line Timing Dual Output
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32
1064
1060
1059
1058
44
43
42
41
40
39
14
13
12
11
1
Pixel Count
2
R
KAI−4011
Line Timing Vertical Binning by 2 − Progressive Scan
tL
V1
3 × tVCCD
V2
tHD
H1
H2
Figure 35. Line Timing Vertical Binning by 2
Line Timing Detail − Progressive Scan
V1
tVCCD
V2
1/2 tH
tHD
H1
H2
R
Figure 36. Line Timing Detail
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33
2124
2123
2122
2098
2097
2096
2095
2094
2093
44
43
42
41
39
40
14
13
11
12
1
Pixel Count
2
R
KAI−4011
Line Timing Binning by 2 Detail − Progressive Scan
V1
V2
1/2 tH
tVCCD
tVCCD
tVCCD
H1
H2
R
Figure 37. Line Timing Binning by 2 Detail
Line Timing Interlaced Modes
V1E
V2E
V1O
V2O
H2
t VCCD
Figure 38. Line Timing Interlaced Modes
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34
tHD
KAI−4011
Line Timing Edge Alignment
tVCCD
V1
V2
tVE
tVE
NOTE: Applies to all modes.
Figure 39. Line Timing Edge Alignment
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35
KAI−4011
Pixel Timing
V1
V2
H1
H2
Pixel
Count
11
1
12
13
39
40
41
R
Vout
Dummy Pixels
Light Shielded Pixels
Photosensitive Pixels
Figure 40. Pixel Timing
Pixel Timing Detail
tR
RH
R
RL
H1H
H1
H1L
H2H
H2
H2L
VOUT
Figure 41. Pixel Timing Detail
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36
KAI−4011
Fast Line Dump Timing
fFD
fV1
fV2
tFD
tVCCD
tFD
tVCCD
fH1
fH2
Figure 42. Fast Line Dump Timing
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37
KAI−4011
Electronic Shutter
Electronic Shutter Line Timing
fV1
tVCCD
fV2
tHD
VSHUTTER
tS
VSUB
tSD
fH1
fH2
fR
Figure 43. Electronic Shutter Line Timing
Electronic Shutter − Integration Time Definition
fV2
Integration Time
VSHUTTER
VSUB
Figure 44. Integration Time Definition
Electronic Shutter − DC and AC Bias Definition
The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock
are referenced to ground.
VSHUTTER
SUB
GND
GND
Figure 45. DC Bias and AC Clock Applied to the SUB Pin
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38
KAI−4011
Large Signal Output
Electronic Shutter Description
The voltage on the substrate (SUB) determines the charge
capacity of the photodiodes. When SUB is 8 V the
photodiodes will be at their maximum charge capacity.
Increasing VSUB above 8 V decreases the charge capacity
of the photodiodes until 48 V when the photodiodes have
a charge capacity of zero electrons. Therefore, a short pulse
on SUB, with a peak amplitude greater than 48 V, empties
all photodiodes and provides the electronic shuttering
action.
It may appear the optimal substrate voltage setting is 8 V
to obtain the maximum charge capacity and dynamic range.
While setting VSUB to 8 V will provide the maximum
dynamic range, it will also provide the minimum
anti-blooming protection.
The KAI−4011 VCCD has a charge capacity of
60,000 electrons (60 ke−). If the SUB voltage is set such that
the photodiode holds more than 60 ke−, then when the
charge is transferred from a full photodiode to VCCD,
the VCCD will overflow. This overflow condition manifests
itself in the image by making bright spots appear elongated
in the vertical direction. The size increase of a bright spot is
called blooming when the spot doubles in size.
The blooming can be eliminated by increasing the voltage
on SUB to lower the charge capacity of the photodiode. This
ensures the VCCD charge capacity is greater than the
photodiode capacity. There are cases where an extremely
bright spot will still cause blooming in the VCCD. Normally,
when the photodiode is full, any additional electrons
generated by photons will spill out of the photodiode.
The excess electrons are drained harmlessly out to the
substrate. There is a maximum rate at which the electrons
can be drained to the substrate. If that maximum rate is
exceeded, (for example, by a very bright light source) then
it is possible for the total amount of charge in the photodiode
to exceed the VCCD capacity. This results in blooming.
The amount of anti-blooming protection also decreases
when the integration time is decreased. There is
a compromise between photodiode dynamic range
(controlled by VSUB) and the amount of anti-blooming
protection. A low VSUB voltage provides the maximum
dynamic range and minimum (or no) anti-blooming
protection. A high VSUB voltage provides lower dynamic
range and maximum anti-blooming protection. The optimal
setting of VSUB is written on the container in which each
KAI−4011 is shipped. The given VSUB voltage for each
sensor is selected to provide anti-blooming protection for
bright spots at least 100 times saturation, while maintaining
at least 40 ke− of dynamic range.
The electronic shutter provides a method of precisely
controlling the image exposure time without any
mechanical components. If an integration time of tINT is
desired, then the substrate voltage of the sensor is pulsed to
at least 40 V tINT seconds before the photodiode to VCCD
transfer pulse on V2. Use of the electronic shutter does not
have to wait until the previously acquired image has been
completely read out of the VCCD.
When the image sensor is operated in the binned or
summed interlaced modes there will be more than
40,000 electrons in the output signal. The image sensor is
designed with a 16 mV/e charge to voltage conversion on the
output. This means a full signal of 40,000 electrons will
produce a 640 mV change on the output amplifier.
The output amplifier was designed to handle an output
swing of 640 mV at a pixel rate of 40 MHz. If 80,000
electron charge packets are generated in the binned or
summed interlaced modes then the output amplifier output
will have to swing 1,280 mV. The output amplifier does not
have enough bandwidth (slew rate) to handle 1,280 mV at
40 MHz. Hence, the pixel rate will have to be reduced to
20 MHz if the full dynamic range of 80,000 electrons is
desired.
The charge handling capacity of the output amplifier is
also set by the reset clock voltage levels. The reset clock
driver circuit is very simple if an amplitude of 5 V is used.
But the 5 V amplitude restricts the output amplifier charge
capacity to 40,000 electrons. If the full dynamic range of
80,000 electrons is desired then the reset clock amplitude
will have to be increased to 7 V.
If you only want a maximum signal of 40,000 electrons in
binned or summed interlaced modes, then a 40 MHz pixel
rate with a 5 V reset clock may be used. The output of the
amplifier will be unpredictable above 40,000 electrons so be
sure to set the maximum input signal level of your analog to
digital converter to the equivalent of 40,000 electrons
(640 mV).
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39
KAI−4011
STORAGE AND HANDLING
Table 13. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Unit
Notes
Storage Temperature
TST
−55
80
°C
1
Humidity
RH
5
90
%
2
1. Long-term exposure toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade MTTF.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
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40
KAI−4011
MECHANICAL DRAWINGS
Completed Assembly
Notes:
1. See Ordering Information for marking code.
2. The cover glass is manually placed and aligned.
Dimensions Units: IN [MM]
Figure 46. Completed Assembly
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41
KAI−4011
Die to Package Alignment
Notes:
1. Center of image is offset from center of package
by coordinates (−0.157, 0.000) mm nominal.
2. Die is aligned within ±1 degree of any package
cavity edge.
Dimensions Units: IN [MM]
Figure 47. Die to Package Alignment
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42
KAI−4011
Glass
Notes:
1. Materials: Substrate − Schott D236T eco or equivalent
2. Epoxy − NCO−150HB
Thickness: 0.002” − 0.005”
3. Dust, Scratch Specification − 10 microns max.
4. Multi−Layer Anti−Reflective Coating on 2 Sides:
a.) Double Sided Reflectance:
b.) Range (nm)
420−435 nm < 2.0%
435−630 nm < 0.8%
630−680 nm < 2.0%
Units: IN [MM]
Tolerance: Unless otherwise specified
±1% no less than 0.004″
Figure 48. Glass Drawing
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43
KAI−4011
Glass Transmission
100
90
80
Transmission (%)
70
60
50
40
30
20
10
0
200
300
400
500
600
700
800
900
Wavelength (nm)
Figure 49. Glass Transmission
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