KAI-43140-FXA-JD-B1

KAI-43140 8040 (X) x 5360 (V) Interline CCD Image Sensor Description The KAI−43140 image sensor is a 43 megapixel Interline Transfer CCD in a 35 mm optical format. Leveraging a 4.5 m pixel design that provides a 50% resolution increase compared to the KAI−29050 and KAI−29052 devices, the KAI−43140 provides excellent image uniformity and broad dynamic range. A flexible output architecture supports 1, 2, or 4 outputs for full resolution readout of up to 4 frames per second, and a true electronic shutter enables image capture without motion artifacts across a broad range of exposure times. In addition to standard monochrome and Bayer Color configurations, the sensor is available in a Sparse CFA configuration which provides a 2x improvement in light sensitivity compared to the standard Bayer Color part. The sensor shares the same package as the KAI−29050 and KAI−29052 image sensors, simplifying camera design. www.onsemi.com Figure 1. KAI−43140 CCD Image Sensor Table 1. GENERAL SPECIFICATIONS Parameter Features Typical Value • High Resolution Image Capture in 35 mm Architecture Interline CCD; Progressive Scan Total Number of Pixels 8160 (H) x 5480 (V) Number of Effective Pixels 8080 (H) x 5400 (V) Number of Active Pixels 8040 (H) x 5360 (V) Pixel Size 4.5 m (H) x 4.5 m (V) Active Image Size 36.18 mm (H) x 24.12 mm (V) 43.48 mm (Diag.), 35 mm Optical Format Aspect Ratio 3:2 Number of Outputs 1, 2, or 4 Charge Capacity 13,000 electrons Output Sensitivity 42 V/e− Quantum Efficiency Pan (−AXA, −QXA) R, G, B (−FXA, −QXA) 45 % 27%, 34%, 37% Read Noise (f = 60 MHz) 13 electrons rms Dark Current Photodiode VCCD 7 electrons/s 50 electrons/s Dynamic Range 60 dB Charge Transfer Efficiency 0.999999 Blooming Suppression > 300 X Smear −98 dB Image Lag < 10 electrons Maximum Pixel Clock Speed 60 MHz Maximum Frame Rates Quad Output Dual Output Single Output 4 fps 2 fps 1 fps Package 72 pin PGA Cover Glass AR Coated, 2 Sides NOTE: • • • • Optical Format True Electronic Shutter with Broad Exposure Latitude Low Noise Architecture Excellent Smear Performance Monochrome, Bayer Color, and Sparse CFA Configurations Applications • Industrial Imaging and Inspection • Security and Surveillance ORDERING INFORMATION See detailed ordering, marking and shipping information on page 2 of this data sheet. All parameters are specified at T = 40°C unless otherwise noted. © Semiconductor Components Industries, LLC, 2015 May, 2018 − Rev. 0 1 Publication Order Number: KAI−43140/D KAI−43140 ORDERING INFORMATION Table 2. ORDERING INFORMATION Part Number Description KAI−43140−AXA−JD−B1 Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 KAI−43140−AXA−JD−B2 Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 KAI−43140−AXA−JD−AE Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade KAI−43140−AXA−JP−B1 Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass (no coatings), Grade 1 KAI−43140−AXA−JP−B2 Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass (no coatings), Grade 2 KAI−43140−AXA−JP−AE Monochrome, Special Microlens, PGA Package, Taped Clear Cover Glass (no coatings), Engineering Grade KAI−43140−FXA−JD−B1 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 KAI−43140−FXA−JD−B2 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 2 KAI−43140−FXA−JD−AE Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade KAI−43140−QXA−JD−B1 Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Grade 1 KAI−43140−QXA−JD−AE Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade Marking Code KAI−43140−AXA Serial Number KAI−43140−AXA Serial Number KAI−43140−FXA Serial Number KAI−43140−QXA Serial Number See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAI−43140 DEVICE DESCRIPTION Architecture H2Bd H2Sd H1Bd H1Sd FDGcd VDDc VOUTc SUB FDGcd H2Bc H2Sc H1Bc H1Sc RDcd Rc RDcd Rd VDDd VOUTd ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ 1 11 40 8 12 4020 4020 12 8 40 11 1 FLD GND OGc H2SLc GND OGd H2SLd 40 8 12 V4T V3T V2T V1BT V4T V3T V2T V1BT DevID 8040H x 5360V 4.5m x 4.5m Pixels 40 8 12 ESD V1BT V2B V3B V4B RDab Ra VDDa VOUTa 12 8 40 V1BT V2B V3B V4B 12 Inner Buffer 8 Outer Buffer ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ 40 Dark FLD 1 11 40 8 12 4020 H2Bb H2Sb H1Bb H1Sb FDGab SUB FDGab H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa 4020 ESD 12 8 40 11 1 RDab Rb VDDb VOUTb GND OGb H2SLb Figure 2. Block Diagram Dark Reference Pixels sensitive than the inner buffer pixels. The inner buffer pixels have the same sensitivity as the 8040 by 5360 active pixels. There are 40 dark reference rows at the top and 40 dark rows at the bottom of the image sensor. The dark rows are not entirely dark and so should not be used for a dark reference level. Use the 40 dark columns on the left or right side of the image sensor as a dark reference. Under normal circumstances use only the center 38 columns of the 40 column dark reference due to potential light leakage. Image Acquisition Within each horizontal shift register there are 12 leading additional shift phases. These pixels are designated as dummy pixels and should not be used to determine a dark reference level. In addition, there is one dummy row of pixels at the top and bottom of the image. An electronic representation of an image is formed when incident photons falling on the sensor plane create electron−hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photo−site. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non−linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. Active Buffer Pixels ESD Protection Dummy Pixels 20 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. These pixels are light sensitive but are not tested for defects and non−uniformities. The 8 outer buffer pixels are less Adherence to the power−up and power−down sequence is critical. Failure to follow the proper power−up and power−down sequences may cause damage to the sensor. See Power−Up and Power−Down Sequence section. www.onsemi.com 3 KAI−43140 Bayer Color Filter H2Bd H2Sd H1Bd H1Sd FDGcd SUB FDGcd H2Bc H2Sc H1Bc H1Sc RDcd Rc RDcd Rd ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ VDDc VOUTc 1 11 40 8 12 4020 4020 VDDd VOUTd 12 8 40 11 1 FLD GND OGc H2SLc GND OGd H2SLd 40 8 12 V4T V3T V2T V1BT B G G R V4T V3T V2T V1BT B G G R DevID ESD 8040H x 5360V 4.5m x 4.5m Pixels 40 8 12 V1BT V2B V3B V4B 12 8 40 B G G R ESD V1BT V2B V3B V4B B G G R 12 Inner Buffer 8 Outer Buffer ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ RDab Ra RDab Rb 40 Dark FLD VDDa VOUTa 1 11 40 8 12 4020 VDDb VOUTb 12 8 40 11 1 GND OGb H2SLb H2Bb H2Sb H1Bb H1Sb FDGab SUB FDGab H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa 4020 Figure 3. Bayer Color Filter Pattern Sparse Color Filter H2Bd H2Sd H1Bd H1Sd FDGcd VDDc VOUTc SUB FDGcd H2Bc H2Sc H1Bc H1Sc RDcd Rc RDcd Rd VDDd VOUTd ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ 1 11 40 8 12 4020 4020 12 8 40 11 1 FLD GND OGc H2SLc GND OGd H2SLd 40 8 12 V4T V3T V2T V1BT G P B P P G P B R P G P P R P G G P B P P G P B R P G P V4T V3T V2T V1BT P R P G DevID ESD V1BT V2B V3B V4B RDab Ra VDDa VOUTa G P B P P G P B R P G P P R P G 12 8 40 G P B P P G P B R P G P P R P G ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ 12 Inner Buffer 8 Outer Buffer 40 Dark FLD 1 11 40 8 12 4020 4020 H2Bb H2Sb H1Bb H1Sb FDGab SUB FDGab H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa 8040H x 5360V 4.5m x 4.5m Pixels 40 8 12 Figure 4. Sparse Color Filter Pattern www.onsemi.com 4 12 8 40 11 1 ESD V1BT V2B V3B V4B RDab Rb VDDb VOUTb GND OGb H2SLb KAI−43140 PHYSICAL DESCRIPTION Pin Description and Device Orientation V3T V1BT VDDd GND Rd H2SLd H1Bd H2Sd SUB N/C H2Sc H1Bc H2SLc Rc GND VDDc V1BT V3T 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 VOUTd RDab VOUTb ESD RDcd OGb DevID OGd H2Bb V4B H2Bd H1Sb V4T H1Sd FDGab V2B FDGcd FDGab V2T FDGcd H1Sa OGa 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 Ra H1Sc OGc RDab 3 GND H2Ba RDcd VOUTa 1 VDDa H2Bc VOUTc V2B 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 V1BT V2T V4B V4T 6 V3B ESD 4 Pixel (1,1) V3B V1BT 5 VDDb www.onsemi.com GND Rb H2SLb H1Bb H2Sb N/C SUB H2Sa H1Ba H2SLa Figure 5. Package Pin Description − Top View KAI−43140 Table 3. PIN DESCRIPTION Pin Name 1 V3B 3 V1BT 4 V4B Vertical CCD Clock, Phase 4, Bottom 5 VDDa Output Amplifier Supply, Quadrant a 6 V2B Vertical CCD Clock, Phase 2, Bottom 7 GND Ground 8 VOUTa 9 Ra 10 RDab Reset Drain, Quadrants a and b 11 H2SLa Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a Description Vertical CCD Clock, Phase 3, Bottom Vertical CCD Clock, Phase 1, Bottom and Top Video Output, Quadrant a Reset Gate, Quadrant a 12 OGa Output Gate, Quadrant a 13 H1Ba Horizontal CCD Clock, Phase 1, Barrier, Quadrant a 14 H2Ba Horizontal CCD Clock, Phase 2, Barrier, Quadrant a 15 H2Sa Horizontal CCD Clock, Phase 2, Storage, Quadrant a 16 H1Sa Horizontal CCD Clock, Phase 1, Storage, Quadrant a 17 SUB Substrate 18 FDGab 19 N/C 20 FDGab 21 H2Sb Horizontal CCD Clock, Phase 2, Storage, Quadrant b 22 H1Sb Horizontal CCD Clock, Phase 1, Storage, Quadrant b 23 H1Bb Horizontal CCD Clock, Phase 1, Barrier, Quadrant b 24 H2Bb Horizontal CCD Clock, Phase 2, Barrier, Quadrant b 25 H2SLb Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant b 26 OGb Output Gate, Quadrant b 27 Rb Reset Gate, Quadrant b 28 RDab Reset Drain, Quadrants a and b 29 GND Ground 30 VOUTb 31 VDDb Output Amplifier Supply, Quadrant b 32 V2B Vertical CCD Clock, Phase 2, Bottom 33 V1BT 34 V4B Vertical CCD Clock, Phase 4, Bottom 35 V3B Vertical CCD Clock, Phase 3, Bottom 36 ESD ESD Protection Disable 37 V3T Vertical CCD Clock, Phase 3, Top 38 DevID Device Identification 39 V1BT Vertical CCD Clock, Phase 1, Bottom and Top 40 V4T 41 VDDd 42 V2T Fast Line Dump Gate, Bottom No Connect Fast Line Dump Gate, Bottom Video Output, Quadrant b Vertical CCD Clock, Phase 1, Bottom and Top Vertical CCD Clock, Phase 4, Top Output Amplifier Supply, Quadrant d Vertical CCD Clock, Phase 2, Top www.onsemi.com 6 KAI−43140 Table 3. PIN DESCRIPTION (continued) Pin Name Description 43 GND 44 VOUTd 45 Rd 46 RDcd Reset Drain, Quadrants c and d 47 H2SLd Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d Ground Video Output, Quadrant d Reset Gate, Quadrant d 48 OGd Output Gate, Quadrant b 49 H1Bd Horizontal CCD Clock, Phase 1, Barrier, Quadrant d 50 H2Bd Horizontal CCD Clock, Phase 2, Barrier, Quadrant d 51 H2Sd Horizontal CCD Clock, Phase 2, Storage, Quadrant d 52 H1Sd Horizontal CCD Clock, Phase 1, Storage, Quadrant d 53 SUB Substrate 54 FDGcd 55 N/C 56 FDGcd 57 H2Sc Horizontal CCD Clock, Phase 2, Storage, Quadrant c 58 H1Sc Horizontal CCD Clock, Phase 1, Storage, Quadrant c 59 H1Bc Horizontal CCD Clock, Phase 1, Barrier, Quadrant c 60 H2Bc Horizontal CCD Clock, Phase 2, Barrier, Quadrant c 61 H2SLc Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c 62 OGc Output Gate, Quadrant c 63 Rc Reset Gate, Quadrant c 64 RDcd Reset Drain, Quadrants c and d 65 GND Ground 66 VOUTc Video Output, Quadrant c 67 VDDc Output Amplifier Supply, Quadrant c 68 V2T 69 V1BT 70 V4T Vertical CCD Clock, Phase 4, Top 71 V3T Vertical CCD Clock, Phase 3, Top 72 ESD ESD Protection Disable Fast Line Dump Gate, Top No Connect Fast Line Dump Gate, Top Vertical CCD Clock, Phase 2, Top Vertical CCD Clock, Phase 1, Bottom and Top 1. Like named pins are internally connected and should have a common drive signal. 2. N/C pins (19, 55) should be left floating www.onsemi.com 7 KAI−43140 IMAGING PERFORMANCE Table 4. TYPICAL OPERATION CONDITIONS (Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Condition Description Light Source Operation Notes Continuous Red, Green and Blue LED Illumination For monochrome sensor, only green LED used Nominal operating voltages and timing Table 5. PERFORMANCE PARAMETERS (Performance parameters are by design.) Description Maximum Photo−response Nonlinearity Symbol Nom. Units Notes NL 2 % 4 Maximum Signal Error due to Nonlinearity Differences NL 1 % 4 Horizontal CCD Charge Capacity HNe 40 ke− Vertical CCD Charge Capacity VNe 24 ke− Photodiode Charge Capacity PNe 13 ke− Image Lag Lag < 10 e− Anti−blooming Factor Xab > 300X Vertical Smear Smr −98 dB 9 Read Noise ne−T 13 e−rms 6 DR 60 dB 6, 7 Output Amplifier DC Offset Vodc 8 V Output Amplifier Bandwidth f−3db 250 MHz Output Amplifier Impedance Rout 127  Output Amplifier Sensitivity V/N 42 V/e− Peak Quantum Efficiency (KAI−43140−AXA and KAI−43410−QXA Configurations) QEmax 45 % QEmax 37 34 27 % Dynamic Range Peak Quantum Efficiency (KAI−43140−FXA and KAI−43140−QXA Configurations) Blue Green Red 5 8 Table 6. PERFORMANCE SPECIFICATIONS Symbol Min. Nom. Max. Units Temperature Tested At (5C) Dark Field Global Non−Uniformity DSNU − − 5 mVpp 27, 40 Bright Field Global Non−Uniformity BSNU − − 5 %rms 27, 40 3 Bright Field Global Peak to Peak Non−Uniformity PRNU − − 30 %pp 27, 40 3 % 27, 40 4 Description Maximum Gain Difference Between Outputs G − − 10 Horizontal CCD Charge Transfer Efficiency HCTE 0.999995 0.999999 − Vertical CCD Charge Transfer Efficiency VCTE 0.999995 0.999999 − Photodiode Dark Current Ipd − 7 50 e/p/s 40 Vertical CCD Dark Current Ivd − 50 200 e/p/s 40 Notes 3. Per color 4. Value is over the range of 10% to 90% of photodiode saturation. 5. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is 546 mV. 6. At 60 MHz 7. Uses 20 * LOG (Pne/ne−T) 8. Assumed 5 pF load. 9. Green LED illumination www.onsemi.com 8 KAI−43140 TYPICAL PERFORMANCE CURVES Quantum Efficiency 0.50 Measured with AR coated cover glass 0.45 0.40 Absolute Quantum Efficiency 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 Wavelength (nm) Figure 6. Monochrome with Microlens Quantum Efficiency 0.50 Measured with AR coated cover glass 0.45 0.40 Absolute Quantun Efficiency 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 Wavelength (nm) Red Green Blue Figure 7. Gen2 Color (Bayer RGB) with Microlens Quantum Efficiency www.onsemi.com 9 1050 1100 KAI−43140 Figure 8. Color (Sparse CFA) with Microlens Quantum Efficiency Angular Quantum Efficiency For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD. For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD. 100 90 Relative Quantum Efficiency (%) 80 70 60 50 40 30 20 10 0 -25 -20 -15 -10 -5 0 5 10 15 20 Angle (degrees) Horizontal QE: KAI-43140-AXA Vertical QE: KAI-43140-AXA Figure 9. Monochrome with Microlens Angular Quantum Efficiency www.onsemi.com 10 25 KAI−43140 Dark Current versus Temperature 10000 Dark Current (e/s/pixel) 1000 100 10 1 0.1 1000/T (K) 2.9 3.0 3.1 3.2 3.3 3.4 T (°C) 60 50 40 30 21 72 Photodiode VCCD Figure 10. Dark Current versus Temperature Power 1.4 1.2 Power (W) 1.0 0.8 0.6 0.4 0.2 0.0 10 15 20 25 30 35 40 45 50 HCCD Frequency (MHz) Single Dual (Left/Right) Figure 11. Power www.onsemi.com 11 Quad 55 60 KAI−43140 Frame Rates 5.0 4.5 4.0 Frame Rate (fps) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 10 15 20 25 30 35 40 45 50 55 60 HCCD Frequency (MHz) Single Dual (Left/Right) Quad Figure 12. Frame Rates DEFECT DEFINITIONS Table 7. OPERATING CONDITIONS Description Condition Notes Light Source Continuous Red, Green, and/or Blue LED Illumination Operation Nominal Operating Voltages and Timing For the monochrome sensor, only the green LED is used Table 8. OPERATING PARAMETERS Description 1 Output 4 Outputs 20 MHz 20 MHz Pixels per Line 8160 4080 Lines per Frame 5480 5480 HCCD Clock Frequency Line Time Frame Time 429.6 s 225.6 s 2354.3 ms 618.2 ms Table 9. TIMING MODES Timing Mode Conditions Mode A 1 Output, no electronic shutter used. Photodiode integration time is equal to the Frame Time Mode B 4 Outputs, no electronic shutter used. Photodiode integration time is equal to the Frame time www.onsemi.com 12 KAI−43140 Table 10. DEFECT DEFINITIONS Description Definition Grade 1 Grade 2 (mono) Grade 2 (color) Column Defect A group of more than 10 contiguous pixels along a single column that deviate from the neighboring columns by: • more than 94 mV in the dark field using Timing Mode A at 40°C • more than 94 mV in the dark field using Timing Mode A at 27°C • more than −2% or +50% in the bright field using timing mode A at 27°C or 40°C 0 7 27 Cluster Defect A group of 2 to N contiguous defective pixels, but no more than W adjacent defects horizontally, that deviate from the neighboring pixels by: • more than 440 mV in the dark field using Timing Mode A at 40°C • more than 236 mV in the dark field using Timing Mode A at 27°C • more than −12% or +12% in the bright field using timing mode A at 27°C or 40°C 30 W=4 N=19 70 W=5 N=38 70 W=5 N=38 Major Point Defect A single defective pixel that deviates from the neighboring pixels by: • more than 440 mV in the dark field using Timing Mode A at 40°C • more than 236 mV in the dark field using Timing Mode A at 27°C • more than −12% or +50% in the bright field using timing mode A at 27°C or 40°C 400 800 800 Minor Point Defect A single defective pixel that deviates from the neighboring pixels by: • more than 220 mV in the dark field using Timing Mode A at 40°C 4000 8000 8000 10. Bright field is define as where the average signal level of the sensor is 382 mV, with the substrate voltage set to the recommend VAB setting such that the capacity of the photodiodes is 546 mV (13,000 electrons) 11. For the color devices (KAI−43140−FXA or KAI−43140−QXA), a bright field defective pixel is with respect to pixels of the same color 12. Column and cluster defects are separated by no less than two (2) non−defective pixels in any direction (excluding single pixel defects). DEFECT MAP The defect map supplied with each sensor is based upon testing at an ambient (27°C) temperature. Minor point defects are not included in the defect map. All defective pixels are reference to pixel 1, 1 in the defect maps. VOUTa VOUTb 40 dark rows 20 buffer rows 1, 1 40 dark columns 8040 x 5360 Active Pixels 20 buffer columns 20 buffer columns 21, 21 Pixel 40 dark columns Pixel 20 buffer rows 40 dark rows VOUTc VOUTd Figure 13. Pixel 1, 1 Location www.onsemi.com 13 KAI−43140 OPERATION Table 11. ABSOLUTE MAXIMUM RATINGS Symbol Minimum Maximum Units Notes Operating Temperature Description Top −50 +70 °C 13, 15 Humidity RH 5 90 % 14, 15 Output Bias Current Iout − 60 mA 16 Off−Chip Load CL − 10 pF Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 13. Noise performance will degrade at higher temperatures. 14. T = 25 °C. Excessive humidity will degrade MTTF. 15. The KAI−43140 image sensors have epoxy sealed cover glass. The seal formed is non−hermetic, and may allow moisture ingress over time, depending on the storage environment. As a result, care must be taken to avoid cooling the device below the dew point inside the package cavity, since this may result in condensation on the sensor. For all KAI−43140 configurations, no warranty, expressed or implied, covers condensation. 16. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Table 12. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND Description VDD, VOUT Minimum Maximum Units Notes −0.4 +17.5 V 17 17 RD −0.4 +15.5 V V1TB ESD − 0.4 ESD + 24.0 V V2B, V2T, V3B, V3T, V3B, V3T ESD − 0.4 ESD + 14.0 V FDGab, FDGcd ESD − 0.4 ESD + 15.0 V H1, H2, H2L ESD − 0.4 ESD + 14.0 V 17 R ESD − 0.4 ESD + 18.0 V 17 ESD −10 0.0 V SUB −0.4 40.0 V 17.  refers to a, b, c, or d. 18. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions www.onsemi.com 14 18 KAI−43140 Power−Up and Power−Down Sequence Adherence to the power−up and power−down sequence is critical. Failure to follow the proper power−up and power−down sequences may cause damage to the sensor. Do not pulse the electronic shutter until ESD is stable V+ VDD SUB ESD V− VCCD and FDG Low HCCD Low Activate all other biases when ESD is stable and sub is above3V NOTES: 19. Activate all other biases when ESD is stable and SUB is above 3 V. 20. Do not pulse the electronic shutter until ESD is stable. 21. The VCCD clock waveform must not have a negative overshoot more than 0.4 V below the ESD voltage. See Figure 15. 22. The image sensor can be protected from an accidental improper ESD voltage by current limiting the SUB current to less than 10 mA. SUB and VDD must always be greater than GND. ESD must always be less than GND. Placing diodes between SUB, VDD, ESD and ground will protect the sensor from accidental overshoots of SUB, VDD and ESD during power on and power off. See Figure 16. Figure 14. Power−Up and Power−Down Sequence 0.0V ESD ESD −0.4V All VCCD and FDG Clocks absolute maximum overshoot of0.4 V Figure 15. VCCD Clock Overshoots SUB VDD GND ESD Figure 16. External Diode Protection www.onsemi.com 15 KAI−43140 Table 13. DC BIAS OPERATING CONDITIONS Pins Symbol Minimum Nominal Maximum Units Max. DC Current Notes Reset Drain RD RD +12.3 +12.5 +12.7 V 10 A 23 Output Gate OG OG +1.5 +1.7 +2.4 V 10 A 23 Output Amplifier Supply VDD VDD +14.5 +15.0 +15.5 V 11.0 mA 23, 24 Ground GND GND +0.0 +0.0 +0.0 V –1.0 mA Substrate SUB VSUB +5.0 VAB VDD V 50 A 25, 30 ESD Protection Disable ESD ESD –9.2 –9.0 –8.8 V 50 A 28, 29 VOUT Iout –3.0 –5.0 –10.0 mA Description Output Bias Current 23, 26, 27 VDDa RDa Ra 23.  denotes a, b, c or d 24. The maximum DC current is for one output. Idd = Iout + Iss. See Figure 17. 25. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is the nominal PNe (see Specifications). 26. An output load sink must be applied to each VOUT pin to activate each output amplifier. 27. Nominal value required for 60 MHz operation per output. May be reduced for slower data rates and lower noise. 28. Adherence to the power−up and power−down sequence is critical. See Power−Up and Power−Down Sequence section. 29. ESD maximum value must be less than or equal to V1_L − 0.4 V and V2_L − 0.4 V. 30. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. Idd HCCD Floating Diffusion Iout OGa VOUTa Iss Source Follower #1 Source Follower #2 Figure 17. Output Amplifier www.onsemi.com 16 Source Follower #3 KAI−43140 AC OPERATING CONDITIONS Table 14. CLOCK LEVELS Description Pins (Note 31) Symbol Level Min Nom Max Units Capacitance (Note 32) Vertical CCD Clock, Phase 1 V1B, V1T V1_L Low –8.2 –8.0 –7.8 V 420 nF V1_M Mid –0.2 +0.0 +0.2 V1_H High +10.3 +10.5 +10.7 V2_L Low –8.2 –8.0 –7.8 V 240 nF V2_H High –0.2 +0.0 +0.2 V3_L Low –8.2 –8.0 –7.8 V 260 nF V3_H High –0.2 +0.0 +0.2 V4_L Low –8.2 –8.0 –7.8 V 240 nF V4_H High –0.2 +0.0 +0.2 H1S_L Low −0.2 +0.0 +0.2 V 650 pF H1S_H High +3.8 +4.0 +5.2 H1B_L Low –0.2 +0.0 +0.2 V 680 pF H1B_H High +3.8 +4.0 +5.2 H2S_L Low –0.2 +0.0 +0.2 V 560 pF H2S_H High +3.8 +4.0 +5.2 V 460 pF V 20 pF V 20 pF V 12 nF V 200 pF Vertical CCD Clock, Phase 2 Vertical CCD Clock, Phase 3 Vertical CCD Clock, Phase 4 V2B, V2T V3B, V3T V4B, V4T Horizontal CCD Clock, Phase 1 Storage H1S Horizontal CCD Clock, Phase 1 Barrier H1B Horizontal CCD Clock, Phase 2 Storage H2S Horizontal CCD Clock, Phase 2 Barrier H2B Horizontal CCD Clock, Last Phase (Note 33) H2SL Reset Gate Electronic Shutter (Notes 35, 38) Fast Line Dump Gate R SUB FDGab, FDGcd H2B_L Low –0.2 +0.0 +0.2 H2B_H High +3.8 +4.0 +5.2 H2SL_L Low –0.2 +0.0 +0.2 H2SL_H High +3.8 +4.0 +5.2 R_L (Note 34) Low +2.0 +3.0 +3.2 R_H High +6.8 +7.0 +7.2 VES High – – +40 VES_Offet Offset VAB + 24 VAB + 25 – FDG_L Low –8.2 –8.0 –7.8 FDG_H High +4.5 +5.0 +5.5 31.  denotes a, b, c or d. 32. Capacitance is total for all like named pins. 33. Use separate clock driver for improved speed performance. 34. Reset low should be set to +2.0 V for signal levels greater than 26,000 electrons. 35. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. 36. Capacitance values are estimated. 37. If the minimum horizontal clock low level is used (−0.2 V), then a 4 V clock amplitude should be used to create a −0.2 V to +3.8 V clock. For the maximum horizontal charge transfer efficiency performance a 5 volt clock amplitude may be used. 38. Figure 18 shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. The VES_Offset is referenced to VSUB. Figure 18. VSUB and VES Reference www.onsemi.com 17 KAI−43140 Device Identification The device identification pin (DevID) may be used to determine which ON Semiconductor 5.5 micron pixel interline CCD sensor is being used. Table 15. DEVICE IDENTIFICATION Description Pins Symbol Minimum Nominal Maximum Unit Max. DC Current Notes Device Identification DevID DevID 230,000 260,000 300,00  50 A 39, 40, 41 39. Nominal value subject to verification and/or change during release of preliminary specifications. 40. If the Device Identification is not used, it may be left disconnected. 41. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent localized heating of the sensor due to current flow through the R_DeviceID resistor. Recommended Circuit Note that V1 must be a different value than V2. Figure 19. Device Identification Recommended Circuit www.onsemi.com 18 KAI−43140 TIMING Table 16. REQUIREMENTS AND CHARACTERISTICS Symbol Minimum Nominal Maximum Units Photodiode Transfer Description TPD 6 – – s VCCD Leading Pedestal T3P 16 – – s VCCD Trailing Pedestal T3D 16 – – s VCCD Transfer Delay TD 4 − − s VCCD Transfer TV 10 – – s VCCD Clock Cross−over Notes VVCR 75 – 100 % 42 TVR, TVF 5 – 10 % 42, 43 FDG Delay TFDG 5 – – s HCCD Delay THS 1 – – s HCCD Transfer TE 16.6667 – – ns Shutter Transfer TSUB 1 – – s Shutter Delay THD 1 – – s Reset Pulse TR 2.5 – – ns Reset – Video Delay TRV – 2.2 – ns H2SL – Video Delay THV – 3.1 – ns TLINE 89.21 – – s 157.21 – – 244.43 – – 488.86 – – Dual HCCD Readout 861.50 – – Single HCCD Readout VCCD Rise, Fall Time Line Time Frame Time TFRAME 42. Refer to Figure 24: VCCD Clock Rise Time, Fall Time and Edge Alignment 43. Relative to the pulse width www.onsemi.com 19 Dual/Quad HCCD Readout Single HCCD Readout ms Quad HCCD Readout KAI−43140 Timing Diagrams table below. The patterns are defined in Figure 20 and Figure 21. Contact ON Semiconductor Application Engineering for other readout modes. The timing sequence for the clocked device pins may be represented as one of seven patterns (P1−P7) as shown in the Table 17. TIMING SEQUENCE Device Pin Quad Readout Dual Readout VOUTa, VOUTb Dual Readout VOUTa, VOUTc Single Readout VOUTa V1BT P1BT P1BT P1BT P1BT V2T P2T P4B P2T P4B V3T P3T P3B P3T P3B V4T P4T P2B P4T P2B V1BT P1BT V2B P2B V3B P3B V4B P4B H1Sa P5 H1Ba P6 H2Sa (Note 45) H2Ba Ra P7 P5 H1Sb P5 H1Bb P6 P6 H2Sb (Note 45) P6 H2Bb P5 P7 44 or Off 46 P7 44 or Off 46 P5 P5 46 P5 P5 44 or Off 46 P6 P6 44 or Off 46 P6 P6 44 or Off 46 Rc P7 P7 44 or Off 46 P7 P7 44 or Off 46 H1Sd P5 P5 44 or Off 46 P5 P5 44 or Off 46 Rb H1Sc P7 44 or Off H1Bc H2Sc (Note 45) H2Bc H1Bd H2Sd (Note 45) P6 P6 P6 44 P7 44 or Off 46 or Off 46 H2Bd P5 Rd P7 # Lines/Frame (Minimum) 2740 # Pixels/Line (Minimum) P6 44 or Off 46 P6 5480 4092 P7 44 or Off 46 P7 44 or Off 46 2740 5480 8172 44. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should be a multiple of the frequency used on the a and b register. 45. H2SLx follows the same pattern as H2Sx For optimal speed performance, use a separate clock driver. 46. Off = R_H for the Reset Gate and H_H for the Horizontal CCD gates. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the unused c/d register into the image area. www.onsemi.com 20 KAI−43140 Photodiode Transfer Timing A row of charge is transferred to the HCCD on the falling edge of V1 as indicated in the P1 pattern below. Using this timing sequence, the leading dummy row or line is combined with the first dark row in the HCCD. The “Last Line” is dependent on readout mode – either 2740 or 5480 minimum counts required. It is important to note that, in Pattern td P1BT t3p tpd t3d tv/2 general, the rising edge of a vertical clock (patterns P1−P4) should be coincident or slightly leading a falling edge at the same time interval. This is particularly true at the point where P1 returns from the high (3rd level) state to the mid−state when P4 transitions from the low state to the high state. td tv tv tv/2 tv/2 P2T tv/2 tv/2 P3T P4T tv P1BT tv/2 tv tv/2 P2B P3B P4B 2tv + ths P5 2tv + ths ths Last Line ths L1 +Dummy Line L2 P6 P7 Figure 20. Photodiode Transfer Timing Line and Pixel Timing P6 pattern). The number of pixels in a row is dependent on readout mode – either 4092 or 8172 minimum counts required. Each row of charge is transferred to the output, as illustrated below, on the falling edge of H2SL (indicated as Pattern tline P1BT P2T P3T P4T P1BT P2B tv P3B 2tv + ths tv P4B P6 te/2 ths te/2 P5 te tr P7 VOUT Pixel 1 Pixel 53 Pixel n Figure 21. Line and Pixel Timing www.onsemi.com 21 ths KAI−43140 Pixel Timing Detail P5 P6 P7 VOUT trv t hv Figure 22. Pixel Timing Detail Frame/Electronic Shutter Timing The SUB pin may be optionally clocked to provide electronic shuttering capability as shown below. The resulting photodiode integration time is defined from the falling edge of SUB to the falling edge of V1 (P1 pattern). tframe Pattern P1T/B SUB P6 thd tint tsub thd Figure 23. Electronic Shutter Timing VCCD Clock Edge Alignment VVCR 90% tV 10% tVF tVR tV tVF tVR Figure 24. VCCD Clock Rise Time, Fall Time, and Edge Alignment www.onsemi.com 22 KAI−43140 Line and Pixel Timing − Vertical Binning by 2 tv tv tv P1BT P2T P3T P4T P1BT P2B P3B P4B te/2 ths P5 P6 P7 Figure 25. Line and Pixel Timing − Vertical Binning by 2 Fast Line Dump Timing The FDG pins may be optionally clocked to efficiently remove unwanted lines in the image resulting for increased tv tv tv frame rates at the expense of resolution. Below is an example of a 2 line dump sequence followed by a normal readout line. tv tv P1BT P2T P3T P4T TFDG FDGcd TFDG P1BT P2B P3B P4B FDGab te/2 ths P5 P6 P7 Figure 26. Fast Line Dump Timing www.onsemi.com 23 KAI−43140 STORAGE AND HANDLING Table 18. STORAGE CONDITIONS Description Symbol Minimum Maximum Units Notes Storage Temperature TAT −55 +88 °C 47 Humidity RH 5 90 % 48 47. Long term storage toward the maximum temperature will accelerate color filter degradation. 48. T = 25 °C. Excessive humidity will degrade MTTF. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. www.onsemi.com 24 KAI−43140 MECHANICAL INFORMATION NOTES: 49. Substrate = Schott D263T eco 50. Dust, Scratch, Inclusion Specification: 20 m Max size in Zone A 51. MAR coated both sides 52. Spectral Transmission 350−365 nm: T ≥ 88% 365−405 nm: T ≥ 94% 405−450 nm: T ≥ 98% 450−650 nm: T ≥ 99% 650−690 nm: T ≥ 98% 690−770 nm: T ≥ 94% 770−870 nm: T ≥ 88% 53. Units: IN [MM] Figure 27. Cover Glass www.onsemi.com 25 KAI−43140 100 90 80 Transmission (%) 70 60 50 40 30 20 10 0 200 300 400 500 600 700 Wavelength (nm) MAR Clear Figure 28. Cover Glass Transmission www.onsemi.com 26 800 900 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS CPGA72, 47.24x45.34 CASE 107ES ISSUE O DATE 30 JUL 2014 (C0.01) ([0.25]) 4X 0.055 [1.40] (70X) 0.100+0.005 −0.007 2.54 +0.13 −0.18 [ ] 2X HOLE Dimensions in: Inches [mm] DOCUMENT NUMBER: STATUS: 98AON88267F ON SEMICONDUCTOR STANDARD REFERENCE: © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 CPGA72, 47.24x45.34 http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 1 OFXXX 3 CPGA72, 47.24x45.34 CASE 107ES ISSUE O DATE 30 JUL 2014 Dimensions in: Inches [mm] DOCUMENT NUMBER: STATUS: 98AON88267F ON SEMICONDUCTOR STANDARD REFERENCE: © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 CPGA72, 47.24x45.34 http://onsemi.com 2 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 2 OFXXX 3 DOCUMENT NUMBER: 98AON88267F PAGE 3 OF 3 ISSUE O REVISION RELEASED FOR PRODUCTION FROM TRUESENSE MATERIAL NUMBER 20351897 TO ON SEMICONDUCTOR. REQ. BY D. TRUHITTE. DATE 30 JUL 2014 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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