ON Semiconductor
Is Now
To learn more about onsemi™, please visit our website at
www.onsemi.com
onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
KLI-4104
Linear CCD Image Sensor
Description
The KLI−4104 Image Sensor is a multi-spectral, linear solid-state
image sensor for color scanning applications where fast operation and
high resolution are required. The imager consists of three parallel
linear photodiode arrays, each with 4,080 active photosites for the
output of red, green and blue (R, G, and B) signals. The sensor
contains a fourth channel for luminance information. This array has
8,160 pixels segmented to transfer out data through one of four
luminance outputs. This device offers high sensitivity, high data rates,
low noise and negligible lag. Individual electronic exposure control
for each of the Chroma and the Luma channel is provided, allowing
the KLI−4104 sensor to be used under a variety of illumination
conditions.
www.onsemi.com
Figure 1. KLI−4104 Linear CCD
Image Sensor
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Total Number of Pixels
3 × 4134 (Chroma),
1 × 8292 (Luma)
Number of Effective Pixels
3 × 4128 (Chroma),
1 × 8276 (Luma)
• Quad-Linear Array (G, R, B, L)
• High Resolution: Luma (Monochrome)
Number of Active Pixels
3 × 4080 (Chroma),
1 × 8160 (Luma)
• Luma Channel has 4 Outputs Approaching
Pixel Size
10 mm (H) × 10 mm (V) (Chroma),
5 mm (H) × 5 mm (V) (Luma)
• High Resolution: Color (RGB) Array with
Pixel Pitch
10 mm (Chroma),
5 mm (Luma)
Features
Array with 5 mm Pixels with 8,160 Count
10 mm Pixels with 4,080 Count
• Each Color Channel has 1 Output
Inter-Array Spacing
G to R
R to B
B to L
90 mm (9 Lines Effective)
90 mm (9 Lines Effective)
122.5 mm (12.25 Lines Effective)
Chip Size
50.5 mm (H) × 1.1 mm (V)
Saturation Signal
121,000 e− (Chroma),
110,000 e− (Luma)
Output Sensitivity
14 mV/e− (Chroma),
11 mV/e− (Luma)
Responsivity
R, G, B, Luma (−RAA)
R, G, B, Luma (−DAA)
Mono (−AAA); Chroma
Channels without Filters
34, 23, 21, 9.5 V/mJ/cm2
31, 21, 18, 9.5 V/mJ/cm2
33 V/mJ/cm2
Total Read Noise
120 e−
Dark Current
0.007 pA/Pixel (Chroma),
0.0008 pA/Pixel (Luma)
Dark Current Doubling Temp.
9°C
Dynamic Range
@ 30 MHz Data Rate
60 dB (Chroma),
60 dB (Luma)
Charge Transfer Efficiency
0.999999/Transfer
Photoresponse Non-Uniformity
5% Peak to Peak
120 MHz Data Rate
•
•
•
•
Approaching 30 MHz Data Rate
No Image Lag
Two-Phase Register Clocking
On-Ship Dark Reference
Electronic Exposure Control
Applications
• Machine Vision
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: All Parameters are specified at T = 25°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 5
1
Publication Order Number:
KLI−4104/D
KLI−4104
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KLI−4104 IMAGE SENSOR
Part Number
Description
Marking Code
KLI−4104−AAA−CB−AA
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Standard Grade
KLI−4104−AAA−CB−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Engineering Sample
KLI−4104−AAA−CP−AA
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Standard Grade
KLI−4104−AAA−CP−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Engineering Sample
KLI−4104−RAA−CB−AA
Gen2 Color (RGB), No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Standard Grade
KLI−4104−RAA−CB−AE
Gen2 Color (RGB), No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Engineering Sample
KLI−4104−RAA−CP−AA
Gen2 Color (RGB), No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Standard Grade
KLI−4104−RAA−CP−AE
Gen2 Color (RGB), No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Engineering Sample
KLI−4104−DAA−CB−AA*
Gen1 Color (RGB), No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Standard Grade
KLI−4104−DAA−CB−AE*
Gen1 Color (RGB), No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Engineering Sample
KLI−4104−DAA−CP−AA*
Gen1 Color (RGB), No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Standard Grade
KLI−4104−DAA−CP−AE*
Gen1 Color (RGB), No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Engineering Sample
KLI−4104−A (Lot Code)
(Serial Number)
KLI−4104−R (Lot Code)
(Serial Number)
KLI−4104−D (Lot Code)
(Serial Number)
*Not recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
KLI−4104−12−30−A−EVK
Description
Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
www.onsemi.com
2
KLI−4104
DEVICE DESCRIPTION
Architecture
Luma Pixel 1 Centered on Chroma Pixel 1 Leading Edge
4 Blank 24 Dark
(ea.)
(ea.)
VIDLBO
24 Dark 4 Blank
(ea.)
(ea.)
2040 Higher order pixels − odd
48 Dark
Pixels
VIDLBE
VIDLAO
2040 Lower order pixels − odd
8160 Active Luminance
48 Dark
Pixels
Pixels
2040 Higher order pixels − even
VIDLAE
2040 Lower oder pixels − even
VIDB
VIDR
VIDG
24 Test
4080 Active Color Pixels
Pin 1 Corner
24 Dark 4 Blank
Chroma Pixel 1
Figure 2. Block Diagram
In other words, twenty-four dark reference pixels are on the
leading edge of each luma output, none trailing. See the
block diagram in Figure 2.
The devices are manufactured using NMOS, buried
channel processing and utilize dual layer polysilicon and
dual layer metal technologies.
The architecture of the KLI−4104 provides the ability to
achieve high-resolution color scans (600 dpi) by utilizing
information from all 4 channels. The edge data from the
luminance channel (which provides the image “detail”) can
be combined with the chroma data and the result is a full
resolution color image. In this design there are 4 outputs on
the luminance channel to match the read out rate of the
chroma channels. Both resolution and throughput are
thereby maximized.
The die size is 50.50 × 1.10 mm and is housed in a custom
46-pin, 0.400″ wide, dual in line package. The die center is
located between the blue and red channels and the color
channels are centered in the long direction of the die.
The blue channel center line is displaced +30 mm along the
short dimension of the die from the die center, with pin 1 in
the lower left corner.
The KLI−4104 Image Sensor is a high resolution,
quadri-linear array designed for high-speed color scanning
applications. Each device contains 3 rows of 4,080 active
photoelements, consisting of high performance ‘pinned
diodes’ for improved sensitivity, lower noise and the
elimination of lag. Each row is selectively covered with
a red, green or blue integral filter stripe for unparalleled
spectral separation. The pixel height and pitch is 10 micron
and the center-to-center spacing between color channels is
90 microns, giving an effective nine line delay between
adjacent channels during imaging.
Each device also contains 1 row of 8,160 active
photoelements. This channel has a monochrome response.
The pixel height and pitch is 5 micron and the
center-to-center spacing between this luminance channel
and the blue color channel is 122.5 microns, giving an
effective 12 1/4 line delay.
Readout of the pixel data for each color channel is
accomplished through the use of a single CCD shift register
allowing for a single output per channel with no
multiplexing artifacts. Twenty-four light shielded
photoelements are supplied at the start of each channel to act
as a dark reference. After the 4,080 active pixels, the trailing
region contains 24 pixels dedicated for test. Only the first
16 pixels in this trailing group are configured to be dark
reference pixels. The remaining pixels are used for internal
testing. See the block diagram in Figure 2.
Readout of the pixel data for the luminance channel is
accomplished through the use of four CCD shift registers in
an odd/even and left/right readout configuration.
Forty-eight light shielded photoelements are supplied at the
beginning of each output channel to act as its dark reference.
Why High-Resolution Luma/Low-Resolution
Chrominance?
The human visual system uses more luminance
information than chrominance information. Based on this,
we know that high spatial frequency luminance data
represents the “details” in an image. To achieve a full
resolution (8,160 pixels) color scan, the chrominance data
can be of lower resolution (4,080 pixels) as long as the
“edge/detail” information is sampled at the higher
frequency.
www.onsemi.com
3
KLI−4104
photodiode. This transfer occurs with the bias applied to
TG1L. The accumulation storage region is isolated from the
CCD shift registers during the integration period by the
transfer gate TG2, which is held at barrier potentials. At the
end of the integration period, the CCD register clocking is
stopped with the f1Lx and f2Lx gates (x = A or B) being
held in a ‘high’ and ‘low’ state respectively. Next, the TG2
gate is turned ‘on’ causing the charge to drain from the
accumulation region into f1 storage region. The TG2 gate
is then turned ‘off’, isolating the shift registers from the
accumulation region once again. Complementary clocking
of the f1 and f2 phases now resumes for readout of the
current line of data while the next line of data is integrated.
Notice that each chroma pixel covers 4 times the area of
a single luma pixel. An advantage to having larger pixel
sizes is increased responsivity. This is especially useful in
the chroma channels where some light is absorbed by the
color filter material. Please refer to Figure 12: Typical
Responsivity for the responsivity data.
Image Processing
By utilizing the data from all 4 channels, a high-resolution
color scan can be achieved. The luminance channel can be
used to provide the edge detail in the image.
Chroma Imaging
During the integration period, an image is obtained by
gathering electrons generated by photons incident upon the
photodiodes. The charge collected in the photodiode array
is a linear function of the local exposure. The charge is stored
in the photodiode itself and is isolated from the CCD shift
registers during the integration period by the transfer gates
TG1 and TG2, which are held at barrier potentials. At the
end of the integration period, the CCD register clocking is
stopped with the f1 and f2 gates being held in a ‘high’ and
‘low’ state respectively. Next, the TG gates are turned ‘on’
causing the charge to drain from the photodiode into the TG1
storage region. As TG1 is turned back ‘off’ charge is
transferred through TG2 and into the f1 storage region.
The TG2 gate is then turned ‘off’, isolating the shift registers
from the accumulation region once again. Complementary
clocking of the f1 and f2 phases now resumes for readout
of the current line of data while the next line of data is
integrated.
Charge Transport and Sensing
Luma Imaging
During the integration period, an image is obtained by
gathering electrons generated by photons incident upon the
photodiodes. The charge collected in the photodiode array
is a linear function of the local exposure. The charge is stored
in the photodiode and an accumulation region adjacent to the
Last Active Pixel
(Luma Pixel #8160)
First Active Pixel
(Luma Pixel #1)
(Center)
In either the chroma or luma cases, readout of the signal
charge is accomplished by two-phase, complementary
clocking of the f1 and f2 gates, (labeled f1Cx/f2Cx or
f1Lx/f2Lx, where x = A or B). The register architecture has
been designed for high speed clocking with minimal
transport and output signal degradation, while still
maintaining low (7.25 Vp-p min) clock swings for reduced
power dissipation at 30 MHz thereby, lowering clock noise
and simplifying the driver design. The data in all registers is
clocked simultaneously toward the output structures.
The signal is then transferred to the output structures in
a parallel format at the falling edge of the H2 clocks.
Re-settable floating diffusions are used for the
charge-to-voltage conversion while source followers
provide buffering to external connections. The potential
change on the floating diffusion is dependent on the amount
of signal charge and is given by DVFD = DQ / CFD, where
DVFD is the change in potential on the floating diffusion,
DQ is the amount of charge, and CFD is the capacitance of
the floating diffusion node. Prior to each pixel output,
the floating diffusion is returned to the RD level by the reset
clock, fR.
Luma
Channel
(Edge)
12.25 Lines Spacing (122.5 mm)
Blue
Channel
9 Lines Spacing (90 mm)
Red
Channel
9 Lines Spacing (90 mm)
Green
Channel
Pin 1
Figure 3. Channel Alignment Diagram
www.onsemi.com
4
KLI−4104
Zero re-phasing errors, in the final color image, is
accomplished by having effectively center-aligned
sampling apertures (pixels) in the luminance and chroma
channels.
Even though the luminance and chroma channels are
physically edge-aligned vertically, when scan motion is
Luma Line#
1
2
3
4
5
6
7
8
introduced it has a “center-weighted” sampling effect at the
full resolution scan speed.
The following pixel alignment diagram explains in more
detail the reason for being edge-aligned in the vertical
direction and how the 12.25 line spacing (122.5 mm) works
out to achieve zero re-phasing errors at full resolution.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Chroma Sampling
Aperture
Luma Sampling Aperture
12.25 Chroma Lines Center-to-Center or
24.5 Luma Lines Center-to-Center
between Chroma and Luma Channels
(Dimension Fixed on Sensor)
Figure 4. Pixel Alignment Diagram
High Speed Scanning
The KLI−4104 sensor is ideal for applications such as
high-speed document scanning.
High data throughput is achieved by having a total of 7
outputs, 4 outputs on the luminance channel (4 ⋅ 30 MHz =
120 MHz total data rate), and 1 output per chroma channel
(30 MHz each).
Readout of the pixel data for the luminance channel is
accomplished through the use of two CCD shift registers in
an odd/even pixel readout configuration (4 outputs total).
A system can be designed with the KLI−4104 to achieve
high-resolution color scans (600 dpi), when scanning the
longer length side of A4 paper size at over 150 pages per
minute.
The y-axis of the diagram is the direction of scanning
motion (luminance-leading scan in this case). Note on the
x-axis, that the luminance sampling rate (represented by the
arrows) is 2× that of the chroma channel. Also note the
horizontal dotted line, showing that the arrows are
synchronized, depicting the effective center-aligned
sampling of luminance and chroma channels after 25
luminance lines have been acquired.
This equates to zero re-phasing error between luminance
and chroma signals at full resolution.
If scan speed is changed to lower the vertical resolution,
a small re-phasing error may be introduced.
www.onsemi.com
5
KLI−4104
Pin Description and Physical Orientation
SUB(DA)
1
46
RDLB
LS
2
45
OGLB
LOGB
3
44
VDDLB
LOGR
4
43
fRLB
LOGG
5
42
VIDLBE
TG1C
6
41
SUBLB
TG2C
7
40
VIDLBO
IDC
8
39
f1LB
IGC
9
38
f2LB
f2CB
10
37
TG1L
f1CB
11
36
TG2L
N/C
12
35
N/C
RDC
13
34
RDLA
f2CA
14
33
f2LA
f1CA
15
32
f1LA
SUBG
16
31
VIDLAO
VIDG
17
30
SUBLA
SUBR
18
29
VIDLAE
VIDR
19
28
fRLA
SUBB
20
27
VDDLA
VIDB
21
26
OGCLA
fRC
22
25
VDDC
SUB(DA)
23
24
LOGL
Figure 5. Pinout Diagram
www.onsemi.com
6
KLI−4104
Table 4. PACKAGE PIN DESCRIPTION
Pin
Name
1
SUB(DA)
Description
Substrate/Ground
2
LS
3
LOGB
Light Shield/Exposure Drain
Exposure Control, Blue
4
LOGR
Exposure Control, Red
5
LOGG
Exposure Control, Green
6
TG1C
Transfer Gate 1 Clock, Chroma
7
TG2C
Transfer Gate 2 Clock, Chroma
8
IDC
Test Input, Input Diode, Chroma
Test Input, Input Gate, Chroma
9
IGC
10
f2CB
Phase 2 CCD Clock, Chroma
11
f1CB
Phase 1 CCD Clock, Chroma
12
N/C
No Connection (Recommended these Pins at Ground)
13
RDC
Reset Drain Chroma
14
f2CA
Phase 2 CCD Clock, Chroma
15
f1CA
Phase 1 CCD Clock, Chroma
16
SUBG
Ground Reference, Green
17
VIDG
Output Video, Green
18
SUBR
Ground Reference, Red
19
VIDR
Output Video, Red
20
SUBB
Ground Reference, Blue
21
VIDB
Output Video, Blue
22
fRC
Reset Clock, Chroma
23
SUB(DA)
Substrate/Ground
24
LOGL
Exposure Control, Luma
25
VDDC
Amplifier Supply, Chroma
26
OGCLA
Output Gate, Chroma and Low Pixels Luma
27
VDDLA
Amplifier Supply, Low-High Pixels, Luma
28
fRLA
29
VISLAE
Output Video, Luma Low Pixels, Even Channel
30
SUBLA
Ground Reference, Low-High Pixels, Luma
31
VIDLAO
Output Video, Luma Low Pixels, Odd Channel
32
f1LA
Phase 1 CCD Clock, Luma
33
f2LA
Phase 2 CCD Clock, Luma
34
RDLA
Reset Drain, Low-High Pixels, Luma
Reset Clock, Luma
35
N/C
36
TG2L
No Connection (Recommended these Pins at Ground)
Transfer Gate 2 Clock, Luma
37
TG1L
Transfer Gate 1 Bias, Luma
38
f2LB
Phase 2 CCD Clock, Luma
39
f1LB
Phase 1 CCD Clock, Luma
40
VIDLBO
Output Video, Luma High Pixels, Odd Channel
41
SUBLB
Ground Reference, Low-High Pixels, Luma
42
VIDLBE
Output Video, Luma High Pixels, Even Channel
43
fRLB
44
VDDLB
Amplifier Supply, Low-High Pixels, Luma
45
OGLB
Output Gate, High Pixels, Luma
46
RDLB
Reset Drain, Low-High Pixels, Luma
Reset Clock, Luma
www.onsemi.com
7
Last active luma
pixel appears at this
amplifier
VIDLBE
SUBLB
VIDLBO
8
OGLB
cells
44blank
blank cells
cells
TG1L
TG2L
LOGL
4 blank cells
4 blank cells
48 Dark
www.onsemi.com
Figure 6. Device Schematic
f1CB
f2CB
2 Blank
Cells
24 Test *
4080 Active Pixels
2 Dark
6 Open Pixels
Description of 24 Test Pixels for Chroma Channel *
IDC
IGC
TG1C
TG2C
LS
LOGx
(R,G,B)
16 Dark
Last 4080 Active Pixels
Chroma Channel Schematic (1 of 3 channels, not drawn to scale)
VDDLB
RDLB fRLB
Luma Channel Schematic, (not drawn to scale)
24 Dark
4 Blank
Cells
(8160 total Active luma Pixels)
f2LA
f1LA
f1LB
f2LB
f2CA
f1CA
RDC
fRC
SUBx
(R,G,B)
VDDC
Leading 4080 Active Pixels
4 blank
4 blank cells
Pixel 1
VIDx
( R,G,B)
OGCLA
48 Dark
4 blank cells
4 blank
RDLA
fRLA
VDDLA
VIDLAE
SUBLA
VIDLAO
First active luma
pixel appears at this
amplifier
KLI−4104
KLI−4104
Table 5. PIXEL CLOCK VIDEO OUTPUT
Leading Blanks
(4)
Leading DARK
Pixels
(24)
ACTIVE Pixels
Pixel
Clock
Cycle
VIDR
VIDG
VIDB
VIDLAO
VIDLAE
VIDLBO
VIDBLE
1
Blank(1)
Blank(1)
Blank(1)
Blank(1)
Blank(1)
Blank(1)
Blank(1)
2
Blank(2)
Blank(2)
Blank(2)
Blank(2)
Blank(2)
Blank(2)
Blank(2)
3
Blank(3)
Blank(3)
Blank(3)
Blank(3)
Blank(3)
Blank(3)
Blank(3)
4
Blank(4)
Blank(4)
Blank(4)
Blank(4)
Blank(4)
Blank(4)
Blank(4)
5
Dark(1)
Dark(1)
Dark(1)
Dark(1)
Dark(1)
Dark(1)
Dark(1)
6
Dark(2)
Dark(2)
Dark(2)
Dark(2)
Dark(2)
Dark(2)
Dark(2)
7
Dark(3)
Dark(3)
Dark(3)
Dark(3)
Dark(3)
Dark(3)
Dark(3)
8
Dark(4)
Dark(4)
Dark(4)
Dark(4)
Dark(4)
Dark(4)
Dark(4)
9
Dark(5)
Dark(5)
Dark(5)
Dark(5)
Dark(5)
Dark(5)
Dark(5)
…
…
…
…
…
…
…
…
26
Dark(22)
Dark(22)
Dark(22)
Dark(22)
Dark(22)
Dark(22)
Dark(22)
27
Dark(23)
Dark(23)
Dark(23)
Dark(23)
Dark(23)
Dark(23)
Dark(23)
28
Dark(24)
Dark(24)
Dark(24)
Dark(24)
Dark(24)
Dark(24)
Dark(24)
29
Active(1)
Active(1)
Active(1)
Active(1)
Active(2)
Active(8159)
Active(8160)
30
Active(2)
Active(2)
Active(2)
Active(3)
Active(4)
Active(8157)
Active(8158)
31
Active(3)
Active(3)
Active(3)
Active(5)
Active(6)
Active(8155)
Active(8156)
32
Active(4)
Active(4)
Active(4)
Active(7)
Active(8)
Active(8153)
Active(8154)
…
…
…
…
…
…
…
…
2066
Active(2038)
Active(2038)
Active(2038)
Active(4075)
Active(4076)
Active(4085)
Active(4086)
2067
Active(2039)
Active(2039)
Active(2039)
Active(4077)
Active(4078)
Active(4083)
Active(4084)
2068
Active(2040)
Active(2040)
Active(2040)
Active(4079)
Active(4080)
Active(4081)
Active(4082)
Clock Hold during Luma Transfer Transition to Minimize Noise Feedthru
TEST Group
Lagging DARK
Pixels
(24)
Blanks
(2) Chroma
2069
Active(2041)
Active(2041)
Active(2041)
Active(1)
Active(2)
Active(8159)
Active(8160)
2070
Active(2042)
Active(2042)
Active(2042)
Active(3)
Active(4)
Active(8157)
Active(8158)
2080
Active(2043)
Active(2043)
Active(2043)
Active(5)
Active(6)
Active(8155)
Active(8156)
…
…
…
…
…
…
…
…
4105
Active(4077)
Active(4077)
Active(4077)
Active(4073)
Active(4074)
Active(4087)
Active(4088)
4106
Active(4078)
Active(4078)
Active(4078)
Active(4075)
Active(4076)
Active(4085)
Active(4086)
4107
Active(4079)
Active(4079)
Active(4079)
Active(4077)
Active(4078)
Active(4083)
Active(4084)
4108
Active(4080)
Active(4080)
Active(4080)
Active(4079)
Active(4080)
Active(4081)
Active(4082)
4109
Dark(1)
Dark(1)
Dark(1)
Dark(1)
Dark(1)
Dark(1)
Dark(1)
4110
Dark(2)
Dark(2)
Dark(2)
Dark(2)
Dark(2)
Dark(2)
Dark(2)
…
…
…
…
…
…
…
…
4123
Dark(15)
Dark(15)
Dark(15)
Dark(15)
Dark(15)
Dark(15)
Dark(15)
4124
Dark(16)
Dark(16)
Dark(16)
Dark(16)
Dark(16)
Dark(16)
Dark(16)
4125
Open(1)
Open(1)
Open(1)
Dark(17)
Dark(17)
Dark(17)
Dark(17)
4126
Open(2)
Open(2)
Open(2)
Dark(18)
Dark(18)
Dark(18)
Dark(18)
4127
Open(3)
Open(3)
Open(3)
Dark(19)
Dark(19)
Dark(19)
Dark(19)
4128
Open(4)
Open(4)
Open(4)
Dark(20)
Dark(20)
Dark(20)
Dark(20)
4129
Open(5)
Open(5)
Open(5)
Dark(21)
Dark(21)
Dark(21)
Dark(21)
4130
Open(6)
Open(6)
Open(6)
Dark(22)
Dark(22)
Dark(22)
Dark(22)
4131
Dark(17)
Dark(17)
Dark(17)
Dark(23)
Dark(23)
Dark(23)
Dark(23)
4132
Dark(18)
Dark(18)
Dark(18)
Dark(24)
Dark(24)
Dark(24)
Dark(24)
4133
Blank(1)
Blank(1)
Blank(1)
4134
Blank(2)
Blank(2)
Blank(2)
NOTE: 2 lines of Luma channels per every Chroma channel.
www.onsemi.com
9
OVERCLOCK FOR SYMMETRY
KLI−4104
IMAGING PERFORMANCE
Imaging Performance Operational Conditions
Specifications given under nominally specified operating
conditions for the given mode of operation at 25°C,
fCLK = 1 MHz, AR cover glass, color filters where
applicable, no exposure control (line time = integration
time), and an active load as shown in Figure 17, unless
otherwise specified. See notes for further descriptions.
Table 6. IMAGING PERFORMANCE SPECIFICATIONS
Description
Symbol
Min.
Nom.
Max.
Unit
Notes
Verification
Plan
VSAT
1.5
1.7
−
Vp-p
1, 8, 9, 17
Die21
8, 9
Design22
CHROMA CHANNELS
Saturation Output Voltage
DVO/DNe
−
14
−
mV/e−
Ne,sat
−
121 k
−
e−
1, 8, 9
Design22
DR
−
60
−
dB
3
Design22
DSNU
−
2
16
mV
DC Gain, Amplifier
ADC
−
0.74
−
Dark Current, @ 40°C
IDARK
−
0.007
2
Charge Transfer Efficiency
@ 30 MHz Data Rate
@ 2 MHz Data Rate
CTE
0.999995
0.999995
0.999992
0.999997
−
−
−
−
1
0.005
−
−
−
8.6
−
−
−
−
−
−
0.03
0.05
0.1
0.2
0.3
−
−
−
−
−
Output Sensitivity
Saturation Signal Charge
Dynamic Range
Dark Signal Non-Uniformity
Lag
@ 30 MHz Data Rate
@ 2 MHz Data Rate
VODC
Smear
@ 450 nm
@ 500 nm
@ 550 nm
@ 600 nm
@ 650 nm
Smear
Design22
pA/Pixel
14, 17
Die21
4, 19
L
DC Output, Offset
Die21
Design22
Die21
%
15
Design22
Die21
V
8, 9
Design22
Design22
%
Response Non-Linearity
RNL
−
3
−
%
16
Design22
Darkfield Defect, Chroma
Brightpoint
Dark Def
−
−
0
Allowed
11, 17
Die21
Brightfield Defect, Chroma Dark or
Bright
Bfld Def
−
−
3
Allowed
10, 12, 19
Die21
Exposure Control Defects, Chroma
Channels
Exp Def
−
−
64
Allowed
10, 13, 20
Figure 11
Die21
−
−
−
34
23
21
−
−
−
−
−
−
650
540
460
−
−
−
KLI−4104−RAA CONFIGURATION − GEN2 COLOR
Responsivity
Red
Green
Blue
Peak Responsivity Wavelength
Red
Green
Blue
RMAX
lR
V/mJ/cm2
Design22
nm
Design22
Photoresponse Uniformity,
Low Frequency
PRNU,
Low
−
4
15
%p−p
Die21
Photoresponse Uniformity,
Medium Frequency
PRNU,
Medium
−
4
15
%p−p
Die21
www.onsemi.com
10
KLI−4104
Table 6. IMAGING PERFORMANCE SPECIFICATIONS (continued)
Description
Symbol
Min.
Nom.
Max.
−
−
−
31
21
18
−
−
−
−
−
−
650
540
460
−
−
−
Unit
Notes
Verification
Plan
V/mJ/cm2
19
Design22
nm
19
Design22
KLI−4104−DAA CONFIGURATION − GEN1 COLOR (Note 23)
Responsivity
Red
Green
Blue
RMAX
Responsivity Wavelength
Red
Green
Blue
lR
Photoresponse Uniformity,
Low Frequency
PRNU,
Low
−
4
15
%p−p
19
Die21
Photoresponse Uniformity,
Medium Frequency
PRNU,
Medium
−
4
15
%p−p
19
Die21
V/mJ/cm2
19
Design22
nm
19
Design22
KLI−4104−AAA CONFIGURATION − MONOCHROME for the “Chroma” Channels
Responsivity
Monochrome, Chroma Channels
RMAX
−
33
−
−
675
−
Responsivity Wavelength
Monochrome
lR
Photoresponse Uniformity,
Low Frequency
PRNU,
Low
−
4
10
%p−p
19
Die21
Photoresponse Uniformity,
Medium Frequency
PRNU,
Medium
−
4
10
%p−p
19
Die21
VSAT
1.0
1.3
−
Vp-p
1, 8, 9, 17
Die21
DVO/DNe
−
11.5
−
mV/e−
8, 9
Design22
Ne,sat
−
110 k
−
e−
1, 8, 9
Design22
8, 9
±10%
Design22
LUMA CHANNELS
Saturation Output Voltage
Output Sensitivity
Saturation Signal Charge
RMAX
−
9.5
−
V/mJ/cm2
DR
−
60
−
dB
3
Design22
DSNU
−
2
16
mV
17
Die21
DC Gain, Amplifier
ADC
−
0.74
−
Dark Current, @ 40°C
IDARK
−
0.0008
0.02
Charge Transfer Efficiency
@ 30 MHz Data Rate
@ 2 MHz Data Rate
CTE
0.999995
0.999995
0.999997
0.999997
−
−
−
−
1
0.03
−
−
VODC
−
8.6
−
V
8, 9
Design22
Photoresponse Non-Uniformity,
Low Frequency
PRNU,
Low
−
4
10
% p-p
5, 19
Die21
Photoresponse Non-Uniformity,
Medium Frequency
PRNU,
Medium
−
4
10
% p-p
6, 19
Die21
Photoresponse Non-Uniformity,
High Frequency
PRNU,
High
−
4
10
% p-p
7, 19
Die21
Smear @ 550 nm
Smear
−
0.12
−
%
RNL
−
3.4
−
%
16
Design22
Dark Def
−
−
0
Allowed
11, 17
Die21
Responsitivity, @ 675 nm Luma
Channel
Dynamic Range
Dark Signal Non-Uniformity
Lag
@ 30 MHz Data Rate
@ 2 MHz Data Rate
DC Output, Offset
Response Non-Linearity
Darkfield Defect, Luma Brightpoint
Design22
pA/Pixel
14, 17
Die21
4, 19
L
Design22
Die21
%
www.onsemi.com
11
15
Design22
Die21
Design22
KLI−4104
Table 6. IMAGING PERFORMANCE SPECIFICATIONS (continued)
Symbol
Min.
Nom.
Max.
Unit
Notes
Verification
Plan
Brightfield Defect, Luma Dark or
Bright
Bfld Def
−
−
6
Allowed
17, 18, 19
Die21
Exposure Control Defects,
Luma Channels
Exp Def
−
−
128
Allowed
13, 20
Figure 11
Die21
Description
LUMA CHANNELS
1. Defined as the maximum output level achievable before linearity or PRNU performance is degraded beyond specification.
2. With color filter. Values specified at filter peaks. 50% bandwidth = ±30 nm. Color filter arrays become transparent after 710 nm. It is
recommended that a suitable IR cut filter be used to maintain spectral balance and optimal MTF. See Figure 12.
3. As measured at 30 MHz data rate. This device utilizes 2-phase clocking for cancellation of driver displacement currents. Symmetry between
f1 and f2 phases must be maintained to minimize clock noise.
4. Measured per transfer. For a Chroma line: (0.99999) ⋅ 8268 = 0.92065. For a Luma line: (0.99999) ⋅ 2092 = 0.97930.
5. Low frequency response is measured across the entire array with a 1000 pixel-moving window and a 5 pixel median filter evaluated under
a flat field illumination.
6. Medium frequency response is measured across the entire array with a 50 pixel-moving window and a 5 pixel median filter evaluated under
a flat field illumination.
7. High frequency response non-uniformity represents individual pixel defects evaluated under a flat field illumination. An individual pixel value
may deviate above or below the average response for the entire array. Zero individual defects allowed per this specification.
8. Increasing the current load (nominally 4.7 mA) to improve signal bandwidth will decrease these parameters.
9. If resistive loads are used to set current, the amplifier gain will be reduced, thereby reducing the output sensitivity and net responsivity.
10. Defective pixels will be separated by at least one non-defective pixel within and across the color channels.
11. Pixels whose response is greater than the average response by the specified threshold, (16 mV). See Figure 11.
12. Pixels whose response is greater or less than the average response by the specified threshold, (±15%). See Figure 11.
13. Pixels whose response deviates from the average pixel response by the specified threshold, (4.5 mV for Chroma, 5.5 mV for Luma), when
operating in exposure control mode with an integration time that is 50% of the line time. See Figure 11. If dark pattern correction is used with
exposure control, the dark pattern acquisition should be completed with exposure control actuated. Dark current tends to suppress the
magnitude of these defects as observed in typical applications, hence line rate changes may affect perceived defect magnitude. Measured
at 1 MHz data rate.
14. Dark current doubles approximately every +9°C.
15. Residual charge in the first field after transfer is used to determine lag measurement.
16. Nominal value was measured at an output of 1.5 V signal level at 30 MHz. Expect linearity to be better than 10% over the entire range.
17. As measured at 1 MHz data rate.
18. Pixels whose response is greater or less than the average response by the specified threshold, (±10%). See Figure 11.
19. As measured at 1 MHz data rate and with an average output level of 70% VSAT.
20. As measured at 1 MHz data rate and with an average output level of 100 mV. With the exposure control active − the timing is adjusted so
exposure time = 50% ⋅ integration time.
21. A parameter that is measured on every sensor during production testing.
22. A parameter that is quantified during the design verification activity.
23. Configuration KLI−4104−DAA uses Gen1 color filter set and is not recommended for new designs.
www.onsemi.com
12
KLI−4104
TYPICAL PERFORMANCE CURVES
Non-Linearity @ f = 30 MHz, Luma Channel
10
LumaA
LumaB
5
0
−5
−10
−15
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Signal (V)
Figure 7. Typical Response Non-Linearity (%), Luma
Non-Linearity @ f = 30 MHz, Blue Channel
10
8
6
4
2
0
−2
−4
−6
−8
−10
0
0.5
1
1.5
Signal (V)
Figure 8. Typical Response Non-Linearity (%), Blue
www.onsemi.com
13
2
2.5
KLI−4104
f = 30 MHz
1
0.99999
0.99998
0.99997
HCT
0.99996
0.99995
0.99994
LumaA
0.99993
LumaB
0.99992
Blue
0.99991
0.99990
5.5
5.75
6
6.25
6.5
6.75
7
7.25
7.5
7.75
8
HSWING (V)
Figure 9. Typical CTE Performance vs. H Clock Levels
f = 30 MHz, HSWING = 6.5 V
9
8
Fixed Loss (%)
7
6
5
4
LumaA
LumaB
Blue
3
2
1
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
OG (V)
Figure 10. Typical Fixed Charge Loss vs. OG at 30 MHz
www.onsemi.com
14
2
2.25
KLI−4104
DEFECT DEFINITIONS
Notes 12, 18: Bright
Field Bright Pixel
Note 13: Bright Field
Exposure Control
Bright Defect
Average
Pixel
Average
Pixel
Signal Out
Signal Out
Note 11:
Dark Field
Note 13: Bright
Field Exposure
Control Dark
Defect
Notes 12, 18: Bright
Field Dark Pixel
Exposure
Exposure
Figure 11. Defect Pixel Classification
50
45
40
Responsivity (V/mJ/cm2)
35
30
25
20
15
10
5
0
300
400
500
600
700
800
900
1000
Wavelength (nm)
Figure 12. Typical Responsivity for KLI−4104−RAA−CB Configuration (Sealed Clear Glass)
www.onsemi.com
15
1100
KLI−4104
50
45
40
Responsivity (V/mJ/cm2)
35
30
25
20
15
10
5
0
300
400
500
600
700
800
900
1000
1100
Wavelength (nm)
Figure 13. Typical Responsivity for KLI−4104−RAA−CP Configuration (Taped Clear Glass).
Data Taken without Cover Glass
50
45
40
Responsivity (V/mJ/cm2)
35
30
25
20
15
10
5
0
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000 1050 1100
Wavelength (nm)
Figure 14. Typical Responsivity for KLI−4104−AAA−CB Configuration (Sealed Clear Glass)
www.onsemi.com
16
KLI−4104
50
45
40
Responsivity (V/mJ/cm2)
35
30
25
20
15
10
5
0
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000 1050 1100
Wavelength (nm)
Figure 15. Typical Responsivity for KLI−4104−AAA−CP Configuration (Taped Clear Glass).
Data Taken without Cover Glass
www.onsemi.com
17
KLI−4104
OPERATION
Table 7. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Unit
Notes
Gate Pin Voltage
VGATE
0
16
V
1, 2
Pin-to-Pin Voltage
VPIN−PIN
−
16
V
1, 3
Diode Pin Voltage
VDIODE
−0.5
16
V
1, 4
IDD
−2
−8
mA
5
Output Load Capacitance
CVID,Load
−
10
pF
7
CCD Clocking Frequency
fCLK
−
30
MHz
6
Output Bias Current
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Referenced to substrate voltage.
2. Includes pins: f1CA, f1CB, f2CA, f2CB, f1LA, f1LB, f2LA, f2LB, TG1C, TG2C, TG1L, TG2L, fRC, fRLA, fRLB, OGCLA, OGLB, IGC,
LOGR, and LOGG.
3. Voltage difference (either polarity) between any two pins.
4. Includes pins: VIDR, VIDG, VIDB, VIDLAO, VIDLAE, VIDLBO, VIDLBE, SUB(DA), SUBR, SUBG, SUBB, SUBLA, SUBLB, RDC, RDLA,
RDLB, VDDC, VDDLA, VDDLB, LS and IDC.
5. Care must be taken not to short output pins to ground during operation as this may cause permanent damage to the output structures.
6. Charge transfer efficiency will degrade at frequencies higher than the maximum clocking frequency. VIDR, VIDG, VIDB, VIDLAO, VIDLAE,
VIDLBO, and VIDLBE load current values may need to be adjusted as well.
7. Exceeding the upper limit on output load capacitance will greatly reduce the output frequency response. Thus, direct probing of the output
pins with conventional oscilloscope probes is not recommended.
8. The absolute maximum ratings indicate the limits of this device beyond which damage may occur. The Operating ratings indicate the
conditions where the design should operate the device. Operating at or near these ratings do not guarantee specific performance limits.
Guaranteed specifications and test conditions are contained in the Imaging Performance section.
Device Input ESD Protection Circuit (Schematic)
To Device
Function
I/O Pin
Vt − 20 V
SUB
CAUTION:
To allow for maximum performance, this device was designed with limited input protection; thus, it is sensitive to electrostatic
induced damage. These devices should be installed in accordance with strict ESD handling procedures!
Figure 16. Device Input ESD Protection Circuit
www.onsemi.com
18
KLI−4104
DC Bias Operating Conditions
Table 8. DC BIAS OPERATING CONDITIONS
Description
Substrate
Accumulation Phase Bias, Luma
Reset Drain Bias
Symbol
Min.
Nom.
Max.
Unit
VSUBR, VSUBG, VSUBB,
VSUBLA, VSUBLB, VSUB(DA)
−
0
−
V
Notes
VTG1L
−
0
0.5
V
2, 3
VRDC, VRDLA, VRDLB
10.5
11
11.5
V
2
VVDDC, VVDDLA, VVDDLB
14.5
15
15.5
V
2
IIDDC, IIDDLA, IIDDLB
−2
−4.7
−8
mA
1, 2
VOGCLA, VOGLB
0.5
0.7
0.9
V
2, 3
Light Shield/Drain Bias
VLS
12
15
15.5
V
2
Test Pin − Input Gate
VIGC
−
0
−
V
2, 3
Test Pin − Input Diode
VIDC
12
15
15.5
V
2
Output Buffer Supply
Output Bias Current/Channel
Output Gate Bias
1. A current sink must be supplied for each output. Load capacitance should be minimized so as not to limit bandwidth. RX serves as the load
bias for the on-chip amplifiers. The values of RX and RL should be chosen to optimize performance for a given operating frequency.
The values shown in Figure 17 below represent just one solution.
2. Referenced to substrate voltage.
3. Do not exceed absolute maximum levels for diode pins voltage.
Typical Output Bias/Buffer Circuit
VDD
0.1 mF
2N2369
or Similar*
To Device
Output Pin: VIDn
(Minimize Path Length)
Buffered Output
RX = 150 W*
RL = 750 W*
Figure 17. Typical Output Bias/Buffer Circuit
www.onsemi.com
19
KLI−4104
AC Operating Conditions
Table 9. CLOCK LEVELS
Symbol
30 MHz
Operation
1 MHz
Operation
Max.
Unit
Notes
CCD Element Duration
1e (= 1/fCLK)
0.033
1
−
ms
3, 1e Count
Line/Integration Period
Chroma
Luma
1L (= tINT)
ms
138.4
68.9
4,156
2,087
−
−
3, 4
4,156e Counts
2,086e Counts
ms
0.533
0.566
16
17
−
−
3, 5
16e Counts
17e Counts
Description
PD-CCD Transfer Period
Chroma
Luma
tPD
Transfer Gate 1 Clear
tTG1
0.033
1
−
ms
3, 1e Count
Transfer Gate 2 Clear
tTG2
0.033
1
−
ms
3, 1e Count
Charge Drain Duration as % of Line Time
Chroma
Luma
tDR
%
2
−
−
−
−
90
90
Clamp to f2 Delay
tCD
5
−
−
ns
1
Sample to Reset Edge Delay
tSD
5
−
−
ns
1
LOG Rise Time
tLOGRISE
0.066
2
−
ms
3, 2e Count
LOG Fall Time
tLOGFALL
0.066
2
−
ms
3, 2e Count
1.
2.
3.
4.
Recommended delays for Correlated Double Sampling (CDS) of output.
Maximum value stated ensures proper linearity performance. Integration times shorter than 10% of the line time increase device non-linearity.
Where noted as a multiple of CCD element durations, scale the appropriate times listed if the clock element time changes.
This value represents the shortest line period. Integration time can be shorter than a line period with the use of electronic exposure control
or by extending the line period with horizontal overclocking.
5. If the application uses values less than those listed here expect degradation in lag and/or exposure control performance, where appropriate.
www.onsemi.com
20
KLI−4104
ELECTRICAL CHARACTERISTICS AC
Table 10. CLOCK LEVEL CONDITIONS FOR OPERATION
Symbol
Min.
1 MHz
Operation
30 MHz
Operation
Max.
Unit
Notes
CCD Readout Clocks High
Vf1xH, Vf2xH
6.25
6.5
7.25
9.0
V
3, 7
CCD Readout Clocks Low
Vf1xL, Vf2xL
−0.1
0.0
0.0
0.1
V
1, 3
VTGxCH
VTGxLH
6.25
7.00
6.5
7.5
7.25
8.00
9.0
10.0
Transfer Clocks Low
VTGxL
−0.1
0.0
0.0
0.1
V
1, 4
Reset Clock High (Normal Mode)
VfRxH
6.25
6.5
7.25
9.0
V
5, 7
Description
Transfer Clocks High
Chroma
Luma
Reset Clock Low
V
4, 7
7
VfRxL
−0.1
0.0
0.0
0.1
V
1, 5
Exposure Clocks High
VLOGxH
6.25
6.5
7.25
9.0
V
2, 6, 7
Exposure Clocks Low
VLOGxL
−0.1
0.0
0.0
0.1
V
1, 2, 6
1. Care should be taken to insure that low rail overshoot does not exceed −0.5 VDC. Exceeding this value may result in non-photogenerated
charged being injected into the video signal.
2. Connect pin to ground potential for applications where exposure control is not required.
3. Where “x” can be “CA”, “CB”, “LA”, or “LB”.
4. Where “x” can be “1” or “2”.
5. Where “x” can be “C”, “LA”, or “LB”.
6. Where “x” can be “R”, “G”, or “B”.
7. For high level clocks at 30 MHz operation, use the values found in the “30 MHz Operation” column. This value represents the recommended
setting for operation. Operating ranges for the high level clocks should be held to a variation range of ±0.25. Clock levels below this range
will result in loss of charge transfer efficiency and other performance degradations.
Table 11. CLOCK VOLTAGE DETAIL CHARACTERISTICS
Description
Symbol
Min.
Nom.
Max.
Unit
Notes
TG1C High-Level Variation
V1HH
−
0.50
1
V
High-Level Coupling
TG1C Low-Level Variation
V1LL
−
0.14
1
V
Low-Level Coupling
TG2x High-Level Variation
V2HL
−
0.28
1
V
High-Level Coupling
TG2x Low-Level Variation
V2LH
−
0.46
1
V
Low-Level Coupling
f1x High-Level Variation
f1HH
−
0.30
1
V
f1x High-Level Variation
f1HL
−
0.07
1
V
f1x Low-Level Variation
f1LH
−
0.16
1
V
f1x Low-Level Variation
f1LL
−
0.25
1
V
f2x High-Level Variation
f2HH
−
0.40
1
V
f2x High-Level Variation
f2HL
−
0.06
1
V
f2x Low-Level Variation
f2LH
−
0.10
1
V
f2x Low-Level Variation
f2LL
−
0.27
1
V
f1x − f2x Cross-Over
f1CR1
40
50
60
%
Rising Side of f1
f1x − f2x Cross-Over
f1CR2
40
50
60
%
Falling Side of f1
fRx High-Level Variation
RGHH
−
0.19
1
V
fRx High-Level Variation
RGHL
−
0.20
1
V
fRx Low-Level Variation
RGLH
−
0.11
1
V
fRx Low-Level Variation
RGLL
−
0.30
1
V
TG1C Rise Time
tV1R
−
0.26
1
ms
2
TG2x Rise Time
tV2R
−
0.55
1
ms
2
TG1C Fall Time
tV1F
−
0.43
1
ms
2
TG2x Fall Time
tV2F
−
0.31
1
ms
2
f1 Rise Time
tH1R
−
9.0
10
ns
2
f2 Rise Time
tH2R
−
6.9
10
ns
2
www.onsemi.com
21
KLI−4104
Table 11. CLOCK VOLTAGE DETAIL CHARACTERISTICS (continued)
Description
Symbol
Min.
Nom.
Max.
Unit
Notes
tH1F
−
5.8
10
ns
2
f2 Fall Time
tH2F
−
5.4
10
ns
2
fRx Rise Time
tRGR
−
2.0
4
ns
2
fRx Fall Time
tRGF
−
2.2
4
ns
2
Reset Pulse Width
tRGW
−
5.0
−
ns
f1 Fall Time
1. f1, f2 clock frequency: 30 MHz. The maximum and minimum values in this table are supplied for reference. Testing against the device
performance specifications is performed using the nominal values.
2. Longer times will degrade noise performance.
Table 12. CLOCK LINE CAPACITANCE
Description
Symbol
Min.
Nom.
Max.
Unit
Notes
Phase 1 Clock Capacitance
Cf1CA, Cf1CB
−
330
−
pF
1
Phase 2 Clock Capacitance
Cf2CA, Cf2CB
−
270
−
pF
1
Transfer Gate 1 Capacitance
CTG1C
−
185
−
pF
Transfer Gate 2 Capacitance
CTG2C
−
320
−
pF
Exposure Gate Capacitance
CLOGR, CLOGG, CLOGB
−
33
−
pF
CfRC
−
10
−
pF
Phase 1 Clock Capacitance
Cf1LA, Cf1LB
−
400
−
pF
Phase 2 Clock Capacitance
Cf2LA, Cf2LB
−
300
−
pF
Transfer Gate 2 Capacitance
CTG2L
−
230
−
pF
CLOGL
−
75
−
pF
CfRLA, CfRLB
−
6
−
pF
CHROMA
Reset Gate Capacitance
LUMA
Exposure Gate Capacitance
Reset Gate Capacitance
1. The value listed is the effective value, or equal to 1/2 the total load capacitance per CCD phase. Since the CCDs are driven from both ends
of the sensor, the total load capacitance per horizontal drive function is approximately twice the value listed. These values were calculated
from design targets. These values do not take into account the device package.
www.onsemi.com
22
KLI−4104
TIMING
Edge Alignment
TG1HH
tW
100%
90%
TG1
TG2HL
TG2
50%
10%
0%
TG2LH
tR
TG1LL
tR
tOVERLAP
Figure 18. Transfer Timing Edge Alignment
Pixel Timing
tRGW
RGHH
RGHL
100%
90%
50%
10%
0%
tRGR
RGLH
tRGF
RGLL
Figure 19. Pixel Timing Detail
www.onsemi.com
23
KLI−4104
Pixel Timing Edge Alignment
tf2W
tf1W
f1HH
f2HH
f2HL
f1HL
f1
f2
100%
100%
90%
90%
f2
f2
f1CR2
f1CR1
50%
50%
f1
f1
10%
0%
10%
0%
f1LH
tf1R
tf1F
f1LL
f2LH
tf2R
tf2F
f2LL
Figure 20. f1 and f2 Edge Alignment
Line Timing
Line Timing, Luma
f1Lx
4e 24e
2040e
f2Lx
4e 24e
2040e
4e 24e
2040e
4e 24e
2040e
19e
tINT
TG2L
LOGL
tDR
Line Timing, Chroma
tEXP
Clock Hold during TGxL Transition to
Minimize Noise Feedthru
f1Cx
4e 24e
2040e = 1/2 Line
f2Cx
4e 24e
2040e = 1/2 Line
2 Overclock Cycles to Match Chroma
and Luma Line Timing
2040e = 1/2 Line
24e
2
e
2
e
2040e = 1/2 Line
24e
2
e
2
e
19e
tINT
TG1C
TG2C
LOGx
(R,G,B)
tEXP
tDR
Figure 21. Line Timing Diagram
www.onsemi.com
24
KLI−4104
Luma Accumulation Gate-to-Gate Transfer Timing
f1Lx
1e
First Dark Reference Pixel Data Valid
f2Lx
TG2L
tTG2
tPD
tDRluma
LOGL
Chroma Photodiode-to-CCD Transfer Timing
f1Cx
1e
First Dark Reference Pixel Data Valid
f2Cx
TG1C
tTG1
tPD
tTG2
TG2C
LOGx
(R,G,B)
tDRchroma
Figure 22. Transfer Timing Diagram
Output Timing
f2CCA, f2CB,
f2LA, f2LB
tR
1 Pixel
tCD
tRGW
fRC, fRL
VIDLAO, VIDLAE,
VIDLBO, VIDLBE,
VIDR, VIDG, VIDB
VFEEDTHRU
VSAT
VDARK
tSD
Clamp*
Sample*
*Required for Optional Off-Chip, Analog, Correlated Double Sampling (CDS) Signal Processing
Figure 23. Output Timing Diagram
www.onsemi.com
25
KLI−4104
STORAGE AND HANDLING
Table 13. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Unit
Notes
Storage Temperature
TST
−25
80
°C
2
Humidity
RH
5
90
%
1
Operating Temperature
TOP
0
70
°C
3
Guaranteed Temperature of Performance
TSP
25
40
°C
4
1.
2.
3.
4.
T = 25°C. Excessive humidity will degrade MTTF.
Long-term storage toward the maximum temperature may accelerate color filter degradation.
Noise performance will degrade at higher temperatures.
See section for Imaging Performance Specifications.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
www.onsemi.com
26
KLI−4104
MECHANICAL INFORMATION
Completed Assembly
Figure 24. Completed Assembly
www.onsemi.com
27
KLI−4104
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
28
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
KLI−4104/D
