LC717A00ARGEVK

LC717A00AR Capacitance‐Digital‐Converter LSI for Electrostatic Capacitive Touch Sensors Overview The LC717A00AR is a high-performance, low-cost capacitancedigital-converter LSI for electrostatic capacitive touch sensor, especially focused on usability. It has 8 channels capacitance-sensor input. The built-in logic circuit can detect the state (ON/OFF) of each input and output the result. This makes it ideal for various switch applications. The calibration function is automatically performed by the built-in logic circuit during power activation or whenever there are environmental changes. In addition, since initial settings of parameters, such as gain, are configured, LC717A00AR can operate as stand-alone when the recommended switch pattern is applied. Also, since LC717A00AR has a serial interface compatible with I2Ct and SPI bus, parameters can be adjusted using external devices whenever necessary. Moreover, outputs of the 8-input capacitance data can be detected and measured as 8-bit data. www.onsemi.com VCT28 CASE 601AE MARKING DIAGRAM XXXXXXXX YMDDD Features • Detection System: Differential Capacitance Detection • • • • • • • • (Mutual Capacitance Type) Input Capacitance Resolution: Can Detect Capacitance Changes in the Femto Farad Order Measurement Interval (8 Differential Inputs): ♦ 18 ms (Typ) (at Initial Configuration) ♦ 3 ms (Typ) (at Minimum Interval Configuration) External Components for Measurement: Not Required Current Consumption: ♦ 320 mA (Typ) (VDD = 2.8 V) ♦ 740 mA (Typ) (VDD = 5.5 V) Supply Voltage: 2.6 V to 5.5 V Detection Operations: Switch Packages: VCT28 Interface: I2C Compatible Bus or SPI Selectable © Semiconductor Components Industries, LLC, 2013 October, 2017 − Rev. 3 1 XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data ORDERING INFORMATION See detailed ordering and shipping information on page 11 of this data sheet. Publication Order Number: LC717A00AR/D LC717A00AR Specifications Table 1. ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS = 0 V) Symbol Ratings Unit Supply Voltage VDD −0.3 to +6.5 V Input Voltage VIN −0.3 to VDD + 0.3 V (Note 1) Output Voltage VOUT −0.3 to VDD + 0.3 V (Note 2) Power Dissipation Pd max 160 mW Parameter Remarks TA = +105_C, Mounted on a substrate (Note 3) Peak Output Current IOP ±8 mA Per terminal, 50% Duty ratio (Note 2) Total Output Current IOA ±40 mA Output total value of LSI, 25% Duty ratio Storage Temperature Tstg −55 to +125 _C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Apply to Cin0 to 7, Cref, nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN. 2. Apply to Cdrv, Pout0 to 7, SDA, SO, ERROR, INTOUT. 3. 4-layer glass epoxy board (40 × 50 × 0.8t mm). Table 2. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Operating Supply Voltage Conditions Min Typ Max Unit VDD 2.6 − 5.5 V Supply Ripple + Noise VPP − − ±20 mV Operating Temperature Topr −40 25 105 _C Remarks (Note 4) Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 4. Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended. In this case, the small-valued capacitor should be at least 0.1 mF, and is mounted near the LSI. Table 3. ELECTRICAL CHARACTERISTICS (VSS = 0 V, VDD = 2.6 to 5.5 V, TA = −40 to +105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143 kHz. Not tested at low temperature before shipment.) Parameter Symbol Capacitance Detection Resolution N Output Noise RMS NRMS Conditions Minimum gain setting Min Typ Max Unit Remarks − − 8 bit − − ±1.0 LSB (Notes 5, 7) (Notes 5, 7) Input Offset Capacitance Adjustment Range CoffRANGE − ±8.0 − pF Input Offset Capacitance Adjustment Resolution CoffRESO − 8 − bit Cin Offset Drift CinDRIFT Minimum gain setting − − ±8 LSB (Note 5) Cin Detection Sensitivity CinSENSE Minimum gain setting 0.04 − 0.12 LSB/fF (Note 6) ICin Cin = Hi−Z − ±25 ±500 nA Cin Allowable Parasitic Input Capacitance CinSUB Cin against VSS − − 30 pF Cdrv Drive Frequency fCDRV 100 143 186 kHz Cdrv Pin Leak Current ICDRV − ±25 ±500 nA nRST Minimum Pulse Width tNRST 1 − − ms Cin Pin Leak Current Power-on Reset Time Cdrv = Hi−Z (Notes 5, 7) tPOR − − 20 ms Power-on Reset Operation Condition: Hold Time tPOROP 10 − − ms (Note 5) Power-on Reset Operation Condition: Input Voltage VPOROP − − 0.1 V (Note 5) www.onsemi.com 2 LC717A00AR Table 3. ELECTRICAL CHARACTERISTICS (continued) (VSS = 0 V, VDD = 2.6 to 5.5 V, TA = −40 to +105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143 kHz. Not tested at low temperature before shipment.) Parameter Symbol Conditions Min Typ Max Unit Remarks Power-on Reset Operation Condition: Power Supply Rise Rate tVDD 0 V to VDD 1 − − V/ms (Note 5) Pin Input Voltage VIH High input 0.8 VDD − − V (Notes 5, 8) VIL Low input − − 0.2 VDD VOH High output (IOH = +3 mA) 0.8 VDD − − V (Note 9) VOL Low output (IOL = −3 mA) − − 0.2 VDD VOL I2C SDA Low output (IOL = −3 mA) − − 0.4 V Pin Output Voltage SDA Pin Output Voltage Pin Leak Current Current Consumption − − ±1 mA (Note 10) When stand-alone configuration and non-touch VDD = 2.8 V − 320 390 mA (Notes 5, 7) When stand-alone configuration and non-touch VDD = 5.5 V − 740 900 During Sleep process − − 1 mA (Note 7) ILEAK IDD ISTBY Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Design-guaranteed values (not tested before shipment). 6. Measurements conducted using the test mode in the LSI. 7. TA = +25_C. 8. Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN. 9. Apply to Cdrv, Pout0 to 7, SO, ERROR, INTOUT. 10. Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN. www.onsemi.com 3 LC717A00AR Table 4. I2C COMPATIBLE BUS TIMING CHARACTERISTICS (VSS = 0 V, VDD = 2.6 to 5.5 V, TA = −40 to +105°C, Not tested at low temperature before shipment.) Min Typ Max Unit SCL − − 400 kHz tHD;STA SCL, SDA 0.6 − − ms SCL Clock Low Period tLOW SCL 1.3 − − ms SCL Clock High Period tHIGH SCL 0.6 − − ms Repeated START Condition Setup Time tSU;STA SCL, SDA 0.6 − − ms Data Hold Time tHD;DAT SCL, SDA 0 − 0.9 ms Data Setup Time tSU;DAT SCL, SDA 100 − − ns (Note 11) tr / tf SCL, SDA − − 300 ns (Note 11) tSU;STO SCL, SDA 0.6 − − ms tBUF SCL, SDA 1.3 − − ms Parameter SCL Clock Frequency START Condition Hold Time SDA, SCL Rise/Fall Time STOP Condition Setup Time STOP-to-START Bus Release Time Symbol Pin Name fSCL Conditions Remarks (Note 11) (Note 11) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 11. Design-guaranteed values (not tested before shipment). Table 5. SPI BUS TIMING CHARACTERISTICS (VSS = 0 V, VDD = 2.6 to 5.5 V, TA = −40 to +105°C, Not tested at low temperature before shipment.) Parameter SCK Clock Frequency Symbol Pin Name Min Typ Max Unit fSCK SCK Conditions − − 5 MHz Remarks SCK Clock Low Time tLOW SCK 90 − − ns (Note 12) SCK Clock High Time tHIGH SCK 90 − − ns (Note 12) Input Signal Rise/Fall Time tr / tf nCS, SCK, SI − − 300 ns (Note 12) nCS Setup Time tSU;NCS nCS, SCK 90 − − ns (Note 12) SCK Clock Setup Time tSU;SCK nCS, SCK 90 − − ns (Note 12) Data Setup Time tSU;SI SCK, SI 20 − − ns (Note 12) Data Hold Time tHD;SI SCK, SI 30 − − ns (Note 12) nCS Hold Time tHD;NCS nCS, SCK 90 − − ns (Note 12) SCK Clock Hold Time tHD;SCK nCS, SCK 90 − − ns (Note 12) nCS Standby Pulse Width tCPH nCS 90 − − ns (Note 12) Output High Impedance Time from nCS tCHZ nCS, SO − − 80 ns (Note 12) Output Data Determination Time Output Data Hold Time Output Low Impedance Time from SCK Clock tv SCK, SO − − 80 ns (Note 12) tHD;SO SCK, SO 0 − − ns (Note 12) tCLZ SCK, SO 0 − − ns (Note 12) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 12. Design-guaranteed values (not tested before shipment). www.onsemi.com 4 LC717A00AR Power-On Reset (POR) Since INTOUT pin changes from “High” to “Low” at the same time as the released of power-on reset state, it is possible to verify the tPOR externally. During power-on reset state, Cin, Cref and Pout are unknown. When power is turned on, power-on reset is enabled inside the LSI and its state is released after a certain power-on reset time, tPOR. Power-on reset operation condition: Power supply rise rate tVDD must be at least 1 V/ms. VDD tVDD VPOROP tPOR tPOR tPOROP POR (LSI Internal Signal) RESET UNKNOWN RELEASE INTOUT VALID Cin, Cref, Pout RESET UNKNOWN VALID UNKNOWN RELEASE UNKNOWN Figure 1. I2C Compatible Bus Data Timing 90% SDA 90% 10% 10% tHD;DAT tLOW tSU;DAT 90% 90% tSU;STA 10% 10% tHD;STA 10% tHIGH tr 10% tHD;STA 90% 90% SCL 90% 10% 90% 90% tBUF 10% tSU;STO 90% 10% tf START condition Repeated START condition STOP condition START condition Figure 2. I2C Compatible Bus Communication Formats • Write format (data can be written into sequentially incremented addresses) START Slave Address Write=L ACK Register Address (N) ACK Slave Data written to Register Address (N) Slave ACK Data written to Register Address (N+1) ACK Slave STOP Slave Figure 3. • Read format (data can be read from sequentially incremented addresses) START Slave Address Write=L ACK Register Address (N) ACK Slave RESTART Slave Address Read=H ACK Slave Slave Data read from Register Address (N) ACK Data read from Register Address (N+1) Master Figure 4. www.onsemi.com 5 ACK Data read from Register Address (N+2) NACK STOP Master Master LC717A00AR I2C Compatible Bus Slave Address Selection of two kinds of addresses is possible through the SA terminal. Table 6. SA Pin Input 7-bit Slave Address Binary Notation 8-bit Slave Address Low 0x16 00101100b (Write) 0x2C 00101101b (Read) 0x2D 00101110b (Write) 0x2E 00101111b (Read) 0x2F High 0x17 SPI Data Timing (SPI Mode 0 / Mode 3) tCPH nCS tSU;SCK tSU;NCS tHIGH tr tLOW tf tHD;NCS tHD;SCK SCK tSU;SI tHD;SI VALID SI tCLZ SO tHD;SO tCHZ VALID Hi−Z tV Figure 5. SPI Communication Formats (Example of Mode 0) • Write format (data can be written into sequentially incremented addresses while holding nCS = L) nCS SCK Write=L SI 7 6 5 4 3 2 1 0 Register Address(N) SO 7 6 5 4 3 2 1 0 Data written to Register Address(N) Hi−Z 7 6 5 4 3 2 1 0 Data written to Register Address(N+1) Figure 6. • Read format (data can be read from sequentially incremented addresses while holding nCS = L) nCS SCK Read=H SI 7 6 5 4 3 2 1 0 Register Address(N) SO Hi−Z 7 6 5 4 3 2 1 0 Data read from Register Address(N) Figure 7. www.onsemi.com 6 7 6 5 4 3 2 1 0 Data read from Register Address(N+1) 7 LC717A00AR Block Diagram Pout0 Cref Pout1 Cin0 Pout2 Cin1 Pout3 + Cin2 + 1st AMP Cin3 MUX − 2nd AMP A/D CONVERTER − Pout4 Pout5 Cin4 Pout6 Cin5 Pout7 Cin6 Cdrv Cin7 ERROR CONTROL LOGIC nCS SCL/SCK INTOUT nRST GAIN I 2 C/SPI SDA/SI SA/SO OSCILLATOR POR V DD V SS Figure 8. Block Diagram LC717A00AR is capacitance-digital-converter LSI capable of detecting changes in capacitance in the femto Farad order. It consists of an oscillation circuit that generates the system clock, a power-on reset circuit that resets the system when the power is turned on, a multiplexer that selects the input channels, a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude values, a A/D converter that converts the analog-amplitude values into digital data, and a control logic that controls the entire chip. Also, it has an I2C compatible bus or SPI that enables serial communication with external devices as necessary. www.onsemi.com 7 LC717A00AR 21 Cdrv 20 ERROR 19 Cref 18 Pout7 17 Pout6 16 Pout5 15 Pout4 Pin Assignment 26 SA/SO Cin6 9 27 nCS Cin5 8 28 nRST Cin0 1 Cin7 10 Cin1 2 25 SDA/SI Cin2 3 Pout0 11 Cin3 4 24 SCL/SCK 5 Pout1 12 VDD 23 GAIN 6 Pout2 13 VSS 22 INTOUT Cin4 7 Pout3 14 Figure 9. Pin Assignment Table 7. PIN ASSIGNMENT Pin No. Pin Name Pin No. Pin Name 1 Cin0 15 Pout4 2 Cin1 16 Pout5 3 Cin2 17 Pout6 4 Cin3 18 Pout7 5 VDD 19 Cref 6 VSS 20 ERROR 7 Cin4 21 Cdrv 8 Cin5 22 INTOUT 9 Cin6 23 GAIN 10 Cin7 24 SCL/SCK 11 Pout0 25 SDA/SI 12 Pout1 26 SA/SO 13 Pout2 27 nCS 14 Pout3 28 nRST www.onsemi.com 8 LC717A00AR Table 8. PIN FUNCTION Pin Name I/O Pin Functions Cin0 I/O Capacitance sensor input Cin1 I/O Capacitance sensor input Cin2 I/O Capacitance sensor input Cin3 I/O Capacitance sensor input Cin4 I/O Capacitance sensor input Cin5 I/O Capacitance sensor input Cin6 I/O Capacitance sensor input Cin7 I/O Capacitance sensor input Cref I/O Reference capacitance input Pout0 O Cin0 judgment result output Pout1 O Cin1 judgment result output Pout2 O Cin2 judgment result output Pout3 O Cin3 judgment result output Pout4 O Cin4 judgment result output Pout5 O Cin5 judgment result output Pout6 O Cin6 judgment result output Pout7 O Cin7 judgment result output ERROR O Error occurrence status output Cdrv O Output for capacitance sensors drive INTOUT O Interrupt output SCL/SCK I Clock input (I2C) / Clock input (SPI) GAIN I Selection pin of the initial value of gain of the 2nd-amplifier Pin Type V DD AMP R V SS Buffer V DD Buffer V SS V DD R nCS I Interface selection / Chip select inverting input (SPI) nRST I External reset signal inverting input SDA/SI I/O Data input and output (I2C) / Data input (SPI) V SS V DD R V SS www.onsemi.com 9 LC717A00AR Table 8. PIN FUNCTION (continued) Pin Name I/O Pin Functions Pin Type SA/SO I/O Slave address selection (I2C) / Data output (SPI) V DD R V SS VDD Power supply (2.6 V to 5.5 V) (Note 13) VSS Ground (Earth) (Notes 13, 14) Buffer 13. Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended. In this case, the small-valued capacitor should be at least 0.1 mF, and is mounted near the LSI. 14. When VSS terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded. Details of Pin Functions However, if the difference between the parasitic capacitance of each Cin pin is extremely large, it may not detect capacitance change in each Cin pin correctly. Cin0 to Cin7 These are the capacitance-sensor-input pins. These pins are used by connecting them to the touch switch pattern. Cin and the Cdrv wire patterns should be close to each other. By doing so, Cdrv and Cin patterns are capacitively coupled. Therefore, LSI can detect capacitance change near each pattern as 8-bit digital data. However, if the shape of each pattern or the capacitively coupled value of Cdrv is not appropriate, it may not be able to detect the capacitance change correctly. In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude values. Cin0 to Cin7 are connected to the inverting input of the 1st amplifier in the LSI. During measurement process, channels other than the one being measured are all in “Low” condition. Leave the unused terminals open. Pout0 to Pout7 These are the detection-result-output pins. The capacitance detection results of Cin0 to Cin7 are compared with the threshold of the LSI. The pin outputs a “High” or a “Low” depending on the result. ERROR It is the error-occurrence-status-output pin. It outputs “Low” during normal operation. If there is a calibration error or a system error, it outputs “High” to indicate that an error occurred. Cdrv It is the output pin for capacitance sensors drive. It outputs the pulse voltage which is needed to detect capacitance at Cin0 to Cin7. Cdrv and Cin wire patterns should be close to each other so that they are capacitively coupled. Cref It is the reference-capacitance-input pin. It is used by connecting to the wire pattern like Cin pins or is used by connecting any capacitance between this pin and Cdrv pin. In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude values. Cref is connected to the non-inverting input of the 1st amplifier in the LSI. Due to the parasitic capacitance generated in the wire connections of Cin pins and their patterns, as well as the one generated between the wire patterns of Cin and Cdrv pins, Cref may not detect capacitance change of each Cin pin accurately. In this case, connect an appropriate capacitance between Cref and Cdrv to detect capacitance change accurately. INTOUT It is the interrupt-output pin. It outputs “High” when a measurement process is completed. Connect to a main microcomputer if necessary, and use as interrupt signal. Leave the terminal open if not in used. SCL/SCK Clock input (I2C)/Clock input (SPI). It is the clock input pin of the I2C compatible bus or the SPI depending on the mode of operation. If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a communication terminal on board is still recommended. www.onsemi.com 10 LC717A00AR nRST It is the external-reset-signal-inverting-input pin. When nRST pin is “Low”, LSI is in the reset state. Each pin (Cin0 to 7, Cref, Pout0 to 7, ERROR) is “Hi−Z” during reset state. GAIN In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude values. It is the selection pin of the initial value of gain of the 2nd amplifier. Even if this LSI is used alone, gain setting can still be selected through this terminal. At initialization of the LSI, it is set to 7-times higher than the minimum setting when GAIN pin is “Low”, and is set to 14-times higher than the minimum setting when GAIN pin is “High”. SDA/SI Data input and output (I2C)/Data input (SPI). It is the data input and output pin of the I2C compatible bus or the data input pin of the SPI depending on the mode of operation. If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a communication terminal on board is still recommended. nCS Interface selection/Chip-select-inverting input (SPI). Selection of I2C compatible bus mode or SPI mode is through this terminal. After initialization, the LSI is automatically in I2C compatible bus mode. To continually use I2C compatible bus mode, fix nCS pin to “High”. To switch to SPI mode after LSI initialization, change the nCS input “High” → “Low”. The nCS pin is used as the chip-select-inverting input pin of SPI, and SPI mode is kept until LSI is again initialized. If interface is not to be used, fix the pin to “High”. SA/SO Slave address selection (I2C)/Data output (SPI). It is the slave address selection pin of the I2C compatible bus or the data output pin of the SPI depending on the mode of operation. If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a communication terminal on board is still recommended. Table 9. ORDERING INFORMATION Device Package Shipping (Qty / Packing)† LC717A00AR−NH VCT28 3.5 × 3.5 (Pb-Free / Halogen Free) 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. I2C Bus is a trademark of Philips Corporation. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS VCT28 3.5x3.5 CASE 601AE ISSUE A TOP VIEW DATE 21 NOV 2013 SIDE VIEW BOTTOM VIEW 3.5±0.08 (0.09) (0.125) (C0.09) 0.4±0.05 0.15 28 3.5±0.08 ×4 LASER MARKED INDEX 2 0.19±0.05 0.05 S 0.05 S (0.035) 0.8±0.05 SIDE VIEW 1 0.4 (0.55) SOLDERING FOOTPRINT* 3.20 (Unit: mm) 3.20 GENERIC MARKING DIAGRAM* XXXXXXXX YMDDD 0.20 0.70 XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 0.19 0.40 NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: 98AON78901E DESCRIPTION: VCT28 3.5X3.5 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 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