LC717A30UJ-AH

LC717A30UJ Capacitance‐Digital‐Converter LSI for Electrostatic Capacitive Touch Sensors The LC717A30UJ is a high performance, low cost, and highly usable capacitance converter for electrostatic capacitive touch and proximity sensors. 8 capacitance-sensing input channels ideal for use in any end products that needs an array of switches. The LC717A30UJ facilitates a short system development time through its automatic calibration function and minimal external components. The detection result (ON/OFF) for each sensor is read out by the serial interface (I2C or SPI). Features • • • • • • • • • SSOP30 (225 mil) CASE 565AZ Differential Capacitive Detection Using Mutual Capacitance Operates with Small to Large Capacitance Sensor Input Pads Capacitance Detection Down to Femto-Farad Level Measurement Time 16 ms for 8 Sensors Minimal External Components Selectable Interface: I2C or SPI Current Consumption: 0.8 mA (VDD = 5.5 V) Supply Voltage: 2.6 V to 5.5 V AEC−Q100 Qualified and PPAP Capable MARKING DIAGRAM XXXXXXXXXX YMDDD Typical Applications • • • • • www.onsemi.com Automotive: Smart Key, Control Switches, Car Audio, Proximity Consumer: Home Appliance, White Goods, Induction Cooking Industrial: Security Lock Computing: PC Peripherals, Audio Visual Equipment Lighting: Remote Control Switches XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. Cref I2C/SPI Main Microcomputer GPIO EXTINT VDD or VSS Cref CrefAdd CdrvBar nCS SCL/SCK CMAdd0 SDA/SI CMAdd4 SA0/SO Cin0 Cin1 nRST Cin6 INOUT Cin7 IFSEL SW1 SW2 SW7 SW8 Cdrv LC717A30UJ Figure 1. Application Schematic 1 © Semiconductor Components Industries, LLC, 2016 January, 2018 − Rev. 1 1 Publication Order Number: LC717A30UJ/D LC717A30UJ 8 small capacitance sensors channels and 4-wire SPI interface. 4 pF (open) Cref CrefAdd nCS SCL/SCK SDA/SI SA0/SO Main Microcomputer CdrvBar (open) CMAdd0 (open) CMAdd4 (open) GPIO EXTINT nRST INTOUT IFSEL Cin0 Cin1 Cin2 Cin3 SW1 (Small capacitance: e.g. 4 pF) SW2 (Small capacitance: e.g. 4 pF) SW3 (Small capacitance: e.g. 4 pF) SW4 (Small capacitance: e.g. 4 pF) Cin4 Cin5 Cin6 Cin7 SW5 (Small capacitance: e.g. 4 pF) SW6 (Small capacitance: e.g. 4 pF) SW7 (Small capacitance: e.g. 4 pF) SW8 (Small capacitance: e.g. 4 pF) Cdrv LC717A30UJ Figure 2. Application Schematic 2 8 Large capacitance sensors and I2C interface. 20 pF 16 pF VDD (open) Cref CrefAdd nCS SCL/SCK SDA/SI SA0/SO Main Microcomputer CdrvBar 16 pF CMAdd0 16 pF CMAdd4 nRST INTOUT GPIO EXTINT VDD IFSEL Cin0 Cin1 Cin2 SW1 (Big capacitance: e.g. 20 pF) SW2 (Big capacitance: e.g. 20 pF) Cin3 SW4 (Big capacitance: e.g. 20 pF) Cin4 Cin5 Cin6 Cin7 SW5 (Big capacitance: e.g. 20 pF) SW6 (Big capacitance: e.g. 20 pF) SW3 (Big capacitance: e.g. 20 pF) SW7 (Big capacitance: e.g. 20 pF) SW8 (Big capacitance: e.g. 20 pF) Cdrv LC717A30UJ Figure 3. Application Schematic 3 www.onsemi.com 2 LC717A30UJ BLOCK DIAGRAM The LC717A30UJ is a capacitance-digital converter LSI that can detect capacitance at the femto farad level. It consists a multiplexer that selects the input channels, a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude values, an A/D converter, a system clock, a power-on reset circuit, control logic and interface, I2C bus or SPI. VDD VSS Cin0 Cin1 Cin2 Tout0 Cin3 Cin4 MUX − Cin5 Cin6 + 1st AMP − + 2nd AMP A/D CONVERTER Tout1 Tout2 Tout3 Tout4 Cin7 CMAdd0 CMAdd4 CdrvBar Cdrv CONTROL LOGIC INTOUT Cref CrefAdd nRST MUX POWER ON RESET nCS OSCILLATOR SCL/SCK I2C/SPI INTERFACE SDA/SI SA0/SO IFSEL Figure 4. Simplified Block Diagram www.onsemi.com 3 LC717A30UJ Tout4 Tout3 Cin1 Cin0 NC nRST nCS SA0/SO SDA/SI SCL/SCK IFSEL INOUT Cdrv CrefAdd CdrvBar PIN ASSIGNMENT 30 16 LC717A30UJ (SSOP30 (225mil)) 15 VDD VSS NC Cin2 Cin3 Tout0 Tout1 Cin4 Cin5 CMAdd4 CMAdd0 Cin6 Cin7 Tout2 Cref 1 Figure 5. Pin Assignment (Top View) Table 1. PIN ASSIGNMENT Pin No. Pin Name I/O 1 VDD Power Power supply (+2.6 V to +5.5 V) (Note 1) 2 VSS Power Ground (Notes 1, 2) 3 Non Connect − Connect to Ground 27 Cin0 I/O 28 Cin1 I/O 4 Cin2 I/O 5 Cin3 I/O 8 Cin4 I/O 9 Cin5 I/O 12 Cin6 I/O 13 Cin7 I/O 6 Tout0 O Test pin, must remain open Description Sensor inputs. Cin0 to Cin7 are connected to the inverting input of the 1st amplifier through the multiplexer. All unused input pins must remain open. Cdrv and Cin printed circuit board patterns should be close to each other as they are capacitively coupled. 7 Tout1 O Test pin, must remain open 10 CMAdd4 I/O Offset capacitance input pin for the sensor inputs 4 to 7. When using large sensor pads with high capacitance, additional capacitance is added between CMAdd4 and CdrvBar. See Figure 3. Remain open if not in use. 11 CMAdd0 I/O Offset capacitance input pin for the sensor inputs 0 to 3. When using large sensor pads with high capacitance, additional capacitance is added between CMAdd4 and CdrvBar. See Figure 3. Remain open if not in use. 14 Tout2 O Test pin, must remain open 15 Cref I/O 17 CrefAdd I/O Reference capacitance input pins. See Figures 2 and 3. When using large sensor pads with high capacitance, additional capacitance maybe added for Cref. See Figure 3. Remain open if not in use. www.onsemi.com 4 LC717A30UJ Table 1. PIN ASSIGNMENT (continued) Pin No. Pin Name I/O Description 16 CdrvBar O Capacitance sensors drive signal inversion output. When using large sensor pads with high capacitance, additional capacitance is added between CMAdd0 and CMAdd4 and CdrvBar. See Figure 3. Remain open if not in use. 18 Cdrv O Capacitance sensors drive output. Cdrv and Cin printed circuit board patterns should be close to each other as they are capacitively coupled. 19 INTOUT O Interrupt output pin. (Active high) Remain open if not in use 20 IFSEL I Interface Select. IFSEL = “Low” (VSS): SPI mode IFSEL = “High” (VDD): I2C mode 21 SCL/SCK I I2C = SCL clock input SPI = SCK clock input 22 SDA/SI I/O I2C = SDA data input/output SPI = SI data input 23 SA0/SO I/O I2C = SA0 slave address selection input SPI = SO data output 24 nCS I I2C = “High” (VDD) SPI = nCS chip select inversion input 25 nRST I Reset signal inversion input pin. nRST = “Low” (VSS), in reset state Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd, CdrvBar and Tout0 to Tout4 are “Hi−Z” 26 Non Connect − Connect to Ground 29 Tout3 O Test pin, must remain open 30 Tout4 O Test pin, must remain open 1. For noise de-coupling place a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS. The small-valued capacitor, at least 0.1 mF, should be mounted near the LSI. 2. When VSS terminal is not grounded, in battery-powered mobile equipment, detection sensitivity may be degraded. Table 2. PIN FUNCTIONS Pin No. Pin Name I/O 1 VDD Power Power supply (+2.6 V to +5.5 V) 2 VSS Power Ground 27 Cin0 I/O Capacitance sensor input 0 28 Cin1 I/O Capacitance sensor input 1 4 Cin2 I/O Capacitance sensor input 2 5 Cin3 I/O Capacitance sensor input 3 8 Cin4 I/O Capacitance sensor input 4 9 Cin5 I/O Capacitance sensor input 5 12 Cin6 I/O Capacitance sensor input 6 13 Cin7 I/O Capacitance sensor input 7 10 CMAdd4 I/O Additional offset capacitance input pin for the sensor inputs 4 to 7 11 CMAdd0 I/O Additional offset capacitance input pin for the sensor inputs 0 to 3 15 Cref I/O Reference capacitance input 17 CrefAdd I/O Additional Reference capacitance input Pin Functions www.onsemi.com 5 Pin Type VDD AMP R VSS Buffer LC717A30UJ Table 2. PIN FUNCTIONS (continued) Pin No. Pin Name I/O Pin Functions 6 Tout0 O Output for tests 7 Tout1 O Output for tests 14 Tout2 O Output for tests 29 Tout3 O Output for tests 30 Tout4 O Output for tests 16 CdrvBar O Capacitance sensors drive signal inversion output 18 Cdrv O Capacitance sensors drive output 19 INTOUT O Interrupt output Pin Type VDD Buffer VSS VDD Buffer VSS 20 IFSEL I Switching control input of the serial data communication interface 21 SCL/SCK I SCL clock input (I2C) I SCK clock input (SPI) 24 nCS I nCS chip select inversion input (SPI) 25 nRST I External reset signal inversion input 22 SDA/SI I/O SDA data input/output (I2C) VDD R VSS VDD R I Schmitt SI data input (SPI) Schmitt O.D. VSS 23 SA0/SO I SA0 slave address selection input (I2C) VDD R O Schmitt SO data output (SPI) VSS www.onsemi.com 6 Buffer LC717A30UJ ABSOLUTE MAXIMUM RATINGS (VSS = 0 V, TA = +25°C) Symbol Parameter Value Unit −0.3 to +6.5 V Input Voltage Range (Note 3) −0.3 to VDD+0.3 V Output Voltage Range (Note 4) −0.3 to VDD+0.3 V VDD Supply Voltage Range VIN VOUT IOP Peak Output Current Range (Notes 4, 5) −8.0 to +8.0 mA IOA Total Outputs Current Range (Note 6) −40 to +40 mA Pdmax Maximum Power Dissipation (Note 7) 160 mW Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. Apply to Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd ,SCL/SCK ,SDA/SI ,SA0, nCS, nRST, IFSEL. 4. Apply to Cdrv, CdrvBar, SDA, SO, INTOUT, Tout0 to Tout4. 5. Total value with duty cycle under 25%. 6. Limited to one pin, with duty cycle under 50%. 7. TA = 105°C, Single-layer glass epoxy board (76.1 × 114.3 × 1.6 mm). RECOMMENDED OPERATING CONDITIONS (VSS = 0 V) Parameter Min Max Unit 2.6 5.5 V Input High-level Voltage Range (Note 9) 0.8 VDD VDD V VIL Input Low-level Voltage Range (Note 9) 0 0.2 VDD V TA Ambient Temperature Range −40 105 °C Symbol VDD Operating Supply Voltage Range (Note 8) VIH Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 8. For noise de-coupling place a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS. The small-valued capacitor, at least 0.1 mF, should be mounted near the LSI. In addition, it is recommended that the power supply ripple + noise is less than ±40 mV. 9. Apply to SCL/SCK ,SDA/SI ,SA0, nCS, nRST, IFSEL. ELECTRICAL CHARACTERISTICS (VDD = 2.6 to 5.5 V, VSS = 0 V, TA = −40 to + 105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 121 kHz.) Symbol Parameter Condition Min Typ Max Unit IO = −1.5 mA, VDD = 2.6 to 3.6 V 0.8 VDD − − V IO = −3.0 mA, VDD = 3.6 to 5.5 V 0.8 VDD − − V IO = +1.5 mA, VDD = 2.6 to 3.6 V − − 0.2 VDD V IO = +3.0 mA, VDD = 3.6 to 5.5 V − − 0.2 VDD V COMMON VOH1 Output High-level Voltage (Note 10) VOH2 VOL1 Output Low-level Voltage (Note 10) VOL2 VOL3 Tout0 to Tout4 pins Output Low-level Voltage IO = +1.5 mA − − 0.2 VDD V VOL4 SDA pin Output Low-level Voltage IO = +3.0 mA − − 0.4 V IIH Input High-level Current (Note 11) VI = VDD − − 1.0 mA IIL Input Low-level Current (Note 11) VI = VSS −1.0 − − mA IOFF Output Off Leakage Current (Note 12) VI = VDD or VI = VSS −1.0 − 1.0 mA IDD1 Current Consumption Initial setting, Long interval operation, Sensor pins are open (Note 13), VDD = 5.5 V − 0.8 2.2 mA IDD2 Initial setting, Short interval operation, Sensor pins are open (Note 13), VDD = 5.5 V − 3.25 6.5 mA ISTBY Sleep mode (Sleep period) Sensor pins are open (Note 13) − 0.1 70 mA www.onsemi.com 7 LC717A30UJ ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.6 to 5.5 V, VSS = 0 V, TA = −40 to + 105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 121 kHz.) Symbol Parameter Condition Min Typ Max Unit 0.0476 0.068 0.0884 LSB/fF − ±25 ±500 nA 84.85 121.21 157.57 kHz CAPACITANCE SENSOR FUNCTION CinSENSE ICin fCDRV Cin Detection Sensitivity Measurements conducted using the test mode in the LSI, Minimum gain setting Sensor Pin Leakage Current (Note 14) VI = VDD or VI = VSS Cdrv Drive Frequency With 121 kHz setting POWER-ON RESET FUNCTION tNRST nRST Minimum Pulse Width 1.0 − − ms tPOR Power-on Reset Time − − 20 ms tPOROP Power-on Reset Operation Condition: Hold Time 10 − − ms VPOROP Power-on Reset Operation Condition: Input Voltage − − 0.1 V tVDD Power-on Reset Operation Condition: Power Supply Rise Rate 0 V to VDD 1.0 − − V/ms VDD = 2.6 to 4.5 V, Long interval mode (Long interval time is set to 101 ms) 35 101 145 ms VDD = 4.5 to 5.5 V, Long interval mode (Long interval time is set to 101 ms) 40 101 125 ms VDD = 2.6 to 4.5 V, Short interval mode (Short interval time is set to 5 ms) 1.7 5 7.3 ms VDD = 4.5 to 5.5 V, Short interval mode (Short interval time is set to 5 ms) 1.9 5 6.3 ms INTERVAL OPERATION TIMING TLIVAL1 Long Interval Time TLIVAL2 TSIVAL1 Short Interval Time TSIVAL2 I2C COMPATIBLE BUS INTERFACE TIMING SCL Clock Frequency SCL − − 400 kHz START Condition Hold Time SCL, SDA 0.6 − − ms tLOW SCL Clock Low Period SCL 1.3 − − ms tHIGH SCL Clock High Period SCL 0.6 − − ms tSU; STA Repeated START Condition Setup Time SCL, SDA 0.6 − − ms tHD; DAT Data Hold Time SCL, SDA 0 − 0.9 ms tSU; DAT Data Setup Time SCL, SDA 0.5 − − ms SDA, SCL Rise/Fall Time SCL, SDA − − 0.3 ms STOP Condition Setup Time SCL, SDA 0.6 − − ms STOP-to-START Bus Release Time SCL, SDA 2.5 − − ms fSCL tHD; STA tr/tf tSU; STO tBUF SPI INTERFACE TIMING fSCK SCK Clock Frequency SCK − − 5.0 MHz tLOW SCK Clock Low Time SCK 100 − − ns tHIGH SCK Clock High Time SCK 100 − − ns Input Signal Rise/Fall Time nCS, SCK, SI − − 300 ns tSU; NCS tr/tf nCS Setup Time nCS, SCK 200 − − ns tSU; SCK SCK Clock Setup Time nCS, SCK 100 − − ns tSU; SI Data Setup Time SCK, SI 100 − − ns tHD; SI Data Hold Time SCK, SI 100 − − ns www.onsemi.com 8 LC717A30UJ ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.6 to 5.5 V, VSS = 0 V, TA = −40 to + 105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 121 kHz.) Symbol Parameter Condition Min Typ Max Unit SPI INTERFACE TIMING tHD; NCS nCS Hold Time nCS, SCK 200 − − ns tHD;SCK SCK Clock Hold Time nCS, SCK 700 − − ns tCPH nCS Standby Pulse Width nCS 300 − − ns tCHZ Output High Impedance Time from nCS nCS, SO − − 100 ns Output Data Determination Time SCK, SO − − 100 ns Output Data Hold Time SCK, SO 0 − − ns Output Low Impedance Time from SCK Clock SCK, SO 100 − − ns tV tHD; SO tCLZ Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 10. Apply to Cdrv, CdrvBar, SO, INTOUT. 11. Apply to SCL/SCK, SDA/SI, SA0, nCS, nRST, IFSEL. 12. Apply to Cdrv, CdrvBar, SDA, SO. 13. Sensor pins (Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd) are open condition. 14. Apply to Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd. Table 3. ORDERING INFORMATION Device Package Shipping (Qty / Packing)† LC717A30UJ−AH SSOP30 (225 mil) (Pb-Free / Halogen Free) 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 9 LC717A30UJ FUNCTIONAL DESCRIPTION Power-on Reset (POR) Since INTOUT pin changes from “High” to “Low” at the same time as reset release, it is possible to verify the timing of release of reset externally. During power-on reset, Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd, and CdrvBar are unknown. When power is turned on, power-on reset is enabled, it is released after power-on reset time, tPOR. Power-on reset operation condition; Power supply rise rate tVDD must be at least 1.0 V/ms. 100% VDD tVDD VPOROP tPOR 0% POR (LSI Internal Signal) Reset tPOROP Unknown Release INTOUT VALID Cin0 to 7, CMAdd0, CMAdd4, Cref, CrefAdd, CdrvBar tPOR Release Unknown Unknown VALID Unknown Reset Figure 6. Power-on Sequence by the Power-on Reset External Reset (nRST) Reset State nRST = “Low”. Pins Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd and CdrvBar, are “Hi-Z” during reset state. The reset state is released after tPOR. Since INTOUT pin changes from “High” to “Low” at the same time as the released of reset, it is possible to verify the timing of release of reset externally. 100% VDD tPOR 0% nRST tPOR Reset Reset tNRST tNRST POR (LSI Internal signal) Reset Release Reset INTOUT Cin0 to 7, CMAdd0, CMAdd4, Cref, CrefAdd, CdrvBar VALID Hi-Z VALID Unknown Hi-Z Unknown Figure 7. Power-on Sequence by the External Reset www.onsemi.com 10 Release LC717A30UJ I2C Data Timing 80% SDA 20% tHD;DAT tLOW tSU;DAT tSU;STA tHD;STA tSU;STO tBUF 80% SCL 20% tHD;STA tHIGH tr tf START condition Repeated START condition STOP condition START condition Figure 8. I2C Data Timing I2C Communication Formats Write Format When using the Write format of I2C the data can be written into sequentially incremented addresses. START Slave Address Write=L ACK Register Address (N) Slave ACK Data written to Register Address (N) Slave ACK Data written to Register Address (N+1) ACK STOP Slave Slave Figure 9. I2C Write Format Read Format When using the Read format of I2C the data can be read from sequentially incremented addresses. START Slave Address Write=L ACK Register Address (N) Slave RESTART Slave Address Read=H ACK ACK Slave Data read from Register Address (N) Slave ACK Data read from Register Address (N+1) Master ACK Data read from Register Address (N+2) NACK STOP Master Master Figure 10. I2C Read Format I2C Slave Address SA0 pin is used to select the slave address Table 4. I2C SLAVE ADDRESS SA0 Pin Input 7 bit Slave Address Binary Notation 8 bit Slave Address Low 0x16 00101100b (Write) 0x2C 00101101b (Read) 0x2D 00101110b (Write) 0x2E 00101111b (Read) 0x2F High 0x17 www.onsemi.com 11 LC717A30UJ SPI Data Timing (Mode 0/Mode 3) tCPH 50% nCS tSU;SCK tHIGH tf tr tLOW tSU;SI tHD;SCK 80% 50% 20% tSU;NCS SCK tHD;SI 50% VALID SI tCLZ SO tHD;NCS tHD;SO tCHZ 50% VALID Hi−Z Hi−Z tV Figure 11. SPI Data Timing SPI Write Format (Example of Mode 0) When using the SPI Write format the data can be written into sequentially incremented addresses with preserving nCS = “L”. nCS SCK Write=L SI SO 7 6 5 4 3 2 1 0 Register Address(N) 7 6 5 4 3 2 1 0 Data written to Register Address(N) Hi-Z 7 6 5 4 3 2 1 0 Data written to Register Address(N+1) Figure 12. SPI Write Format SPI Read Format When using the SPI Read format the data can be read from sequentially incremented addresses with preserving nCS = “L”. nCS SCK Read=H SI 7 6 5 4 3 2 1 0 Register Address(N) SO Hi-Z 7 6 5 4 3 2 1 0 Data read from Register Address(N) Figure 13. SPI Read Format I2C Bus is a trademark of Philips Corporation. www.onsemi.com 12 7 6 5 4 3 2 1 0 Data read from Register Address(N+1) 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SSOP30 (225 mil) CASE 565AZ ISSUE A DATE 25 OCT 2013 1.00 SOLDERING FOOTPRINT* (Unit: mm) 5.80 GENERIC MARKING DIAGRAM* 0.50 0.32 NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON80824E SSOP30 (225 MIL) XXXXXXXXXX YMDDD XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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