LC72121MA-AH

Ordering number : ENA2009 LC72121MA CMOS IC PLL Frequency Synthesizers for Electronic Tuning http://onsemi.com Overview The LC72121MA are high input sensitivity (20mVrms at 130MHz) PLL frequency synthesizers for 3V systems. These ICs are serial data (CCB) compatible with the LC72131K/KMA, and feature the improved input sensitivity and lower spurious radiation (provided by a redesigned ground system) required in high-performance AM/FM tuners. Features • High-speed programmable divider • FMIN: 10 to 160MHz ·············· Pulse swallower technique (With built-in divide-by-2 prescaler) • AMIN: 2 to 40MHz ················ Pulse swallower technique 0.5 to 10MHz ·············· Direct division technique • IF counter • IFIN: 0.4 to 15MHz ················ For AM and FM IF counting • Reference frequency • One of 12 reference frequencies can be selected (using a 4.5 or 7.2MHz crystal element) 1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50, and 100kHz • Phase comparator • Supports dead zone control. • Built-in unlocked state detection circuit • Built-in deadlock clear circuit • An MOS transistor for an active low-pass filter is built in. • I/O ports • Output-only ports: 4 pins • I/O ports: 2 pins • Supports the output of a clock time base signal. • Serial data I/O • Support CCB format communication with the system controller. • Operating ranges • Supply voltage: 2.7 to 3.6V • Operating temperature: -40 to +85°C • Package • MFP24SJ • CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format. • CCB is a registered trademark of Semiconductor Components Industries, LLC. Semiconductor Components Industries, LLC, 2013 June, 2013 30712HKPC 20120124-S00002 No.A2009-1/24 LC72121MA Specifications Absolute Maximum Ratings at Ta = 25°C, VSSd = VSSa = VSSX = 0V Parameter Symbol Conditions Maximum supply voltage VDD max VDD Maximum input voltage VIN1 max CE, CL, DI, AIN VIN2 max XIN, FMIN, AMIN, IFIN VIN3 max IO1, IO2 VO1 max DO VO2 max XOUT, PD VO3 max BO1 to BO4, IO1, IO2, AOUT Maximum output voltage Maximum output current Ratings Unit -0.3 to +7.0 V -0.3 to +7.0 V -0.3 to VDD+0.3 V -0.3 to +15 V -0.3 to +7.0 V -0.3 to VDD+0.3 V -0.3 to +15 V IO1 max DO, AOUT 0 to 6.0 mA IO2 max BO1 to BO4, IO1, IO2 0 to 10 mA Allowable power dissipation Pd max (Ta ≤ 85°C) 200 mW Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C Note 1: Power pins VDD and VSS: Insert a capacitor with a capacitance of 2,000pF or higher between these pins when using the IC. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ranges at Ta = -40 to +85°C, VSSd = VSSa = VSSX = 0V Parameter Symbol Pin Conditions Ratings min typ Unit max Supply voltage VDD VDD 2.7 3.6 V Input high-level voltage VIH1 CE, CL, DI 0.7VDD 6.5 V VIH2 IO1, IO2 0.7VDD 13 V Input low-level voltage VIL CE, CL, DI, IO1, IO2 0 0.3VDD V Output voltage VO1 DO 0 6.5 V Input frequency Guaranteed crystal oscillator VO2 BO1 to BO4, IO1, IO2, AOUT 0 13 V fIN1 XIN VIN1 1.0 8.0 MHz fIN2 FMIN VIN2 10 160 MHz fIN3 AMIN VIN3(SNS=1) 2.0 40 MHz fIN4 AMIN VIN4(SNS=0) 0.5 10 MHz fIN5 IFIN VIN5 0.4 15 MHz X’tal XIN, XOUT 4.0 8.0 MHz 200 800 mVrms 20 800 mVrms Note 2 frequency Input amplitude VIN1 XIN fIN1 VIN2-1 FMIN f=10 to 130MHz VIN2-2 FMIN f=130 to 160MHz 40 800 mVrms VIN3 AMIN fIN3(SNS=1) 40 800 mVrms VIN4 AMIN fIN4(SNS=0) 40 800 mVrms VIN5 IFIN fIN5(IFS=1) 40 800 mVrms VIN6 IFIN fIN5(IFS=0) 70 800 mVrms tSU DI, CL Data hold time tHD Clock low level time tCL Clock high level time Note 3 0.75 μs DI, CL Note 3 0.75 μs CL Note 3 0.75 μs tCH CL Note 3 0.75 μs CE wait time tEL CE, CL Note 3 0.75 μs CE setup time tES CE, CL Note 3 0.75 μs CE hold time tEH CE, CL Note 3 0.75 μs Data setup time Data latch change time tLC Data output time tDC DO, CL Differs depending Note 3 tDH DO, CE on the value of the pull-up resistor. 0.75 μs 0.35 μs Note 3 No.A2009-2/24 LC72121MA Note 2: Recommended crystal oscillator CI values: CI ≤ 120Ω (For a 4.5MHz crystal) CI ≤ 70Ω (For a 7.2MHz crystal) The characteristics of the oscillation circuit depends on the printed circuit board, circuit constants, and other factors. Therefore we recommend consulting with the anufacturer of the crystal for evaluation and reliability. Note 3: Refer to "Serial Data Timing". Electrical Characteristics in the Allowable Operating Ranges Parameter Internal feedback resistance Symbol Pin Conditions Ratings min typ Unit max Rf1 XIN 1.0 MΩ Rf2 FMIN 500 kΩ Rf3 AMIN 500 kΩ Rf4 IFIN 250 Internal pull-down resistance Rpd1 FMIN 100 Rpd2 AMIN 100 Hysteresis VHIS CE, CL, DI Output high-level voltage VOH PD IO=-1mA Output low-level voltage VOL1 PD IO=1mA 1.0 V VOL2 BO1 to BO4, IO1, IO2 IO=1mA 0.2 V IO=8mA 1.6 V V VOL3 Input high-level current Input low-level current DO kΩ 200 400 kΩ 200 400 kΩ 0.1VDD V VDD-1.0 V IO=1mA 0.2 IO=5mA 1.0 V VOL4 AOUT IO=1mA, AIN=1.3V 0.5 V IIH1 CE, CL, DI VI=6.5V 5.0 μA IIH2 IO1, IO2 VI=13V 5.0 μA IIH3 XIN VI=VDD 1.3 8 μA IIH4 FMIN, AMIN VI=VDD 2.5 15 μA 5.0 30 μA IIH5 IFIN VI=VDD IIH6 AIN VI=6.5V 200 nA IIL1 CE, CL, DI VI=0V 5.0 μA IIL2 IO1, IO2 VI=0V 5.0 μA IIL3 XIN VI=0V 1.3 8 μA IIL4 FMIN, AMIN VI=0V 2.5 15 μA 5.0 30 μA IIL5 IFIN VI=0V IIL6 AIN VI=0V 200 nA Output off leakage current IOFF1 BO1 to BO4, AOUT, IO1, IO2 VO=13V 5.0 μA IOFF2 DO VO=6.5V 5.0 μA High-level 3-state off leakage IOFFH PD VO=VDD 0.01 200 nA IOFFL PD VO=0V 0.01 200 nA current Low-level 3-state off leakage current Input capacitance CIN FMIN Supply current IDD1 VDD 6 fIN2=130MHz IDD2 VDD pF X’tal=7.2MHz 2.5 6 mA VIN2=20mVrms PLL block stopped (PLL INHIBIT mode) Crystal oscillator operating 0.3 mA (crystal frequency: 7.2 MHz) IDD3 VDD PLL block stopped. Crystal oscillator 10 μA stopped. No.A2009-3/24 LC72121MA Package Dimensions unit : mm (typ) 3419 13.0 0.45 8.0 6.0 24 1 2 1.0 0.15 0.4 0.1 (1.5) 1.9 MAX (1.0) SANYO : MFP24SJ(300mil) XOUT NC VSSa AOUT AIN PD VDD FMIN AMIN VSSd IO2 IFIN Pin Assignment 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 XIN VSSX CE DI CL DO BO1 BO2 BO3 BO4 IO1 NC LC72121MA Top view No.A2009-4/24 LC72121MA Block Diagram VSSX REFERENCE DIVIDER XIN PHASE DETECTOR CHARGE PUMP PD XOUT FMIN 1/2 UNLOCK DETECTOR SWALLOW COUNTER 1/16,1/17 4bits AIN AOUT VSSa 12bits PROGRAMMABLE DIVIDER AMIN CE DI CL CCB I/F DATA SHIFT REGISTER LATCH UNIVERSAL COUNTER IFIN DO VDD POWER ON RESET VSSd BO1 BO2 BO3 BO4 IO1 IO2 No.A2009-5/24 LC72121MA Pin Descriptions Pin name Pin No. XIN 1 XOUT 24 Type X’tal OSC Function Equivalent circuit • Crystal oscillator element connections (4.5 or 7.2 MHz) • FMIN is selected when DVS in the serial data is set to 1. • Input frequency: 10 to 160MHz FMIN 17 Local oscillator signal input • The signal is passed through an internal divide-by-two prescaler and then input to the swallow counter. • The divisor can be set to a value in the range 272 to 65535. Since the internal divide-by-two prescaler is used, the actual divisor will be twice the set value. • AMIN is selected when DVS in the serial data is set to 0. • When SNS in the serial data is set to 1: • Input frequency: 2 to 40MHz • The signal is input to the swallow counter directly. AMIN 16 Local oscillator signal input • The divisor can be set to a value in the range 272 to 65535. The set value becomes the actual divisor. • When SNS in the serial data is set to 0: • Input frequency: 0.5 to 10MHz • The signal is input to a 12-bit programmable divider directly. • The divisor can be set to a value in the range 4 to 4095. The set value becomes the actual divisor. CE 3 Chip enable DI 4 Input data CL 5 Clock DO 6 Output data VDD 18 Power supply VSSX 2 Ground VSSd 15 BO1 7 BO2 8 BO3 9 BO4 10 Ground • This pin must be set high to enable serial data input (DI) or serial data output (DO). S • Input for serial data transferred from the controller S • Clock used for data synchronization for serial data input (DI) and S serial data output (DO). • Output for serial data transmitted to the controller. The content of the data transmitted is determined by DOC0 through DOC2. • LC72121MA power supply (VDD 2.7 to 3.6V) • The power on reset circuit operates when power is first applied. • Ground for the crystal oscillator circuit • Ground for the LC72121MA digital systems other than those that use VSSa or VSSX. • Output-only ports - • The output state is determined by BO1 through BO4 in the serial data. When the data value is 0: The output state will be the open circuit Output port state. When the data value is 1: The output state will be a low level. • A time base signal (8Hz) is output from BO1 when TBC in the serial data is set to 1. • Shared function I/O ports • The pin function is determined by IOC1 and IOC2 in the serial data. When the data value 0: Input port When the data value 1: Output port • When specified to function as an input port: The input pin state is reported to the controller through the DO pin. IO1 11 IO2 14 I/O port When the input state is low: The data will be 0: When the input state is high: The data will be 1: • When specified to function as an output port: The output state is determined by IO1 and IO2 in the serial data. When the data value is 0: The output state will be the open circuit state. When the data value is 1: The output state will be a low level. • These pins are set to input mode after a power on reset. Continued on next page. No.A2009-6/24 LC72121MA Continued from preceding page. Pin name Pin No. Type Function Equivalent circuit • PLL charge pump output PD 19 Charge pump output A high level is output when the frequency of the local oscillator signal divided by N is higher than the reference frequency, and a low level is output when that frequency is lower. This pin goes to the highimpedance state when the frequencies match. AIN 20 AOUT 21 VSSa 22 Low-pass filter amplifier transistor Ground • Connections for the MOS transistor used for the PLL active low-pass filter. • Ground for the low-pass filter MOS transistor • The input frequency range is 0.4 to 15MHz IFIN 13 IF counter • The signal is passed directly to the IF counter. • The result is output, MSB first, through the DO pin. • Four measurement periods are supported: 4, 8, 32, and 64ms. NC 12 23 NC pin • No connection - No.A2009-7/24 LC72121MA Procedures for Input and Output of Serial Data This product uses the CCB (Computer Control Bus), which is Ours audio product serial bus format, for data input and output. This product adopts an 8-bit address CCB format. I/O mode Address B0 B1 B2 B3 A0 A1 A2 Function A3 • Control data input (serial data input) mode [1] IN1(82) 0 0 0 1 0 1 0 0 • 24 bits of data are input. • See the “DI Control Data (serial data input)” section for details on the content of the input data. • Control data input (serial data input) mode [2] IN2(92) 1 0 0 1 0 1 0 0 • 24 bits of data are input. • See the “DI Control Data (serial data input)” section for details on the content of the input data. • Data output (serial data output) mode [3] OUT(A2) 0 1 0 1 0 1 0 0 • The number of bits output is equal to the number of clock cycles. • See the “DO output Data (serial data output)” section for details on the content of the output data. ∼ ∼ I/O mode determined ∼ ∼ CE (1) (2) DI B0 B1 B2 B3 A0 A1 A2 A3 First data IN1/2 (1) First data OUT DO (2) ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ CL First data OUT (1) CL:Normally high (2) CL:Normally low No.A2009-8/24 P13 P14 P15 SNS DVS UL1 DZ0 DZ1 GT0 GT1 R1 TEST0 R2 R3 TEST1 TEST2 (2) R-CTR IFS (11) IFS (12) TEST R0 DLC (10) PD-C XS TBC CTE P12 UL0 (3) IF-CTR P11 DOC2 P9 P10 DOC0 DOC1 (9) TIME (3) IF-CTR 0 (8) DZ-C 0 P8 0 (7) UNLOCK (1) P-CTR 0 DNC P7 1 BO4 P4 P3 P6 First data IN2 P5 Address BO3 [2] IN2 mode BO2 0 1 (6) DO-C 1 0 (13) Don’t care 0 BO1 0 1 (5) O-PORT 1 0 IO2 0 P2 P1 P0 0 IO1 IOC2 DI IOC1 DI (4) IO-C LC72121MA Structure of the DI Control Data (serial data input) [1] IN1 mode Address First data IN1 No.A2009-9/24 LC72121MA Control Data No. Control block/data Function Related data • Specifies the divisor for the programmable divider. This is a binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS. (* : don’t care) DVS Programmable divider data (1) P0 to P15 DVS, SNS SNS LSB Set divisior (N) Actual divisior 1 * P0 272 to 65535 Twice the set value 0 1 P0 272 to 65535 The set value 0 0 P4 4 to 4095 The set value * LSB : When P4 is the LSB, P0 to P3 are ignored. • These pins select the signal input to the programmable divider (FMIN or AMIN) and switch the input frequency range. (* : don’t care) DVS SNS Input pin Frequency range accepted by the input pin 10 to 160MHz 1 * FMIN 0 1 AMIN 2 to 40MHz 0 0 AMIN 0.5 to 10MHz * See the “Structure of the Programmable Divider” section for details. • Reference frequency selection Reference divider data (2) R0 to R3 XS R3 R2 R1 R0 0 0 0 0 Reference frequency 0 0 0 1 50 0 0 1 0 25 0 0 1 1 25 0 1 0 0 12.5 0 1 0 1 6.25 0 1 1 0 3.125 0 1 1 1 1 0 0 0 10 1 0 0 1 9 1 0 1 0 5 1 0 1 1 1 1 1 0 0 3 1 1 0 1 15 1 1 1 0 * PLL INHIBIT+X’tal OSC STOP 1 1 1 1 * PLL INHIBIT 100 kHz 3.125 * PLL INHIBIT mode In this mode, the programmable divider and the IF counter block are stopped, the FMIN, AMIN, and IFIN pins are pulled down to ground, and the charge pump output goes to the highimpedance state. • Crystal oscillator element selection data XS = 0: 4.5MHz XS = 1: 7.2MHz Note that 7.2 MHz is selected after a power on reset. • IF counter measurement start command data CTE = 1 : Starts the counter IF counter control data (3) CTE GT0, GT1 CTE = 0 : Resets the counter • IF counter measurement time. GT1 GT0 0 0 0 1 1 Measurement time Wait time 4 ms 3 to 4 ms 1 8 3 to 4 0 32 7 to 8 1 64 7 to 8 IFS * See the “Structure of the IF Counter” section for details. (4) I/O port setup data IOC1,IOC2 Output port data (5) BO1 to BO4 IO1,IO2 • Specifies input or output for the shared function I/O pins (IO1 and IO2). Data = 0: Input port Data = 1: Output port • Determines the output state of the BO1 through BO4, IO1, and IO2 output ports. Data = 0: Open IOC1 Data = 1: Low level IOC2 • The data is reset to 0, setting the pins to the open state, after a power on reset. Continued on next page. No.A2009-10/24 LC72121MA Continued from preceding page. No. Control block/data Function Related data • Determines the DO pin output. DOC2 DOC1 DOC0 0 0 0 DO pin state Open 0 0 1 Low when the PLL is unlocked 0 1 0 end-UC *1 0 1 1 Open 1 0 0 Open 1 0 1 1 1 0 The IO1 pin state *2 The IO2 pin state *2 1 1 1 Open The open state is selected after a power on reset. *1. end-UC: IF counter measurement end check CTE ∼ ∼ DO pin (6) UL0, UL1 ∼ ∼ DO pin control data DOC0 DOC1 (1) Count start DOC2 (2) Count end CE:high IOC1 IOC2 (1)When end-UC is selected and an IF count is started (by switching CTE from 0 to 1), the DO pin automatically goes to the open state. (2)When the IF counter measurement period completes, the DO pin goes to the low level, allowing applications to test for the completion of the count period. (3)The DO pin is set to the open state by performing a serial data input or output operation (when the CE pin is set high). *2. The DO pin will go to the open state if the corresponding IO pin is set up to be an output port. Note) During the data input period (the period that CE is high in IN1 or IN2 mode), the DO pin goes to the open state regardless of the DO pin control data (DOC0 to DOC2). During the data output period (the period that CE is high in OUT mode) the DO pin state reflects the internal DO serial data in synchronization with the CL clock, regardless of the DO pin control data (DOC0 to DOC2). • Selects the width of the phase error (φE) detected for PLL lock state discrimination. The state is taken to be unlocked if a phase error in excess of the detection width occurs. (7) Unlocked state UL1 UL0 φE detection width Detection output detection data 0 0 Stop Open 0 1 0 φE is output directly 1 0 ±0.55μs φE is extended by 1 to 2ms 1 1 ±1.11μs ↑ UL0, UL1 DOC0 DOC1 DOC2 * When the PLL is unlocked, the DO pin goes low and UL in the serial data output is set to 0. • Controls the phase comparator dead zone Phase comparator (8) DZ1 DZ0 Dead zone mode 0 0 DZA 0 1 DZB 1 0 DZC 1 1 DZD control data DZ0, DZ1 Dead zone width: DZA < DZB < DZC < DZD (9) Clock time base TBC • Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from the BO1 pin. (The BO1 data will be ignored.) BO1 • Forcibly controls the charge pump output. Charge pump (10) control data DLC IF counter control (11) data IFS DLC Charge pump output 0 Normal operation 1 Forced Low * If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being stopped, applications can get out of the deadlocked state by setting the charge pump output to low and setting Vtune to VCC. (Deadlock clear circuit) • This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity mode, in which the sensitivity is reduced by about 10 to 30mV rms. * See the “IF Counter Operation” section for details. • Test data (12) Test data TEST0 to 2 TEST0 TEST1 All these bits must be set to 0. TEST2 All these bits are set to 0 after a power on reset. (13) DNC • This bit must be set to 0. No.A2009-11/24 LC72121MA Structure of the DO Output Data (serial data output) [3] OUT mode 0 1 0 1 0 1 0 0 C16 DI C17 Address C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 (3) IF-CTR C11 C12 C13 C14 C15 C18 C19 UL (2) UNLOCK * I1 (1) IN-PORT DO I2 Fist data OUT *: Data with the value 0 Control Data Functions No. Control block/data Function Related data • Data latched from the I/O port IO1 or IO2 pin states. I/O port data I2, I1 PLL unlocked state (2) data UL IF counter (3) • These bits reflect the pin states regardless of the I/O port mode (input or output). The data is latched at the point the circuit enters data output mode (OUT mode). (1) binary counter C19 to C0 I1 ← The IO1 pin state High : 1 I2 ← The IO2 pin state Low : 0 • Indicates the state of the unlocked state detection circuit. UL ← 0: When the PLL is unlocked. UL ← 1: When the PLL is locked or in the detection disabled mode. • Indicates the value of the IF counter (20-bit binary counter). IOC1 IOC2 UL0 UL1 CTE C19 ← MSB of the binary counter GT0 C0 ← LSB of the binary counter GT1 No.A2009-12/24 LC72121MA 1.Serial Data Input (IN1/IN2) tSU, tHD, tES, tEH, ≥ 0.75μs tLC < 0.75μs (1) CL: Normally high tEL tES tEH CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data (2) CL: Normally low tEL tES tEH CE CL tSU tHD B0 DI B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC Internal data 2.Serial Data Output (Out) tSU, tHD, tEL, tES, tEH, ≥ 0.75μs tDC, tDH < 0.35μs (1) CL: Normally high tEL CE tES tEH CL tSU tHD B0 DI B1 B2 B3 A0 A1 A2 A3 tDC I2 tDC I1 tDH UL C3 C1 C0 DO (2) CL: Normally low tEL tES tEH CL tSU DI DO tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC tDC I2 I1 tDH UL C3 C2 C1 C0 Note: The data conversion times (tDC and tDH) depend on the value of the pull-up resistor and the printed circuit board capacitance since the DO pin is an n-channel open-drain circuit. No.A2009-13/24 LC72121MA Serial Data Timing VIH CE tCH VIH VIL CL VIL tCL VIH VIL VIH tES tEL VIH VIL VIH tEH DI VIL tSU tHD VIL tDC tDC tDH DO tLC Internal data latch Old New When CL is Stopped at the Low Level VIH CE tCL CL VIL tCH VIH VIL VIH VIH VIH VIL tEL tES VIH tEH DI VIL tSU tHD VIL tDC tDH DO tLC Internal data latch Old New When CL is Stopped at the High Level No.A2009-14/24 LC72121MA Structure of the Programmable Divider 4bits FMIN 1/2 12bits (A) Swallow counter Programmable divider (C) (B) AMIN fvco/N φE PD fref DVS fvco = fref × N SNS DVS SNS Input pin Set divisor Actual divisor Input frequency range (A) 1 * FMIN 272 to 65535 Twice the set value 10 to 160MHz (B) 0 1 AMIN 272 to 65535 The set value 2 to 40MHz (C) 0 0 AMIN 4 to 4095 The set value 0.5 to 10MHz *: Don’t care Sample Programmable Divider Divisor Calculations (1) For FM with a step size of 50kHz (DVS = 1, SNS = *: FMIN selected) FM RF = 90.0MHz (IF +10.7MHz) FM VCO = 100.7MHz PLL fref = 25kHz (R0 to R1 = 1, R2 to R3 = 0) 100.7MHz (FM VCO) ÷ 25kHz (fref) ÷ 2 (for the FMIN 1/2 prescaler) = 2014 → 07DE (hexadecimal) 1 1 0 0 R1 R2 R3 1 R0 * XS 0 CTE P13 0 DVS 0 SNS 0 P15 0 P14 1 P12 1 P11 1 0 P10 1 P9 P5 1 P8 0 P7 1 7 P6 1 P4 P1 1 P3 1 D P2 0 P0 E (2) For SW with a step size of 5kHz (DVS = 0, SNS = 1: AMIN high-speed operation selected) SW RF = 21.75 MHz (IF +450kHz) SW VCO = 22.20MHz PLL fref = 5kHz (R0 = R2 = 0, R1 = R3 = 1) 22.2MHz (SW VCO) ÷ 5kHz (fref) = 4440 → 1158 (hexadecimal) 0 1 0 1 R3 0 R2 1 R1 0 R0 0 XS 0 CTE 1 DVS 0 SNS 0 P15 P5 0 P14 P4 1 P13 P3 0 P12 P2 1 P11 0 1 P10 1 P9 1 P8 0 P7 0 1 P6 0 P1 5 P0 8 (3) For MW with a step size of 9kHz (DVS = 0, SNS = 0: AMIN low-speed operation selected) MW RF = 1008kHz (IF +450kHz) WM VCO = 1458kHz PLL fref =9kHz (R0 = R3 = 1, R1 = R2 = 0) 1458 (MW VCO) ÷ 9kHz (fref) = 162 → 0A2 (hexadecimal) 0 0 0 1 0 1 0 0 0 0 0 0 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 SNS DVS 1 0 0 1 R3 1 R2 0 R1 * R0 * XS * CTE * P2 0 P1 A P0 2 No.A2009-15/24 LC72121MA Structure of the IF Counter The LC72121MA IF counter is a 20-bit binary counter, and takes the IF signal from the IFIN pin as its input. The result of the count can be read out serially, MSB first, from the DO pin. IF counter (20-bits binary counter) (Fc) IFIN L S B M S B 0 to 3 4/8/32/64 ms DO pin 4 to 7 8 to 11 12 to 15 16 to 19 (C) (GT) CTE GT0 GT1 C = Fc × GT Measurement time GT1 GT0 0 0 4 ms 3 to 4 ms 0 1 8 3 to 4 1 0 32 7 to 8 1 1 64 7 to 8 Measurement time (GT) Wait time (tWU) The IF frequency (Fc) is measured by determining how many pulses were input to the IF counter in the stipulated measurement time, GT. C Fc = GT (C=Fc × GT) C: Counted value (the number of pulses) IF Counter Frequency Measurement Examples (1) When the measurement time (GT) is 32ms and the counted value (C) is 53980 (hexadecimal) or 342,400 (decimal). IF frequency (Fc) = 342400 ÷ 32ms = 10.7MHz 0 0 0 0 C0 0 C1 C6 0 C2 0 C3 1 C4 1 0 C5 0 C7 0 C8 1 8 C9 1 C10 C14 1 C11 0 C12 0 9 C13 1 C15 C18 0 C16 1 3 C17 0 C19 UL I1 I2 5 (2) When the measurement time (GT) is 8ms and the counted value (C) is E10 (hexadecimal) or 3600 (decimal). IF frequency (FC) = 3600 ÷ 8ms = 450kHz 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 0 C16 1 C17 E C18 0 C19 UL I1 I2 0 No.A2009-16/24 LC72121MA IF Counter Operation CE Data with CTE 1 Measurement time Frequency measurement time GT Wait time IFIN Count start Count end (end-UC) Applications must first, before starting an IF count operation reset the IF counter by setting CTE in the serial data to 0. The IF counter operation is started setting CTE in the serial data from 0 to 1. Although the serial data is latched by dropping the CE pin from high to low, the IF signal input to the IFIN pin must be provided within the wait time from the point CE goes low. Next, the readout of the IF counter after measurement is complete must be performed while CTE is still 1, since the counter will be reset if CTE is set to 0. Note: If IF counting is used, applications must determine whether or not the IF IC SD (station detect) signal is present in the microcontroller software, and perform the IF count only if that signal is asserted. This is because autosearch techniques that use IF counting only are subject to incorrect stopping at points where there is no station due to IF buffer leakage. Note that the LC72121MA input sensitivity can be controlled with the IFS bit in the serial data. Reduced sensitivity mode (IFS = 0) must be selected when this IC is used in conjunction with an IF IC that does not provide an SD output and auto-search is implemented using only IF counting. IFIN Minimum Sensitivity Standard Input frequency : f [MHz] IFS data 0.4 ≤ f < 0.5 0.5 ≤ f < 8 8 ≤ f ≤ 15 1 (Normal mode) 40mVrms (0.1 to 3mVrms) 40mVrms 40mVrms(1 to 15mVrms) 0 (Degraded sensitivity mode) 70mVrms(5 to 10mVrms) 70mVrms 70mVrms(30 to 40mVrms) Note: Values in parentheses are actual performance values that are provided for reference purposes. No.A2009-17/24 LC72121MA Unlocked State Detection 1. Unlocked state detection timing Unlocked state detection is performed during the reference frequency (fref) period (interval). This means that a period at least as long as the period of the reference frequency is required to recognize the locked/unlocked state. However, applications must wait at least twice the period of the reference frequency immediately after changing the divisor (N) before checking the locked/unlocked state. CE Data latch Old data New data VCO/N Ncounter Old divisor N New divisor N ▼ fref φError (Unlock) Do not change the divisor N in the first period. * After changing the value of the divisor, the φ error signal will be output following the second period of the fref signal. Figure 1 Unlocked State Detection Timing For example, if fref is 1kHz (a period of 1ms) applications must wait at least 2 ms after the divisor N is changed before performing a locked/unlocked check. ÷R VCO ÷N fref VCO/N Unlocked state detection circuit Unlock Phase comparator φError Preset L.P.F Data latch Figure 2 Circuit Structure No.A2009-18/24 LC72121MA 2. Combining with Software Data input Data output (1) Data output (2) CE Divisor N Old data New data VCO frequency φError Unlocked state output in the serial data Unlocked detection pin output Locked Unlocked Locked Figure 3 Combining with Software 3. Outputting the unlocked state data in the serial data At the point of data output 1 in figure 3, the unlocked state data will indicate the unlocked state, since the VCO frequency is not stable (locked) yet. In cases such as this, the application should wait at least one whole period and then check again whether or not the frequency has stabilized with the data output 2 operation in the figure. Applications can implement even more reliable recognition of the locked state by performing several more checks of the state and requiring that the locked state be detected sequentially. Divisor N changed (data input) Wait at least 2 reference frequency periods. Data output (1) Valid output data is acquired by using an interval of at least one reference frequency period. Data output (2) Locked state check * YES NO *: Even more reliable recognition of the locked state can be achieved by performing several checks of the state and requiring that the locked state be detected sequentially. 4. Directly outputting the unlocked state to the DO pin Since the unlocked state (high level when locked, low when unlocked) is output from the DO pin, applications can check for the locked state by waiting at least two reference frequency periods after changing the divisor N. However, in this case also, even more reliable recognition of the locked state can be achieved by performing several checks of the state and requiring that the locked state be detected sequentially. No.A2009-19/24 LC72121MA Clock Time Base Usage Notes When using the clock time base output function, the output pin (BO1) pull-up resistor must have a value of over 100kΩ. The use of a Schmitt input in the microcontroller that accepts this signal is recommended to reduce chattering. This is to prevent degradation of the VCO C/N characteristics when combining with a loop filter that uses the internal transistor provided to form a low-pass filter. Although the ground for the clock time base output pin (VSSd) and the ground for the transistor (VSSa) are isolated internally on the chip, applications must take care to avoid ground loops and minimize current fluctuations in the time base pin to prevent degradation of the low-pass filter characteristics. VDD LC72121MA Rt ≥ 100kΩ Microcontroller BO1 S Time base output Schmitt input VSSd PD VCC VSSd AOUT AIN VCO Vt Loop filter VSSa Other Items (1) Notes on the phase comparator dead zone DZ1 DZ0 Dead zone mode Charge pump Dead zone 0 0 DZA ON/ON --0s 0 1 DZB ON/ON -0s 1 0 DZC OFF/OFF +0s 1 1 DZD OFF/OFF ++0s When the charge pump is used with one of the ON/ON modes, correction pulses are generated from the charge pump even if the PLL is locked. As a result, it is easy for the loop to become unstable, and special care is required in application design. The following problems can occur if an ON/ON mode is used. (1) Sidebands may be created by reference frequency leakage. (2) Sidebands may be created by low-frequency leakage due to the correction pulse envelope. Although the loop is more stable when a dead zone is present (i.e. when an OFF/OFF mode is used), a dead zone makes it more difficult to achieve excellent C/N characteristics. On the other hand, while it is easy to achieve good C/N characteristics when there is no dead zone, achieving good loop stability is difficult. Accordingly, the DZA and DZB settings, in which there is no dead zone, can be effective in situations where a signal-to-noise ratio of 90 to 100dB or higher is required in FM reception, or where it is desirable to increase the pilot margin in AM stereo reception. However, if such a high signal-to-noise ratio is not required for FM reception, if an adequate pilot margin can be acquired in AM stereo reception, or if AM stereo is not required, then either DZC or DZD, in which there is a dead zone, should be chosen. No.A2009-20/24 LC72121MA Dead Zone As shown in figure 1, the phase comparator compares a reference frequency (fr) with fp. As shown in figure 2, the phase comparator's characteristics consist of an output voltage (V) that is proportional to the phase difference φ. However, due to internal circuit delay and other factors, an actual circuit has a region (the dead zone, B) where the circuit cannot actually compare the phases. To implement a receiver with a high S/N ratio, it is desirable that this region be as small as possible. However, it is often desirable to have the dead zone be slightly wider in popularly-priced models. This is because in certain cases, such as when there is a strong RF input, popularly-priced models can suffer from mixer to VCO RF leakage that modulates the VCO. When the dead zone is small, the circuit outputs signals to correct this modulation and this output further modulates the VCO. This further modulation may then generate beats and the RF signal. V RF (A) MIX Reference divider Programmable divider fr Leakage (B) Phase fp LPF Detector Figure 1 VCO φ(ns) Dead zone Figure 2 (2) Notes on the FMIN, AMIN, and IFIN pins Coupling capacitors should be placed as close to their pin as possible. A capacitance of about 100pF is desirable for these capacitors. In particular, if the IFIN pin coupling capacitor is not held under 1000pF, the time to reach the bias level may become excessive and incorrect counts may result due to the relationship with the wait time. (3) Notes on IF counting → Use the SD signal in conjunction with IF counting When counting the IF frequency, the microcontroller must determine the presence or absence of the IF IC SD (station detect) signal and turn on the IF counter buffer output and execute the IF count only if there is an SD signal. Autosearch techniques that only use the IF counter are subject to incorrect stopping at points where there is no station due to IF buffer leakage. (4) DO pin usage The DO pin can be used for IF counter count completion checking and as an unlock detection output in addition to its use in data output mode. It is also possible to have the DO pin reflect the state of an input pin to input that state to the microcontroller. (5) Power supply pins Capacitors must be inserted between the power supply VDD and VSS pins for noise exclusion. These capacitors must be placed as close as possible to the VDD and VSS pins. (6) VCO setup Applications must be designed so that the VCO (local oscillator) does not stop, even if the control voltage (Vtune) goes to 0V. If it is possible for the oscillator to stop, the application must use the control data (DLC) to temporarily force Vtune to VCC to prevent deadlock from occurring. (Deadlock clear circuit) No.A2009-21/24 LC72121MA (7) Front end connection example Since this product is designed with the relatively high resistance of 200kΩ for the pulldown (on) resistors built in to the FMIN and AMIN pins, a common AM/FM local oscillator buffer can be used as shown in the following circuit. FMIN FM OSC OSC buffer out On resistance: 200kΩ AM OSC AMIN On resistance: 200kΩ FE PLL (8) PD pin Note that the charge pump output voltage is reduced when this IC, which is a 3-V system, is used to replace the LC72131K/KMA, which is a 5-V system. This means that since the loop gain is reduced, the loop filter constants, the lock time (SD wait time), and other related parameters must be reevaluated in the end product design. Pin States after a Power on Reset XOUT XIN NC VSSX VSSa DI AOUT CL AIN LC72121MA CE PD Open DO Open BO1 Open BO2 Open BO3 AMIN Open BO4 VSSd Input port IO1 IO2 NC IFIN VDD FMIN Input port No.A2009-22/24 LC72121MA Sample Applications Circuit XIN 1 VSSX 2 μ-COM 23 NC CE CE 3 S 22 VSSa DI DI 4 S 21 AOUT CL CL 5 S 20 AIN DO DO 6 BO1 7 LC72121MA Unlock SD end-UC IFcount ST-indic 24 XOUT FMVCO 19 PD 18 VDD BO2 8 17 FMIN BO3 9 16 AMIN BO4 10 15 VSSd IO1 11 VCC 14 IO2 AMVCO SD TUNER-System NC 12 13 IFIN AM/FM-IF IF-Request FM/AM MONO/ST ST-Indicate No.A2009-23/24 LC72121MA ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. 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