LC72131KMA-AE

LC72131K, LC72131KMA PLL Frequency Synthesizer for Tuners in Radio/Cassette Players Overview The LC72131K and LC72131KMA are PLL frequency synthesizers for use in tuners in radio/cassette players. They allow high-performance AM/FM tuners to be implemented easily. Features  High speed programmable dividers  FMIN: 10 to 160 MHz ····· pulse swallower (built-in divide-by-two prescaler)  AMIN: 2 to 40 MHz ······ pulse swallower 0.5 to 10 MHz ····· direct division  IF counter  IFIN: 0.4 to 12 MHz ······ AM/FM IF counter  Reference frequencies  Twelve selectable frequencies (4.5 or 7.2 MHz crystal)  100, 50, 25, 15, 12.5, 6.25, 3.125, 10, 9, 5, 3, 1 kHz  Phase comparator  Dead zone control  Unlock detection circuit  Deadlock clear circuit  Built-in MOS transistor for forming an active low-pass filter  I/O ports  Dedicated output ports: 4  Input or output ports: 2  Support clock time base output  Serial data I/O  Support CCB* format communication with the system controller.  Operating ranges  Supply voltage : 4.5 to 5.5 V  Operating temperature : 40 to +85C  Packages  LC72131K : DIP22S (300mil)  LC72131KMA : MFP20J (300mil) www.onsemi.com PDIP22 / DIP22S (300 mil) [LC72131K] SOIC20W / MFP20J (300 mil) [LC72131KMA] * Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and the bus addresses are controlled by ON Semiconductor. ORDERING INFORMATION See detailed ordering and shipping information on page 23 of this data sheet. © Semiconductor Components Industries, LLC, 2017 July 2017 - Rev. 1 1 Publication Order Number : LC72131K_KMA/D LC72131K, LC72131KMA Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Supply voltage Maximum input voltage Symbol VDD max VIN1 max VIN2 max VIN3 max Maximum output voltage VO1 max VO2 max VO3 max Pins VDD CE, CL, DI, AIN XIN, FMIN, AMIN, IFIN Conditions Ratings 0.3 to +7.0 0.3 to +7.0 0.3 to VDD+0.3 IO1, IO2 DO XOUT, PD BO1 to BO4, IO1, IO2, AOUT Maximum output current IO1 max IO2 max IO3 max Allowable power dissipation Pd max Operating temperature Storage temperature 0.3 to +15 V 0.3 to +7.0 0.3 to VDD+0.3 V V 0.3 to +15 V BO1 DO, AOUT BO2 to BO4, IO1, IO2 Ta  85C [LC72131K] Ta  85C [LC72131KMA] 0 to 3.0 mA 0 to 6.0 mA 0 to 10 mA 350 mW 180 mW 40 to +85 55 to +125 Topr Tstg Unit V V V C C Note 1: Power pins VDD and VSS: Insert a capacitor with a capacitance of 2,000pF or higher between these pins when using the IC. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ranges at Ta = 40C to +85C, VSS = 0 V Parameter Symbol Supply voltage Input high-level voltage VDD VIH1 VIH2 Input low-level voltage VIL Output voltage VO1 VO2 Input frequency Supported crystals Input amplitude High-level clock pulse width tφH CL [Figure 1] [Figure 2] 160 ns Low-level clock pulse width Data setup time Data hold time Clock low-level time Clock high-level time CE wait time CE setup time CE hold time Data latch change time Data output time fIN1 fIN2 fIN3 fIN4 fIN5 X'tal VIN1 VIN2-1 VIN2-2 VIN3 VIN4 VIN5 VIN6 tSU tHD tCL tCH tEL tES tEH tLC tDC tDH Pins Conditions Ratings typ VDD CE, CL, DI IO1, IO2 0.7VDD 13 V 0 0.3VDD V 0 6.5 V 0 13 V 1.0 10 2.0 0.5 0.4 4.0 400 40 70 40 40 40 70 0.75 0.75 0.75 0.75 0.75 0.75 0.75 8.0 160 40 10 12 8.0 1500 1500 1500 1500 1500 1500 1500 MHz MHz MHz MHz MHz MHz mVrms mVrms mVrms mVrms mVrms mVrms mVrms 0.75 s s s s s s s s 0.35 s CE, CL, DI, IO1, IO2 DO BO1 to BO4, IO1, IO2, AOUT XIN FMIN AMIN AMIN IFIN XIN, XOUT XIN FMIN FMIN AMIN AMIN IFIN IFIN DI, CL DI, CL CL CL CE, CL CE, CL CE, CL VIN1 VIN2 VIN3 VIN4 VIN5 Note 1 fIN1 f = 10 to 130 MHz f = 130 to 160 MHz fIN3 fIN4 fIN5 (IFS=1) fIN5 (IFS=0) Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Differs depending on the value of the pull-up resistor. Note 2 DO, CL DO, CE www.onsemi.com 2 max 5.5 6.5 unit min 4.5 0.7VDD V V LC72131K, LC72131KMA Note 1: Recommended crystal oscillator CI values: CI  120 Ω (For a 4.5 MHz crystal) CI  70 Ω (For a 7.2 MHz crystal) The characteristics of the oscillation circuit depends on the printed circuit board, circuit constants, and other factors. Therefore we recommend consulting with the anufacturer of the crystal for evaluation and reliability. Note 2: Refer to "Serial Data Timing". Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Electrical Characteristics in the Allowable Operating Ranges Parameter Built-in feedback resistance Built-in pull-down resistor Hysteresis Output high-level voltage Output low-level voltage Input high-level current Input low-level current Output off leakage current High-level three-state off leakage current Low-level three-state off leakage current Input capacitance Current drain Symbol Rf1 Rf2 Rf3 Rf4 Rpd1 Rpd2 VHYS VOH Pins Conditions XIN FMIN AMIN IFIN FMIN AMIN CE, CL, DI, IO1, IO2 PD VOL1 VOL2 BO1 VOL3 DO VOL4 BO2 to BO4, IO1, IO2 VOL5 AOUT IIH1 IIH2 IIH3 IIH4 IIH5 IIH6 IIL1 IIL2 IIL3 IIL4 IIL5 IIL6 IOFF1 Ratings typ 1.0 500 500 250 200 200 0.1VDD min IO = 1 mA PD IO = 1 mA IO = 0.5 mA IO = 1 mA IO = 1 mA IO = 5 mA IO = 1 mA IO = 5 mA IO = 8 mA IO = 1 mA AIN = 1.3 V VI = 6.5 V VI = 13 V VI = VDD VI = VDD VI = VDD VI = 6.5 V VI = 0 V VI = 0 V CE, CL, DI IO1, IO2 XIN FMIN, AMIN IFIN AIN CE, CL, DI IO1, IO2 XIN FMIN, AMIN IFIN AIN max unit MΩ kΩ kΩ kΩ kΩ kΩ V VDD0.1 V 2.0 4.0 8.0 1.0 0.5 1.0 0.2 1.0 0.2 1.0 1.6 V V V V V V V V 0.5 V 5.0 A 5.0 A 11 22 44 200 5.0 A A A nA 5.0 A 11 22 44 200 A A A nA 5.0 A 5.0 A A BO1 to BO4, AOUT, VI = 0 V VI = 0 V VI = 0 V VI = 0 V VO = 13 V IOFF2 IOFFH IO1, IO2 DO PD VO = 6.5 V VO = VDD 0.01 200 nA IOFFL PD VO = 0 V 0.01 200 nA CIN IDD1 FMIN VDD IDD2 IDD3 2.0 4.0 8.0 6 X'tal = 7.2 MHz fIN2 = 130 MHz VIN2 = 40 mVrms PLL block stopped (PLL INHIBIT) X'tal oscillator operating (X'tal = 7.2 MHz) PLL block stopped X'tal oscillator operating VDD VDD 5 pF 10 0.5 mA mA 10 A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 3 LC72131K, LC72131KMA  Serial Data Timing VIH tCL VIH VIL VIH VIH DI VIL tSU VIH VIL tHD tEL       CL VIL VIL DO Internal data latch VIL tES tDC tDC VIH        tCH   CE tEH tDH tLC Old New VIH VIH VIL VIH VIH VIL DO Internal data latch tSU tHD VIL        VIH DI VIL  tCL tEL VIL tES tDC When stopped with CL high www.onsemi.com 4       tCH  CE CL  When stopped with CL low VIH tEH tDH tLC Old New LC72131K, LC72131KMA Package Dimensions unit : mm [LC72131K] to PDIP22 / DIP22S (300 mil) CASE 646AV ISSUE A GENERIC MARKING DIAGRAM* XXXXXXXXXX YMDDD XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data *This information is generic. www.onsemi.com 5 LC72131K, LC72131KMA Package Dimensions unit : mm [LC72131KMA] SOIC20W / MFP20J (300 mil) CASE 751DE ISSUE O to www.onsemi.com 6 LC72131K, LC72131KMA XOUT VSS AOUT AIN PD VDD FMIN AMIN NC IO2 IFIN Pin Assignments 22 21 20 19 18 17 16 15 14 13 12 2 3 4 5 6 7 8 9 10 NC CE DI CL DO BO1 BO2 BO3 BO4 11 IO1 1 XIN LC72131K XOUT VSS AOUT AIN PD VDD FMIN AMIN IO2 IFIN Top view 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 XIN CE DI CL DO BO1 BO2 BO3 BO4 IO1 LC72131KMA Top view Block Diagram REFERENCE DIVIDER XIN PHASE DETECTOR CHARGE PUMP PD XOUT FMIN 1/2 SWALLOW COUNTER 1/16,1/17 4bits UNLOCK DETECTOR AIN AOUT 12bits PROGRAMMABLE DIVIDER AMIN CE DI CL CCB I/F DATA SHIFT REGISTER LATCH DO VDD VSS POWER ON RESET BO1 BO2 BO3 BO4 IO1 IO2 www.onsemi.com 7 UNIVERSAL COUNTER IFIN LC72131K, LC72131KMA Pin Functions Symbol Pin No. LC72131K LC72131KMA XIN 1 1 XOUT 22 20 FMIN 16 14 Type X'tal OSC Functions Circuit configuration Crystal resonator connection (4.5MHz/7.2MHz) Local FMIN is selected when the serial data input DVS bit is set to 1. oscillator The input frequency range is from 10 to 160MHz. signal input The input signal passes through the internal divide-by-two prescaler and is input to the swallow counter. The divisor can be in the range 272 to 65535. However, since the signal has passed through the divide-by-two prescaler, the actual divisor is twice the set value. AMIN 15 13 Local AMIN is selected when the serial data input DVS bit is set to 0. oscillator When the serial data input SNS bit is set to 1: signal input  The input frequency range is 2 to 40MHz.  The signal is directly input to the swallow counter.  The divisor can be in the range 272 to 65535, and the divisor used will be the value set. When the serial data input SNS bit is set to 0:  The input frequency range is 0.5 to 10MHz.  The signal is directly input to a 12-bit programmable divider.  The divisor can be in the range 4 to 4095, and the divisor used will be the value set. CE 3 2 Chip enable Set this pin high when inputting (DI) or outputting (DO) serial S data. DI 4 3 Input data Inputs serial data transferred from the controller to the S LC72131K/KMA. CL 5 4 Clock DO 6 5 Output data S Used as the synchronization clock when inputting (DI) or outputting (DO) serial data. Outputs serial data transferred from the LC72131K/KMA to the controller. The content of the output data is determined by the serial data DOC0 to DOC2. VDD 17 15 Power supply The LC72131K/KMA power supply pin (VDD=4.5 to 5.5V) The power on reset circuit operates when power is first applied. VSS 21 19 Ground The LC72131K/KMA ground BO1 7 6 Output port Dedicated output pins BO2 8 7 The output states are determined by BO1 to BO4 bits in BO3 9 8 the serial data. BO4 10 9 - Data: 0=open, 1=low A time base signal (8Hz) can be output from the BO1 pin. (When the serial data TBC bit is set to 1.) Care is required when using the BO1 pin, since it has a higher on impedance that the other output ports (pins BO2 to BO4). IO1 11 10 IO2 13 12 I/O port I/O dual-use pins The direction (input or output) is determined by bits IOC1 and IOC2 in the serial data. Data: 0=input port, 1=output port When specified for use as input ports: S The state of the input pin is transmitted to the controller over the DO pin. Input state: low=0 data value high=1 data value When specified for use as output ports: The output states are determined by the IO1 and IO2 bits in the serial data. Data: 0=open, 1=low These pins function as input pins following a power on reset. Continued on next page. www.onsemi.com 8 LC72131K, LC72131KMA Continued from preceding page. Pin No. Symbol PD LC72131K LC72131KMA 18 16 Type Functions Charge pump Circuit configuration PLL charge pump output output When the frequency generated by dividing the local oscillator frequency by N is higher than the reference frequency, a high level is output from the PD pin. Similarly, when that frequency is lower, a low level is output. The PD pin goes to the high impedance state when the frequencies match. AIN 19 17 LPF amplifier The n-channel MOS transistor used for the PLL active AOUT 20 18 transistors low-pass filter. IFIN 12 11 IF counter Accepts an input in the frequency range 0.4 to 12MHz. The input signal is directly transmitted to the IF counter. The result is output starting the MSB of the IF counter using the DO pin. Four measurement periods are supported: 4, 8, 32, and 64ms. DI Control Data (Serial Data Input) Structure [1] IN1 mode address DI 0 0 0 1 0 1 0 0 R3 R2 (2) R-CTR R1 R0 XS (3) IF-CTR CTE DVS SNS P15 P14 P13 P12 P11 P10 P9 P7 BO4 P8 P6 0 (1) P-CTR P5 0 BO3 P4 1 BO2 P3 P2 P1 P0 First Data IN1 [2] IN2 mode address 1 0 0 1 0 www.onsemi.com 9 TEST2 TEST1 IFS (11) IFS (12) TEST DLC (10) PD-C TEST0 TBC GT1 (9) TIME (3) IF-CTR GT0 DZ1 UL1 DZ0 (8) DZ-C (7) UNLOCK UL0 DOC2 DOC1 (6) DO-C DOC0 DNC (13) Don’t care (5) O-PORT BO1 IO2 IO1 IOC2 IOC1 First Data IN2 (4) IO-C DI LC72131K, LC72131KMA Control Data Functions No. (1) Control block/data Functions Related data Programmable Data that sets the divisor of the programmable divider. divider data A binary value in which P15 is the MSB. The LSB changes depending on P0 to P15 DVS and SNS. (*: don’t care) DVS SNS LSB Divisor setting (N) Actual divisor 1 0 0 * 1 0 P0 P0 P4 272 to 65535 272 to 65535 4 to 4095 Twice the value of the setting The value of the setting The value of the setting Note: P0 to P3 are ignored when P4 is the LSB. DVS, SNS Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches the input frequency range. (*: don’t care) DVS SNS Input pin 1 0 0 * 1 0 FMIN AMIN AMIN Input frequency range 10 to 160MHz 2 to 40MHz 0.5 to 10MHz Note: See the “Programmable Divider Structure” item for more information. (2) Reference divider data R0 to R3 Reference frequency (fref) selection data. R3 R2 R1 R0 Reference frequency 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 100kHz 50 25 25 12.5 6.25 3.125 3.125 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 10 9 5 1 1 1 1 1 0 0 0 1 3 15 1 1 1 0 1 1 1 1 * PLL INHIBIT + X'tal OSC STOP * PLL INHIBIT Note *: PLL INHIBIT The programmable divider block and the IF counter block are stopped, the FMIN, AMIN, and IFIN pins are set to the pull-down state (ground), and the charge pump goes to the high impedance state. XS Crystal resonator selection XS=0: 4.5MHz XS=1: 7.2MHz The 7.2MHz frequency is selected after the power-on reset. (3) IF counter control IF counter measurement start data data CTE=1: Counter start CTE GT0, GT1 IFS =0: Counter reset Determines the IF counter measurement period. GT1 GT0 0 0 1 1 0 1 0 1 Measurement time (ms) 4 8 32 64 Wait time (ms) 3 to 4 3 to 4 7 to 8 7 to 8 Note: See the “IF Counter Structure” item for more information. Continued on next page. www.onsemi.com 10 LC72131K, LC72131KMA Continued from preceding page. No. Control block/data (4) I/O port specification data Functions Related data Specifies the I/O direction for the bidirectional pins IO1 and IO2. Data: 0=input mode, 1=output mode IOC1, IOC2 (5) Output port data BO1 to BO4 (6) Data that determines the output from the BO1 to BO4, IO1 and IO2 output ports IOC2 IO1, IO2 The data=0 (open) state is selected after the power-on reset. DO pin control data Data that determines the DO pin output DOC0 DOC1 DOC2 IOC1 Data: 0=open, 1=low UL0, UL1 DOC2 DOC1 DOC0 Do pin state CTE 0 0 0 0 0 0 1 1 0 1 0 1 Open Low when the unlock state is detected end-UC *1 Open IOC1 1 1 1 1 0 0 1 1 0 1 0 1 Open The IO1 pin state *2 The IO2 pin state *2 Open IOC2 The open state is selected after the power-on reset.  Note: 1. end-UC: Check for IF counter measurement completion  DO pin (1) Count start (2) Count end (3)CE: High (1) When end-UC is set and the IF counter is started (i.e., when CTE is changed from zero to one), the DO pin automatically goes to the open state. (2) When the IF counter measurement completes, the DO pin goes low to indicate the measurement completion state. (3) Depending on serial data I/O (CE: high) the DO pin goes to the open state. Note: 2. Goes to the open state if the I/O pin is specified to be an output port. Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE high) will be open, regardless of the state of the DO control data (DOC0 to DOC2). Also, the DO pin during a data output period (an OUT mode period with CE high) will output the contents of the internal DO serial data in synchronization with the CL pin signal, regardless of the state of the DO control data (DOC0 to DOC2). (7) Unlock detection Selects the phase error (E) detection width for checking PLL lock. DOC0 data A phase error in excess of the specified detection width is seen as an unlocked state. DOC1 UL0, UL1 UL1 UL0 0 0 1 1 0 1 0 1 E detection width stopped 0 0.55s 1.11 DOC2 Detector output Open E is output directry E is extended by 1 to 2ms  Note: In the unlocked state the DO pin goes low and the UL bit in the serial data becomes zero. Continued on next page. www.onsemi.com 11 LC72131K, LC72131KMA Continued from preceding page. No. Control block/data (8) Functions Phase comparator Related data • Controls the phase comparator dead zone. control data DZ0, DZ1 DZ1 DZ0 Dead zone mode 0 0 1 1 0 1 0 1 DZA DZB DZC DZD Dead zone width: DZA