LC72720YVS-MPB-E

Ordering number : ENA2155 LC72720YVS CMOS IC Single-Chip RDS Signal-Processing System IC http://onsemi.com Overview The LC72720YVS is a single-chip system IC that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RBDS (Radio Broadcast Data System) standard. This IC include band-pass filter, demodulator, synchronization, and error correction circuits as well as data buffer RAM on chip and perform effective error correction using a soft-decision error correction technique. Functions • Band-pass filter : switched capacitor filter (SCF) • Demodulator : RDS data clock regeneration and demodulated data reliability information • Synchronization : Block synchronization detection (with variable backward and forward protection conditions) • Error correction : Soft-decision/hard-decision error correction • Buffer RAM : Adequate for 24 blocks of data (about 500ms) and flag memory • Data I/O : CCB interface (power on reset) Features • Error correction capability improved by soft-decision error correction • The load on the control microprocessor can be reduced by storing decoded data in the on-chip data buffer RAM. • Two synchronization detection circuits provide continuous and stable detection of the synchronization. • Data can be read out starting with the backward-protection block data after a synchronization reset. • Fully adjustment free Specifications • Operating power-supply voltage : • Operating temperature : • Package : 3.0 to 3.6V -40 to +85°C SSOP30(275mil) • CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format. • CCB is a registered trademark of Semiconductor Components Industries, LLC. Semiconductor Components Industries, LLC, 2013 June, 2013 N1412HK B8-5256 No. A2155-1/18 LC72720YVS Specifications Absolute Maximum Ratings at Ta = 25°C, Vssd = Vssa = 0V Parameter Symbol Maximum supply voltage Maximum input voltage Maximum output voltage Maximum output current Allowable power dissipation Pin Name Ratings Unit Vddmax Vddd, Vdda -0.3 to +7.0 V Vin1max CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC -0.3 to +7.0 V Vin2max XIN -0.3 to Vddd+0.3 V Vin3max MPXIN, CIN -0.3 to Vdda+0.3 V Vo1max DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 -0.3 to +7.0 V Vo2max XOUT -0.3 to Vddd+0.3 V Vo3max FLOUT -0.3 to Vdda+0.3 V Io1max DO, T3, T4, T5, T6, T7 +6.0 mA Io2max XOUT, FLOUT +3.0 mA Io3max SYNC, RDS-ID +20.0 mA Pdmax (Ta≤85°C) 150 mW Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ranges at Ta = -40 to 85°C, Vssd = Vssa = 0V Parameter Pin Name Symbol Vdd1 Vddd, Vdda Vdd2 Vddd Conditions Ratings min typ 3.0 max 3.6 Unit V Supply voltage Input high-level voltage Input low-level voltage Output voltage VIH VIL VO VIN1 Input amplitude CL, DI, CE, SYR, T1, T2 CL, DI, CE, SYR, T1, T2 2.0 V 0.7Vddd 6.5 V 0 0.3Vddd V 6.5 V 50 mVrms DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 MPXIN f=57±2kHz 100% modulation composite VIN2 VXIN XIN XTAL XIN, XOUT Guaranteed crystal Oscillator Serial data hold voltage frequencies Crystal oscillator frequency deviation TXtal Data setup time tSU Data hold time tHD Clock low level time tCL Clock high level time tCH CE wait time tEL CE setup time CE hold time CE high-level time tCE CE Data latch change tLC XIN, XOUT 100 mVrms 400 1500 mVrms CI≤120Ω (XS=0) 4.332 MHz CI≤70Ω (XS=1) 8.664 MHz ±100 fo=4.332MHz, 8.664MHz ppm 0.75 μs DI, CL 0.75 μs CL 0.75 μs CL 0.75 μs CE, CL 0.75 μs tES CE, CL 0.75 μs tEH CE, CL 0.75 μs DI, CL 20 ms 1.15 μs 0.46 μs 0.46 μs time tDC DO,CL tDH DO,CE Data output time Differs depending on the value of the pull-up resistor used. No. A2155-2/18 LC72720YVS Electrical Characteristics at Ta = -40 to 85°C, Vssd = Vssa = 0V Pin Name Symbol Input resistance RMPXIN Internal feedback Rf XIN Center frequency fc FLOUT 56.5 57.0 57.5 kHz -3dB band width BW-3dB FLOUT 2.5 3.0 3.5 kHz 31 34 dB MPXIN-Vssa Conditions Ratings Parameter min f=0 to 100kHz typ max Unit 23 kΩ 1.5 MΩ resistance Gain Gain MPXIN-FLOUT f=57kHz 28 Att1 FLOUT Δf=±7kHz 30 dB Att2 FLOUT f70kHz 40 dB Att3 FLOUT f when ARI presence or absence is unclear. 1 0 1 If the circuit determines that the ARI signal is absent : 90° phase If the circuit determines that the ARI signal is present : 0° phase Initial values : PL0 = 0, PL1 = 1 Caution : 1. When PL0 is 0 (normal operation), the IC detects the presence or absence of the ARI signal and reproduces the RDS data by automatically controlling the demodulation phase with respect to the reproduced carrier. However, the initial phase following a synchronization reset is set by PL1. 2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90° (PL1 = 0) or 0° (PL1 = 1), allowing RDS data to be reproduced. When ARI is not present, PL1 should be set to 0, since the RDS data is reproduced by detecting at a phase of 90° with respect to the reproduced carrier. When ARI is present, PL1 should be set to 1, since detection is at 0°. In cases where the ARI presence is known in advance, more stable reproduction can be achieved by fixing the demodulation phase in this manner. (8) RDS/RBDS(MMBS) selection (1bit) : RM RM RBDS Decoding method 0 None 1 Provided Only RDS data is decoded correctly (Offset word E is not detected.) RDS and MMBS data is decoded correctly (Offset word E is also detected.) Initial value : RM=0 (9) Output pin settings (3bits) : PT0 to PT2 These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins MODE P T 0 P T 1 P T 2 0 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 T3 T4 T5 T6 T7 RDCL RDDA RSFT ERROR 57K BE1 CORREC ARI-ID BE0 −    −    −    − − −  − −  − − −  − −  −    −    −    − − −  − − − −  − − − −  − − −  − − − − − − −  − − −  − − − − − : open, ,  : Output enabled ( = reverse polarity) Initial value : PT0 = 1, PT1 = 1, PT2 = 0 (Mode 3) Caution : 1. When PT2 is set to 1, the polarity of the T3(RDCL), T6(ERROR/57K), T7(CORREC/ARI-ID), SYNC, and RDS-ID pins changes to active high. 2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors to output data. No. A2155-11/18 LC72720YVS Item Pin T3 (RDCL) PT2 = 0 Data(RDDA and RSFT) changes on this pin’s rising edge PT2 = 1 Data(RDDA and RSFT) changes on this pin’s falling edge Mode2 (PT2 = 0) Pin T7 (ARI-ID) No SK High (1) SK present Low (0) Mode3 (PT2 = 0) Correction not possible Errors corrected No errors Pin T6 (ERROR) Low (0) High (1) High (1) Pin T7 (CORREC) Low (0) Low (0) High (1) Pin T6 (BE1) Pin T7 (BE0) B=0 Low (0) Low (0) 1 ≤ B ≤ 20 Low (0) High (1) 20 < B ≤ 40 High (1) Low (0) Mode = 4 Number of error blocks (B) 40 < B ≤ 48 High (1) High (1) These pins indicate the number of blocks in a set of 48 blocks that had errors before correction. The output polarity of these pins is fixed at the values listed in the table. Mode (PT2 = 0) The SYNC pin When synchronized : Low (0), When unsynchronized: High (1) When synchronized : Goes high for a fixed period (421 μs) at the start of a block and then goes low. When unsynchronized : High (1) 0 to 2 3 Caution : The output indicates the synchronization state for the previous block. When PT2 = 0 The RDS-ID pin No RDS High (1) RDS present Low (0) (10) Test mode settings (4bits) : TS0 to TS3 Initial values : TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0 (Applications must set these bits to the above values.) Notes : The T1 and T2 pins (pins 9 and 10) are related to test mode as follows. Pin T1 Pin T2 IC operation 0 0 Normal operating mode 0 1 Standby mode (crystal oscillator stopped) 1 0/1 The T1 pin must be tied to VSS (0V). IC test mode Notes These states are user settable Users cannot use this state (11) Circuit control (2 bits) : CT0 and CT1 Item CT0 RSFT control CT1 RDS-ID detection condition Control When set to 1, soft-decision control data (RSFT) is easier to generate. When set to 1, the RDS-ID detection conditions are made more restrictive. Initial value : CT0 = 0, CT1 = 0 No. A2155-12/18 LC72720YVS RDCL / RDDA / RSFT and ERROR / CORREC / SYNC output timing (1) Timing 1 421 μs Tp1 421 μs 421 μs RDCL output RDDA output RSFT output 842 μs Note : When PT2 = 0, RDDA and RSFT must be acquired on the falling edge of RDCL. Error crrection Sync NG Sync OK Sync OK Sync OK Sync OK Sync OK Sync NG Data corrected No errors No errors Data corrected Uncorrectable Input data Uncorrectable (2) Timing 2 (mode 3, PT2 = 0) Tp1 Tp1 Sync NG SYNC output ERROR output CORREC output No. A2155-13/18 LC72720YVS Serial Data Input and Output Methods Data is input and output using the CCB (Computer Control Bus), which is Our audio IC serial bus format. This IC adopts an 8-bit address CCB format. I/O mode (LSB) B0 B1 Address B2 B3 (MSB) A0 A1 A2 A3 [1] IN1 (6A) 0 1 0 1 0 1 1 0 [2] IN2 (6B) 1 1 0 1 0 1 1 0 [3] OUT (6C) 0 0 1 1 0 1 1 0 Comment  Control data input mode, also referred to as “ serial data input ” mode.  16bit data input mode  Data output mode  The data for multiple blocks can be output sequentially in this mode. I/O mode determined CE 1 CL 2 B0 DI B1 B2 B3 A0 A1 A2 A3 First Data IN1/2 1 First Data OUT DO 2 First Data OUT 1 For the CL normal high state 2 For the CL normal low state No. A2155-14/18 LC72720YVS (1) Serial data input (IN1 / IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75μs tLC < 1.15μs tCE < 20 ms  CL : Normal high tEL tCE tES tEH CE CL tSU tHD B0 DI B1 B2 B3 A0 A1 A2 FS0 CT1 A3 FS1 0 FS2 0 FS3 0 EC3 TS0 EC4 TS1 CT0 TS2 0 TS3 tLC Internal data  CL : Normal low tEL tCE tES tEH CE CL tSU tHD B0 DI B1 B2 B3 A0 A1 FS0 CT1 A3 A2 FS1 0 FS2 0 FS3 0 EC3 TS0 EC4 TS1 CT0 TS2 0 TS3 tLC Internal data (2) Serial data output (OUT) tSU, tHD, tEL, tES, tEH ≥ 0.75μs tDC, tDH < 0.46μs tCE < 20 ms  CL : Normal high tEL tCE tES tEH CE CL tSU tHD B0 DI B1 B2 B3 A0 A1 A2 A3 tDC tDC 1 DO  CL : Normal low tEL 0 tDH 1 0 D3 D2 D1 tCE tES D0 tEH CE CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC DO tDH tDC 1 0 1 0 D3 D2 D1 D0 Cautions : 1. Since the DO pin is an n-channel open-drain output, the transition times (tDC, tDH) will differ with the value of the pull-up resistor used. 2. The CE, CL, DI, and DO pins can be connected to the corresponding pins on other ICs that use the CCB interface. (However, we recommend connecting the DO and CE pins separately if the number of available microcontroller ports allows it.) 3. Serial data I/O becomes possible after the crystal oscillator starts oscillation. No. A2155-15/18 LC72720YVS (3) Serial data timing  CL : Normal high tCE VIH CE tCL tCH VIH VIL CL VIL tES tEL VIH VIL DI VIH VIL VIH tEH VIH VIL tSU tHD tDC tDH DO tLC Internal data latch New Old  CL : Normal low tCE VIH CE tCH tCL VIH VIL CL VIH VIL tEL VIH VIL DI tSU VIL VIL VIL tEH tES VIH VIL tHD tDC tDH tDC DO tLC Old Internal data latch Parameter Symbol Conditions min typ max New Unit Data setup time tSU DI, CL 0.75 μs Data hold time tHD DI, CL 0.75 μs Clock low level time tCL CL 0.75 μs Clock high level time tCH CL 0.75 μs CE wait time tEL CE, CL 0.75 μs CE setup time tES CE, CL 0.75 μs CE hold time tEH CE, CL 0.75 μs CE high level time tCE CE Data latch transition time tLC Data output time tDC DO, CL tDH DO, CE Differs with the value of the pull-up resistor used. 20 ms 1.15 μs 0.46 μs 0.46 μs No. A2155-16/18 LC72720YVS DO pin operation This IC incorporates a RAM data buffer that can hold up to 24 blocks of data. At the point when one block of data is written to this RAM, the IC issues a read request by switching the DO pin from high to low. The DO pin always goes high for a fixed period (Tdo = 265 μs) after a readout and CE goes low. When all the data in the data buffer has been read out, the DO pin is held in the high state until a new block of data has been written to the RAM. If there is data that has not yet been read remaining in the data buffer, the DO pin goes low after the Tdo time has elapsed. After a synchronization reset, the DO pin is held high until synchronization is established. It goes low at the point the IC synchronizes.  When the DO pin is high following the 265 μs period (Tdo) after data is read out. Here, the buffer is in the empty state, i.e. the state where new data has not been written. After this, when the DO pin goes low, applications are guaranteed to be able to read out that data without it being overwritten by new data if they start a readout operation within 480 ms of DO going low. Tdo CE pin T DO pin (Last data)-1 New data Last data DO check (Tdo < T)  When DO goes low 265 μs after data is read out Here, there is data that has not been read out remaining in the data buffer. In this case, applications are guaranteed to be able to read out that data without it being overwritten by new data if they start a readout operation within 20 ms of DO going low. (Note that this is the worst case condition.) Tdo CE pin T DO pin (Last data)-2 Last data (Last data)-1 DO check (Tdo < T) Notes : 1. Although an application can determine whether or not there is data remaining in the buffer by checking the DO level with the above timing, checking the RE and RF flags in the serial data is a preferable method. 2. Applications are not limited to reading out one block of data at a time, but rather can read out multiple blocks of data continuously as described above. When using this method, if an application references the RE and RF flags in the data while reading out data, it can determine the amount of data remaining. However, the length of the period for data readout (the period the CE pin remains high) must be kept under 20 ms. 3. If the DO pin is shared with other ICs that use the CCB interface, the application must identify which IC issued the readout request. One method is to read out data from the LC72720YVS and either check whether meaningful data has been read (if the LC72720YVS is not requesting a read, data consisting of all zeros will be read out) or check whether the DO level goes low within the 256 μs following the completion of the read (if the DO pin goes low, then the request was from another IC). No. A2155-17/18 LC72720YVS Sample Application circuit 1 10 μF + Vssa 2 MPXIN 330 pF 3 Vdda 0.1 μF 5 Vssa 6 560 pF 100 kΩ 7 9 VREF SYR MPXIN CE Vdda DI Vssa CL FLOUT DO CIN RDS-ID T1 SYNC 10 T2 Vssd 11 T3 NC NC NC 13 14 15 16 pF Vssd T7 T6 T4 Vssd T5 Vddd XOUT 4.332 MHz XIN 30 SYR 29 Vssd CE 28 DI 26 25 24 22 21 20 Vddd 10 kΩ Vddd 10 kΩ Vddd 10 kΩ DO RDS-ID SYNC NC NC 18 17 CL Vssd 0.1 μF Vddd 16 16 pF Vssd Caution : 1. Determine the value of the DO pin pull-up resistor based on the required serial data transfer speed. 2. A 100-kΩ bias resistor must be connected between the CIN pin and the VREF pin. Note that this resistor is planned to be included internally to the IC in later versions of this product. 3. If the SYR pin is unused, it must be connected to ground. ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No. A2155-18/18