LC75806PTS-T-H

LC75806PTS-T 1/4, 1/3-Duty LCD Driver with Key Input Function Overview The LC75806PTS-T is 1/4 duty and 1/3 duty LCD display driver that can directly drive up to 304 segments and can control up to 9 generalpurpose output ports. This product also incorporates a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. Features  Key input function for up to 30 keys (A key scan is performed only when a key is pressed.)  1/4 duty 1/3 bias and 1/3 duty 1/3 bias drive schemes can be controlled from serial data.  Capable of driving up to 304 segments using 1/4 duty and up to 231 segments using 1/3 duty.  Switching between key scan output and segment output can be controlled from serial data.  The key scan operation enabled/disabled state can be controlled from serial data.  Switching between segment output port and general-purpose output port can be controlled from serial data.  Switching between general-purpose output port, clock output port, and segment output port can be controlled from serial data. (Up to 9 general-purpose output ports and up to one clock output port)  Serial data I/O supports CCB* format communication with the system controller. (Support 3.3 V and 5 V operation)  Sleep mode and all segments off functions that are controlled from serial data.  The frame frequency of the common and segment output waveforms can be controlled from serial data.  Switching between RC oscillator operating mode and external clock operating mode can be controlled from serial data.  Direct display of display data without the use of a decoder provides high generality.  Built-in display contrast adjustment circuit.  Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays.  RES pin provided for forcibly initializing the IC internal circuits. www.onsemi.com TQFP100 14x14 / TQFP100 * Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and the bus addresses are controlled by ON Semiconductor. ORDERING INFORMATION See detailed ordering and shipping information on page 36 of this data sheet. © Semiconductor Components Industries, LLC, 2017 July 2017 - Rev. 1 1 Publication Order Number : LC75806PTS-T/D LC75806PTS-T Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Symbol VDD max Maximum supply voltage VIN1 Conditions Ratings 0.3 to +7.0 VDD 0.3 to +7.0 Unit V VIN2 CE, CL, DI, RES OSC, TEST, VDD1, VDD2, KI1 to KI5 VOUT1 VOUT2 OSC, S1 to S77, COM1 to COM4, KS1 to KS6, P1 to P9 IOUT1 IOUT2 COM1 to COM4 3 IOUT3 KS1 to KS6 1 IOUT4 P1 to P9 5 Allowable power dissipation Pd max Ta = 105C Operating temperature Topr 40 to +105 C Storage temperature Tstg 55 to +125 C Input voltage Output voltage Output current 0.3 to VDD+0.3 0.3 to +7.0 DO 0.3 to VDD+0.3 S1 to S77 300 100 V V A mA mW Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ranges at Ta = 40 to +105C, VSS = 0 V Parameter Symbol VDD Supply voltage Input voltage *1 Conditions VDD1 VDD VDD1 VDD2 VDD2 VIH1 Ratings min typ Unit max 4.5 6.0 2/3VDD0 VDD0 1/3VDD0 VDD0 V V CE, CL, DI, RES 0.4VDD 6.0 VIH2 KI1 to KI5 0.6VDD VDD VIH3 OSC: External clock operating mode 0.4VDD VDD VIL1 CE, CL, DI, RES 0 0.2VDD VIL2 KI1 to KI5 0 0.2VDD VIL3 OSC: External clock operating mode 0 0.2VDD Recommended external resistor for RC oscillation Recommended external capacitor for RC oscillation Guaranteed range of RC oscillation External clock operating frequency ROSC OSC: RC oscillation operating mode 39 kΩ COSC OSC: RC oscillation operating mode 1000 pF fOSC OSC: RC oscillation operating mode fCK External clock duty cycle DCK Data setup time tds OSC: External clock operating mode [Figure4] OSC: External clock operating mode [Figure4] CL, DI [Figure2], [Figure3] 160 ns Data hold time tdh CL, DI [Figure2], [Figure3] 160 ns CE wait time tcp CE, CL [Figure2], [Figure3] 160 ns CE setup time tcs CE, CL [Figure2], [Figure3] 160 ns CE hold time tch CE, CL [Figure2], [Figure3] 160 ns High level clock pulse width tH CL [Figure2], [Figure3] 160 ns Low level clock pulse width tL CL [Figure2], [Figure3] 160 Rise time tr CE, CL, DI [Figure2], [Figure3] 160 ns Fall time tf 160 ns DO output deley time tdc DO rise time tdr CE, CL, DI [Figure2], [Figure3] DO RPU = 4.7 kΩ CL = 10 pF *2 [Figure2], [Figure3] DO RPU = 4.7 kΩ CL = 10 pF *2 [Figure2], [Figure3] Input high level voltage Input low level voltage V V 19 38 76 kHz 10 38 76 kHz 30 50 70 % ns 1.5 s 1.5 s Note: *1. VDD0 = 0.70VDD to VDD *2. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistorRPU and the load capacitance CL. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2 LC75806PTS-T Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Hysteresis VH1 VH2 Power-down detection voltage VDET Input high level current Input low level current Input floating voltage Pull-down resistance Output off leakage current Output high level voltage *1 Output low level voltage Output middle level voltage *1, *3 Oscillator frequency Pin Conditions Ratings min typ 0.03VDD CE, CL, DI, RES 2.0 CE, CL, DI, RES IIH2 OSC IIL1 CE, CL, DI, RES V 0.1VDD KI1 to KI5 IIH1 Unit max VI = 6.0 V VI = VDD : External clock operating mode VI = 0 V VI = 0 V : External clock operating mode IIL2 OSC VIF KI1 to KI5 RPD KI1 to KI5 VDD = 5.0 V IOFFH DO VO = 6.0 V VOH1 VOH2 2.3 2.6 V 5.0 5.0 A 5.0 A 5.0 0.05VDD V 50 100 250 kΩ 6.0 A KS1 to KS6 IO = 500 A VDD1.0 VDD0.5 VDD0.2 P1 to P9 IO = 1 mA VOH3 S1 to S77 IO = 20 A VOH4 COM1 to COM4 IO = 100 A VDD0.9 VDD00.9 VDD00.9 VOL1 VOL2 KS1 to KS6 P1 to P9 IO = 25 A IO = 1 mA VOL3 S1 to S77 IO = 20 A VOL4 COM1 to COM4 IO = 100 A VOL5 DO IO = 1 mA VMID1 S1 to S77 1/3 bias IO = ±20 A VMID2 S1 to S77 1/3 bias IO = ±20 A VMID3 COM1 to COM4 1/3 bias IO = ±100 A VMID4 COM1 to COM4 1/3 bias IO = ±100 A fOSC OSC IDD1 VDD IDD2 VDD Current drain IDD3 VDD ROSC = 39 kΩ, COSC = 1000 pF RC oscillation operating mode Sleep mode VDD = 6.0 V, Output open, RC oscillation operating mode, fOSC = 38 kHz VDD = 6.0 V, Output open, External clock operating mode, fCK = 38 kHz, VIH3 = 0.5VDD, VIL3 = 0.1VDD 0.2 V 0.5 1.5 0.9 0.9 V 0.9 0.1 2/3VDD0 0.9 1/3VDD0 0.9 2/3VDD0 0.9 1/3VDD0 0.9 30.4 0.3 2/3VDD0 +0.9 1/3VDD0 +0.9 2/3VDD0 +0.9 1/3VDD0 +0.9 38 45.6 V kHz 100 1300 2600 A 1400 2800 Note: *1. VDD0 = 0.70VDD to VDD *3. Excluding the bias voltage generation divider resistor built into the VDD0, VDD1, VDD2 and VSS. (See [Figure 1]) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 3 LC75806PTS-T VDD CONTRAST ADJUSTER VDD0 VDD1 To the common and segment drivers VDD2 VSS Excluding these resistors [Figure 1] 1. When CL is stopped at the low level VIH1 CE CL tH VIH1 tL 50% VIL1 tr DI VIL1 tf tcp VIH1 tcs tch VIL1 tdh tds tdc DO D0 tdr D1 [Figure 2] 2. When CL is stopped at the high level VIH1 CE tL tH CL VIH1 50% VIL1 tr tf VIL1 tcp tcs tch VIH1 DI VIL1 tds tdh DO D0 D1 tdc tdr [Figure 3] 3. OSC pin clock timing in external clock operating mode tCKH OSC tCKL VIH3 50% VIL3 1 fCK= t CKH + tCKL [kHz] tCKH DCK= t CKH + tCKL 100[%] [Figure 4] www.onsemi.com 4 LC75806PTS-T COM3 COM4/S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 Pin Assignment 75 51 76 50 COM2 COM1 S75/KS1 S76/KS2 KS3 KS4 KS5 KS6 KI1 KI2 KI3 KI4 KI5 S77/P9 VDD VDD1 VDD2 VSS TEST OSC RES DO CE CL DI S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 LC75806PTS-T 100 26 25 P1/S1 P2/S2 P3/S3 P4/S4 P5/S5 P6/S6 P7/S7 P8/S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 1 www.onsemi.com 5 Top view LC75806PTS-T COMMON DRIVER SEGMENT DRIVER & LATCH P9/S77 S1/P1 S2/P2 S9 S8/P8 S73 COM4/S74 COM3 COM2 COM1 Block Diagram GENERAL PURPOSE PORT VDD CONTRAST ADJUSTER VDD0 VDD1 CONTROL REGISTER VDD2 VSS CLOCK GENERATOR OSC DO SHIFT REGISTER CCB INTERFACE DI CL KEY BUFFER CE RES VDD KEY SCAN VDET www.onsemi.com 6 KS6 KS5 KS4 KS3 S76/KS2 S75/KS1 KI5 KI4 KI3 KI2 KI1 TEST LC75806PTS-T Pin Functions Handling Symbol Pin No. Function Active I/O when unused S1/P1 to S8/P8 1 to 8 S9 to S73 9 to 73 COM1 to COM3 77 to 75 COM4/S74 74 Segment outputs for displaying the display data transferred by serial data input. The S1/P1 to S8/P8 pins can be used as general-purpose output ports - O OPEN - O OPEN - O OPEN H I GND - O OPEN - I/O VDD H I under serial data control. Common driver outputs. The frame frequency is fO[Hz]. The COM4/S74 pin can be used as a segment output in 1/3 duty. Key scan outputs. Although normal key scan timing lines require diodes to KS1/S75 78 KS2/S76 79 KS3 to KS6 80 to 83 be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The KS1/S75 and KS2/S76 pins can be used as segment outputs when so specified by the control data. KI1 to KI5 84 to 88 P9/S77 89 Key scan inputs. These pins have built-in pull-down resistors. General-purpose output port. This pin can be used as clock output port or segment output port under serial data control. Oscillator connections. An oscillator circuit is formed by connecting an OSC 95 external resistor and capacitor at this pin. This pin can also be used as the external clock input pin if the external clock operating mode is selected with the control data. CE 98 Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CL 99 DI 100 DO 97 I CE: Chip enable CL: Synchronization clock DI: Transfer data DO: Output data GND - I - O OPEN L I VDD - I - - I OPEN - I OPEN Reset signal input  RES=Low ···· Display off - S1/P1 to S8/P8, KS1/S75, KS2/S76=Low (These pins are forcibly set to the segment output port function and fixed at the low level.) - S9 to S73=Low - COM1 to COM3=Low - COM4/S74=Low (This pin is forcibly set to the common output function and fixed at the low level.) - P9/S77=Low (This pin is forcibly set to the general-purpose output port function and RES 96 fixed at the low level.) - KS3 to KS6=Low - Key scanning disabled - All the key data is reset to low. - OSC=”Z”(High impedance) - RC oscillation stopped - Inhibits external clock input - Display contrast adjustment circuit stopped.  RES=High ··· Display on - General-purpose output port state setting is enabled - Key scanning is enabled. - RC oscillation enabled (RC oscilltator operating mode) - Enables external clock input (external clock operating mode) - Display contrast adjustment circuit operation is enabled. However, serial data can be transferred when the RES pin is low TEST 94 This pin must be connected to ground. VDD1 91 VDD2 92 VDD 90 Power supply connections. Provide a voltage of between 4.5 to 6.0V. - - - VSS 93 Power supply connections. Connect to ground. - - - LCD drive 2/3 bias voltage (middle level) supply pin. This pin can be used to supply the 2/3 VDD0 voltage level externally. LCD drive 1/3 bias voltage (middle level) supply pin. This pin can be used to supply the 1/3 VDD0 voltage level externally. www.onsemi.com 7 LC75806PTS-T Serial Data Input 1. 1/4 duty (1) When CL is stopped at the low level CE CL DI 0 1 0 0 0 0 1 0 D1 D2 D71 D72 D73 D74 D75 D76 0 0 0 0 OC PC90 PC91 S0 S1 K0 K1 P0 P1 P2 P3 SC KSC 0 DO 0 1 0 0 0 0 1 0 D77 D78 B0 B1 B2 B3 A0 A1 A2 A3 0 1 0 0 0 0 1 0 D153 D154 B0 B1 B2 B3 A0 A1 A2 A3 0 1 0 0 0 0 1 0 D229 D230 B0 B1 B2 B3 A0 A1 A2 A3 D147 D148 D149 D150 D151 D152 0 0 0 0 0 0 Display data (76 bits) 0 0 0 0 0 FC0 FC1 FC2 CT0 CT1 CT2 0 D223 D224 D225 D226 D227 D228 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D299 D300 D301 D302 D303 D304 0 0 0 0 0 0 0 0 0 0 0 0 Fixed data (17 bits) Note: B0 to B3, A0 to A3 ······ CCB address DD ························· Direction data www.onsemi.com 8 0 1 0 1 0 DD (3 bits) Fixed data (17 bits) Display data (76 bits) 0 DD (3 bits) Control data (17 bits) Display data (76 bits) 0 DD (3 bits) Control data (17 bits) Display data (76 bits) B0 B1 B2 B3 A0 A1 A2 A3 0 0 0 0 0 0 1 1 DD (3 bits) LC75806PTS-T (2) When CL is stopped at the high level CE CL DI 0 1 0 0 0 0 1 0 D1 D2 D71 D72 D73 D74 D75 D76 0 0 0 0 OC PC90 PC91 S0 S1 K0 K1 P0 P1 P2 P3 SC KSC 0 Display data (76 bits) B0 B1 B2 B3 A0 A1 A2 A3 Control data (17 bits) DO 0 1 0 0 0 0 1 0 D77 D78 0 1 0 0 0 0 1 0 D153 D154 0 1 0 0 0 0 1 0 0 0 0 0 0 D229 D230 0 0 0 0 0 FC0 FC1 FC2 CT0 CT1 CT2 0 D223 D224 D225 D226 D227 D228 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Fixed data (17 bits) D299 D300 D301 D302 D303 D304 0 0 0 Display data (76 bits) 0 0 0 0 0 0 0 0 0 Fixed data (17 bits) 0 0 1 0 0 0 0 0 0 0 1 1 DD (3 bits)  CCB address ············ “42H”  D1 to D304 ············· Display data  OC ······················· RC oscillator operating mode/external clock operationg mode switching control data  PC90, PC91 ············· General-purpose output port/clock output port/segment output port switching control data  S0, S1 ···················· Sleep control data  K0, K1 ··················· Key scan output/segment output switching control data  P0 to P3 ················· Segment output port/general-purpose output port switching control data  SC ························ Segment on/off control data  KSC ······················ Key scan operation enabled/disabled state setting control data  FC0 to FC2 ············· Common and segment output waveform frame frequency control data  CT0 to CT2 ············· Display contrast setting control data 9 1 DD (3 bits) Note: B0 to B3, A0 to A3 ······ CCB address DD ························· Direction data www.onsemi.com 0 DD (3 bits) Control data (17 bits) Display data (76 bits) B0 B1 B2 B3 A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 D147 D148 D149 D150 D151 D152 0 Display data (76 bits) B0 B1 B2 B3 A0 A1 A2 A3 0 DD (3 bits) LC75806PTS-T 2. 1/3 duty (1) When CL is stopped at the low level CE CL DI 0 1 0 0 0 0 1 0 D1 D2 D71 D72 D73 D74 D75 D76 D77 D78 0 0 OC PC90 PC91 S0 S1 K0 K1 P0 P1 P2 P3 SC KSC 1 Display data (78 bits) B0 B1 B2 B3 A0 A1 A2 A3 Control data (15 bits) DO 0 1 0 0 0 0 1 0 D79 D80 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D149 D150 D151 D152 D153 0 0 0 0 0 0 0 Display data (75 bits) B0 B1 B2 B3 A0 A1 A2 A3 D154 D155 0 0 0 0 0 FC0 FC1 FC2 CT0 CT1 CT2 1 Control data (18 bits) D224 D225 D226 D227 D228 D229 D230 D231 0 Display data (78 bits) 0 0 0 0 0 0 0 0 0 0 Fixed data (15 bits) Note: B0 to B3, A0 to A3 ······ CCB address DD ························· Direction data www.onsemi.com 10 0 0 DD (3 bits) 0 1 DD (3 bits) 0 0 0 0 1 1 0 DD (3 bits) LC75806PTS-T (2) When CL is stopped at the high level CE CL DI 0 1 0 0 0 0 1 0 D1 D2 D71 D72 D73 D74 D75 D76 D77 D78 0 0 OC PC90 PC91 S0 S1 K0 K1 P0 P1 P2 P3 SC KSC 1 Display data (78 bits) B0 B1 B2 B3 A0 A1 A2 A3 Control data (15 bits) DO 0 1 0 0 0 0 1 0 D79 D80 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D149 D150 D151 D152 D153 0 0 0 0 0 0 0 0 Display data (75 bits) B0 B1 B2 B3 A0 A1 A2 A3 D154 D155 0 0 0 0 FC0 FC1 FC2 CT0 CT1 CT2 1 Control data (18 bits) D224 D225 D226 D227 D228 D229 D230 D231 0 Display data (78 bits) 0 0 0 0 0 0 0 0 0 0 Fixed data (15 bits) 0 0 0 0 0 0 1 1 0 DD (3 bits)  CCB address ············ “42H”  D1 to D231 ············· Display data  OC ······················· RC oscillator operating mode/external clock operationg mode switching control data  PC90, PC91 ············· General-purpose output port/clock output port/segment output port switching control data  S0, S1 ···················· Sleep control data  K0, K1 ··················· Key scan output/segment output switching control data  P0 to P3 ················· Segment output port/general-purpose output port switching control data  SC ························ Segment on/off control data  KSC ······················ Key scan operation enabled/disabled state setting control data  FC0 to FC2 ············· Common and segment output waveform frame frequency control data  CT0 to CT2 ············· Display contrast setting control data 11 1 DD (3 bits) Note: B0 to B3, A0 to A3 ······ CCB address DD ························· Direction data www.onsemi.com 0 DD (3 bits) LC75806PTS-T Control Data Functions 1. OC …RC oscillator operating mode/external clock operating mode switching control data This control data bit selects the OSC pin function (RC oscillator operating mode or external clock operating mode) OC OSC pin function 0 RC oscillator operating mode 1 External clock operating mode Note: If RC oscillator operating mode is selected, connect an external resistor ROSC and an external capacitor COSC to the OSC pin. 2. PC90, PC91 … General-purpose output port/clock output port/segment output port switching control data These control data bits switches the functions of the P9/S77 output pin between the general-purpose output port, the clock output port, and the segment output port. Control data PC90 PC91 0 0 The state of P9/S77 output pin General-purpose output port (P9) (”L” level output) 1 0 General-purpose output port (P9) (“H” level output) 0 1 Clock output port (P9) (Clock frequency is fOSC/2 or fCK/2) 1 1 Segment output port (S77) Note: If the sleep mode is set, the P5/S57 output pin can not be used as the clock output port. 3. S0, S1 … Sleep control data These control data bits switch between normal mode and sleep mode, and set the states of the KS1 to KS6 key scan output during key scan standby. OSC pin state Control data (RC oscillator S0 S1 Mode or acceptance of the external clock signal) Output pin states during key scan standby Segment output / Common KS1 KS2 KS3 KS4 KS5 KS6 output 0 0 Normal Operating Operating H H H H H H 0 1 Sleep Stopped L L L L L L H 1 0 Sleep Stopped L L L L L H H 1 1 Sleep Stopped L H H H H H H Note: This assumes that the KS1/S75 and KS2/S76 output pins are selected for key scan output. 4. K0, K1 … Key scan output/segment output switching control data These control data bits switch the functions of the KS1/S75 and KS2/S76 output pins between the key scan output and the segment output. Control data Output pin state Maximum number K0 K1 KS1/S75 KS2/S56 of input keys 0 0 KS1 KS2 30 0 1 S75 KS2 25 1 X S75 S76 20 X : don't care www.onsemi.com 12 Note: KSn (n=1 or 2): Key scan output Sn (n=75 or 76): Segment output LC75806PTS-T 5. P0 to P3 … Segment output port/general-purpose output port switching control data These control data bits switch the functions of the S1/P1 to S8/P8 output pins between the segment output port and the general-purpose output port. Control data Output pin state P0 P1 P2 P3 S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8 0 0 0 0 S1 S2 S3 S4 S5 S6 S7 S8 0 0 0 1 P1 S2 S3 S4 S5 S6 S7 S8 0 0 1 0 P1 P2 S3 S4 S5 S6 S7 S8 0 0 1 1 P1 P2 P3 S4 S5 S6 S7 S8 0 1 0 0 P1 P2 P3 P4 S5 S6 S7 S8 0 1 0 1 P1 P2 P3 P4 P5 S6 S7 S8 0 1 1 0 P1 P2 P3 P4 P5 P6 S7 S8 0 1 1 1 P1 P2 P3 P4 P5 P6 P7 S8 1 0 0 0 P1 P2 P3 P4 P5 P6 P7 P8 Note: Sn (n=1 to 8): Segment output port Pn (n=1 to 8): General-purpose output port The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports. Output pin Correspondence display data 1/4 duty 1/3 duty S1/P1 D1 D1 S2/P2 D5 D4 S3/P3 D9 D7 S4/P4 D13 D10 S5/P5 D17 D13 S6/P6 D21 D16 S7/P7 D25 D19 S8/P8 D29 D22 For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level when the display data D13 is 1, and will output a low level when D13 is 0. 6. SC … Segment on/off control data This control data bit controls the on/off state of the segments. SC Display state 0 On 1 Off However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 7. KSC … Key scan operation enabled/disabled state setting control data This control data bit enables or disables key scan operation. KSC Key scan operating state Key scan operation enabled 0 (A key scan operation is performed if any key on the lines corresponding to KS1 to KS6 pin which is set high is pressed.) Key scan operation disabled 1 (No key scan operation is performed, even if any of the keys in the key matrix are pressed. If this state is set up, the key data is forcibly reset to 0 and the key data read request is also cleared. (DO is set high.)) www.onsemi.com 13 LC75806PTS-T 8. FC0 to FC2 … Common and segment output waveform frame frequency control data These control data bits set the common and segment output waveform frequency. Control data Frame frequency FC0 FC1 FC2 fO[Hz] 1 1 0 fOSC/768, fCK/768 1 1 1 fOSC/576, fCK/576 0 0 0 fOSC/384, fCK/384 0 0 1 fOSC/288, fCK/288 0 1 0 fOSC/192, fCK/192 9. CT0 to CT2 … Display contrast setting control data Set the display contrast with this control data. CT0 to CT2: Sets the display contrast (7 steps) CT0 CT1 CT2 LCD drive 3/3 bias voltage VDD0 level 0 0 0 1.00VDD=VDD-(0.05VDD0) 1 0 0 0.95VDD=VDD-(0.05VDD1) 0 1 0 0.90VDD=VDD-(0.05VDD2) 1 1 0 0.85VDD=VDD-(0.05VDD3) 0 0 1 0.80VDD=VDD-(0.05VDD4) 1 0 1 0.75VDD=VDD-(0.05VDD5) 0 1 1 0.70VDD=VDD-(0.05VDD6) Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it can also be adjusted by modifying the supply pin VDD voltage level. Display Data and Output Pin Correspondence 1. 1/4 duty Output pin COM1 COM2 COM3 COM4 Output pin COM1 COM2 COM3 COM4 S1/P1 D1 D2 D3 D4 S26 D101 D102 D103 D104 S2/P2 D5 D6 D7 D8 S27 D105 D106 D107 D108 S3/P3 D9 D10 D11 D12 S28 D109 D110 D111 D112 S4/P4 D13 D14 D15 D16 S29 D113 D114 D115 D116 S5/P5 D17 D18 D19 D20 S30 D117 D118 D119 D120 S6/P6 D21 D22 D23 D24 S31 D121 D122 D123 D124 S7/P7 D25 D26 D27 D28 S32 D125 D126 D127 D128 S8/P8 D29 D30 D31 D32 S33 D129 D130 D131 D132 S9 D33 D34 D35 D36 S34 D133 D134 D135 D136 S10 D37 D38 D39 D40 S35 D137 D138 D139 D140 S11 D41 D42 D43 D44 S36 D141 D142 D143 D144 S12 D45 D46 D47 D48 S37 D145 D146 D147 D148 S13 D49 D50 D51 D52 S38 D149 D150 D151 D152 S14 D53 D54 D55 D56 S39 D153 D154 D155 D156 S15 D57 D58 D59 D60 S40 D157 D158 D159 D160 S16 D61 D62 D63 D64 S41 D161 D162 D163 D164 S17 D65 D66 D67 D68 S42 D165 D166 D167 D168 S18 D69 D70 D71 D72 S43 D169 D170 D171 D172 S19 D73 D74 D75 D76 S44 D173 D174 D175 D176 S20 D77 D78 D79 D80 S45 D177 D178 D179 D180 S21 D81 D82 D83 D84 S46 D181 D182 D183 D184 S22 D85 D86 D87 D88 S47 D185 D186 D187 D188 S23 D89 D90 D91 D92 S48 D189 D190 D191 D192 S24 D93 D94 D95 D96 S49 D193 D194 D195 D196 S25 D97 D98 D99 D100 S50 D197 D198 D199 D200 Note: This is for the case where the S1/P1 to S8/P8, KS1/S75, KS2/S76, P9/S77 output pins are selected for use as segment outputs. Continued on next page. www.onsemi.com 14 LC75806PTS-T Continued from preceding page. Output pin COM1 COM2 COM3 COM4 Output pin COM1 COM2 COM3 COM4 S51 D201 D202 D203 D204 S64 D253 D254 D255 D256 S52 D205 D206 D207 D208 S65 D257 D258 D259 D260 S53 D209 D210 D211 D212 S66 D261 D262 D263 D264 S54 D213 D214 D215 D216 S67 D265 D266 D267 D268 S55 D217 D218 D219 D220 S68 D269 D270 D271 D272 S56 D221 D222 D223 D224 S69 D273 D274 D275 D276 S57 D225 D226 D227 D228 S70 D277 D278 D279 D280 S58 D229 D230 D231 D232 S71 D281 D282 D283 D284 S59 D233 D234 D235 D236 S72 D285 D286 D287 D288 S60 D237 D238 D239 D240 S73 D289 D290 D291 D292 S61 D241 D242 D243 D244 KS1/S75 D293 D294 D295 D296 S62 D245 D246 D247 D248 KS2/S76 D297 D298 D299 D300 S63 D249 D250 D251 D252 P9/S77 D301 D302 D303 D304 Note: This is for the case where the S1/P1 to S8/P8, KS1/S75, KS2/S76, P9/S77 output pins are selected for use as segment outputs. For example, the table below lists the segment output states for the S11 output pin. Display data Output pin state (S11) D41 D42 D43 D44 0 0 0 0 The LCD segments for COM1, COM2, COM3 and COM4 are off. 0 0 0 1 The LCD segment for COM4 is on. 0 0 1 0 The LCD segment for COM3 is on. 0 0 1 1 The LCD segments for COM3 and COM4 are on. 0 1 0 0 The LCD segment for COM2 is on. 0 1 0 1 The LCD segments for COM2 and COM4 are on. 0 1 1 0 The LCD segments for COM2 and COM3 are on. 0 1 1 1 The LCD segments for COM2, COM3 and COM4 are on. 1 0 0 0 The LCD segment for COM1 is on. 1 0 0 1 The LCD segments for COM1 and COM4 are on. 1 0 1 0 The LCD segments for COM1 and COM3 are on. 1 0 1 1 The LCD segments for COM1, COM3 and COM4 are on. 1 1 0 0 The LCD segments for COM1 and COM2 are on. 1 1 0 1 The LCD segments for COM1, COM2 and COM4 are on. 1 1 1 0 The LCD segments for COM1, COM2 and COM3 are on. 1 1 1 1 The LCD segments for COM1, COM2, COM3 and COM4 are on. www.onsemi.com 15 LC75806PTS-T 2. 1/3 duty Output pin COM1 COM2 COM3 Output pin COM1 COM2 COM3 S1/P1 D1 D2 D3 S40 D118 D119 D120 S2/P2 D4 D5 D6 S41 D121 D122 D123 S3/P3 D7 D8 D9 S42 D124 D125 D126 S4/P4 D10 D11 D12 S43 D127 D128 D129 S5/P5 D13 D14 D15 S44 D130 D131 D132 S6/P6 D16 D17 D18 S45 D133 D134 D135 S7/P7 D19 D20 D21 S46 D136 D137 D138 S8/P8 D22 D23 D24 S47 D139 D140 D141 S9 D25 D26 D27 S48 D142 D143 D144 S10 D28 D29 D30 S49 D145 D146 D147 S11 D31 D32 D33 S50 D148 D149 D150 S12 D34 D35 D36 S51 D151 D152 D153 S13 D37 D38 D39 S52 D154 D155 D156 S14 D40 D41 D42 S53 D157 D158 D159 S15 D43 D44 D45 S54 D160 D161 D162 S16 D46 D47 D48 S55 D163 D164 D165 S17 D49 D50 D51 S56 D166 D167 D168 S18 D52 D53 D54 S57 D169 D170 D171 S19 D55 D56 D57 S58 D172 D173 D174 S20 D58 D59 D60 S59 D175 D176 D177 S21 D61 D62 D63 S60 D178 D179 D180 S22 D64 D65 D66 S61 D181 D182 D183 S23 D67 D68 D69 S62 D184 D185 D186 S24 D70 D71 D72 S63 D187 D188 D189 S25 D73 D74 D75 S64 D190 D191 D192 S26 D76 D77 D78 S65 D193 D194 D195 S27 D79 D80 D81 S66 D196 D197 D198 S28 D82 D83 D84 S67 D199 D200 D201 S29 D85 D86 D87 S68 D202 D203 D204 S30 D88 D89 D90 S69 D205 D206 D207 S31 D91 D92 D93 S70 D208 D209 D210 S32 D94 D95 D96 S71 D211 D212 D213 S33 D97 D98 D99 S72 D214 D215 D216 S34 D100 D101 D102 S73 D217 D218 D219 S35 D103 D104 D105 COM4/S74 D220 D221 D222 S36 D106 D107 D108 KS1/S75 D223 D224 D225 S37 D109 D110 D111 KS2/S76 D226 D227 D228 S38 D112 D113 D114 P9/S77 D229 D230 D231 S39 D115 D116 D117 Note: This is for the case where the S1/P1 to S8/P8, KS1/S75, KS2/S76, P9/S77 output pins are selected for use as segment outputs. www.onsemi.com 16 LC75806PTS-T For example, the table below lists the segment output states for the S11 output pin. Display data Output pin state (S11) D31 D32 D33 0 0 0 The LCD segments for COM1, COM2, and COM3 are off. 0 0 1 The LCD segment for COM3 is on. 0 1 0 The LCD segment for COM2 is on. 0 1 1 The LCD segments for COM2 and COM3 are on. 1 0 0 The LCD segment for COM1 is on. 1 0 1 The LCD segments for COM1 and COM3 are on. 1 1 0 The LCD segments for COM1 and COM2 are on. 1 1 1 The LCD segments for COM1, COM2 and COM3 are on. Serial Data Output 1. When CL is stopped at the low level CE CL DI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 DO X KD1 KD2 KD27 KD28 KD29 KD30 SA Output data X: don’t care Note: B0 to B3, A0 to A3 … CCB address 2. When CL is stopped at the high level CE CL DI DO 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 X KD1 KD2 KD3 KD28 KD29 KD30 SA Output data Note: B0 to B3, A0 to A3 … CCB address X X: don’t care  CCB address ···· “43H”  KD1 to KD30 ··· Key data  SA ················ Sleep acknowledge data Note: If a key data read operation is executed when DO is high (DO does not generate a key data read request output), the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. www.onsemi.com 17 LC75806PTS-T Output Data 1. KD1 to KD30 … Key data When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. KI1 KI2 KI3 KI4 KI5 KS1/S75 KD1 KD2 KD3 KD4 KD5 KS2/S76 KD6 KD7 KD8 KD9 KD10 KS3 KD11 KD12 KD13 KD14 KD15 KS4 KD16 KD17 KD18 KD19 KD20 KS5 KD21 KD22 KD23 KD24 KD25 KS6 KD26 KD27 KD28 KD29 KD30 When the KS1/S75 and KS2/S76 output pins are selected to be segment outputs by control data bits K0 and K1 and a key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0. 2. SA … Sleep acknowledge data This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep mode and 0 in normal mode. Sleep Mode Functions Sleep mode is set up by setting S0 or S1 in the control data to 1. When sleep mode is set up, both the segment and common outputs will go to the low level. In RC oscillator operating mode (OC = 0), the oscillator on the OSC pin will stop (although it will operate during key scan operations), and in external clock operating mode (OC = 1), acceptance of the external clock signal on the OSC pin will stop (although the clock signal will be accepted during key scan operations). Thus this mode reduces power consumption. However, the S1/P1 to S8/P8, P9/S77 output pins can be used as general-purpose output ports under control of the P0 to P3, PC90 and PC91 bits in the control data even in sleep mode (The P9/S77 output pin can not be used as clock output port). Sleep mode is cancelled by setting both S0 and S1 in control data to 0. Key Scan Operation Functions 1. Key scan timing The key scan period is 288T[s]. To reliably determine the on/off state of the keys, the LC75806PTS-T scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 615T[s] after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the keys again. Thus the LC75806PTS-T cannot detect a key press shorter than 615T[s]. KS1 *4 KS2 *4 KS3 *4 KS4 *4 KS5 *4 1 *4 1 2 *4 2 3 *4 3 4 *4 4 5 6 KS6 Key on *4 5 6 576T[s] Note: *4. These are set to the high or low level by the S0 and S1 bits in the control data. Key scan output signals are not output from pins that are set to the low level. www.onsemi.com 18 1 1 T= f = OSC fCK LC75806PTS-T 2. Normal mode, when key scan operations are enabled (1) The KS1 to KS6 pins are set high. (See the description of the control data.) (2) When a key is pressed, a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. (3) If a key is pressed for longer than 615T[s] (Where T = 1/fOSC or T = 1/fCK), the LC75806PTS-T outputs a key data read request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. (4) After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75806PTS-T performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10k). Key input 1 Key input 2 Key scan 615T[s] 615T[s] CE Serial data transfer (KSC=0) Serial data transfer (KSC=0) Key address(43H) 615T[s] Serial data transfer (KSC=0) Key address Key address DI DO Key data read Key data read request Key data read Key data read Key data read request Key data read request 1 1 T= f = OSC fCK 3. Sleep mode, when key scan operations are enabled (1) The KS1 to KS6 pins are set to high or low level by the S0 and S1 bits in the control data. (See the description of the control data.) (2) If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pins starts in RC oscillator operating mode (the IC starts accepting the external clock signal in external clock operating mode) and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. (3) If a key is pressed for longer than 615T[s] (Where T = 1/fOSC or T = 1/fCK), the LC75806PTS-T outputs a key data read request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. (4) After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75806PTS-T performs another key scan. However, this does not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ). (5) Sleep mode key scan example Example: S0=0, S1=1 (Sleep with only KS6 high) “L” KS1 “L” KS2 When any one of these keys is pressed, the oscillator on the OSC pins starts in RC oscillator operating mode (the IC starts accepting the external clock signal in external clock operating mode) and a key scan operation is performed. “L” KS3 “L” KS4 “L” KS5 “H” KS6 *5 KI1 KI2 KI3 KI4 KI5 Note: *5. These diodes are required to reliably recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. www.onsemi.com 19 LC75806PTS-T Key input (KS6 line) Key scan 615T[s] 615T[s] CE Serial data transfer (KSC=0) Serial data transfer (KSC=0) Key Serial data transfer address(43H) (KSC=0) Key address 1 1 T= f = OSC fCK DI DO Key data read Key data read request Key data read Key data read request 4. Normal/sleep mode, when key scan operations are disabled (1) The KS1 to KS6 pins are set to high or low level by the S0 and S1 bits in the control data. (2) No key scan operation is performed, whichever key is pressed. (3) If the key scan disabled state (KSC = 1 in the control data) is set during a key scan, the key scan is stopped. (4) If the key scan disabled state (KSC = 1 in the control data) is set when a key data read request (a low level on DO) is output to the controller, all the key data is set to 0 and the key data read request is cleared (DO is set high). Note that DO, being an open-drain output, requires a pull-up resister (between 1 to 10 k). (5) The key scan disabled state is cleared by setting KSC in the control data to 0. Key input 1 Key input 2 Key scan 615T[s] 615T[s] CE Serial data transfer (KSC=0) Serial data transfer (KSC=1) Serial data transfer (KSC=0) Serial data transfer (KSC=1) Serial data transfer (KSC=0) Key Address(43H) DI DO Key data read request Key data read Key data read request 1 1 T= f = OSC fCK Multiple Key Presses Although the LC75806PTS-T is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. www.onsemi.com 20 LC75806PTS-T fO[Hz] 1/4 Duty, 1/3 Bias Drive Technique VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V COM1 COM2 COM3 COM4 LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are turned off. LCD driver output when only LCD segments corresponding to COM1 are on. LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when LCD segments corresponding to COM1, COM2, and COM3 are on. LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, COM3, and COM4 are on. Control data Common and segment output waveform FC0 FC1 FC2 frame frequency fO[Hz] 1 1 0 fOSC/768, fCK/768 1 1 1 fOSC/576, fCK/576 0 0 0 fOSC/384, fCK/384 0 0 1 fOSC/288, fCK/288 0 1 0 fOSC/192, fCK/192 www.onsemi.com 21 LC75806PTS-T 1/3 Duty, 1/3 Bias Drive Technique fO[Hz] VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V VDD0 VDD1 VDD2 0V COM1 COM2 COM3 LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off. LCD driver output when only LCD segments corresponding to COM1 are on. LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on. Control data Common and segment output waveform FC0 FC1 FC2 frame frequency fO[Hz] 1 1 0 fOSC/768, fCK/768 1 1 1 fOSC/576, fCK/576 0 0 0 fOSC/384, fCK/384 0 0 1 fOSC/288, fCK/288 0 1 0 fOSC/192, fCK/192 www.onsemi.com 22 LC75806PTS-T Clock Signal Output Waveform Control data PC90 PC91 0 1 The state of P9/S77 output pin Clock output port (P9) (Clock frequency is fOSC/2 or fCK/2) P9 1 Tc= fc Tc/2 Tc Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when power is first applied and when the voltage drops, i.e., when the power supply voltage is less than or equal to the power down detection voltage VDET, which is 2.3 V, typical. To assure that this function operates reliably, a capacitor must be added to the power supply line so that the power supply voltage VDD rise time when the power is first applied and the power supply voltage VDD fall time when the voltage drops are both at least 1ms. (See Figure 5 and Figure 6.) System Reset The LC75806PTS-T supports the reset methods described below. When a system reset is applied, display is turned off, key scanning is stopped, all the key data is reset to low, and the general-purpose output ports are fixed at the low level (The S1/P1 to S8/P8 pins are forcibly set to the segment output port function and fixed at the low level. The P9/S77 pin is forcibly set to the general-purpose output port function and fixed at the low level). When the reset is cleared, display is turned on, key scanning is enabled and the general-purpose output ports state setting is enabled. 1. Reset methods (1) Reset method by the voltage detection type reset circuit (VDET) If at least 1ms is assured as the supply voltage VDD rise time when power is applied, a system reset will be applied by the VDET output signal when the supply voltage is brought up. If at least 1 ms is assured as the supply voltage VDD fall time when power drops, a system reset will be applied in the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (1/4 duty: the display data D1 to D304 and the control data, 1/3 duty: the display data D1 to D231 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has been transferred. (See Figure 5 and Figure 6.)  1/4 duty t1 VDD t2 VDET VDET CE D1 to D76 Internal data OC, PC90, PC91, S0, S1, K0, K1, P0 to P3, SC, KSC VIL1 Display and control data transfer Undefined Defined Undefined Internal data D77 to D152, FC0 to FC2, CT0 to CT2 Undefined Defined Undefined Internal data (D153 to D228) Undefined Defined Undefined Internal data (D229 to D304) Undefined Defined Undefined System reset period Note: t11 [ms](Power supply voltage VDD rise time) t21 [ms](Power supply voltage VDD fall time) [Figure 5] www.onsemi.com 23 LC75806PTS-T  1/3 duty t1 VDD t2 VDET VDET VIL1 CE Display and control data transfer D1 to D78 Internal data OC, PC90, PC91, S0, S1, K0, K1, P0 to P3, SC, KSC Undefined Defined Undefined Internal data D79 to D153, FC0 to FC2, CT0 to CT2 Undefined Defined Undefined Internal data (D154 to D231) Undefined Defined Undefined System reset period Note: t11 [ms](Power supply voltage VDD rise time) t21 [ms](Power supply voltage VDD fall time) [Figure 6] (2) Reset method by the RES pin When power is applied, a system reset is applied by setting the RES pin low level. The reset is cleared by setting the RES pin high level after all the serial data (1/4 duty: the display data D1 to D304 and the control data, 1/3 duty: the display data D1 to D231 and the control data) has been transferred. In the allowable operating range (VDD = 4.5 to 6.0 V), A reset is applied by setting the RES pin low level. and the reset is cleared by setting the RES pin high level. 2. Internal block states during the reset period  CLOCK GENERATOR A reset is applied and either the OSC pin oscillator is stopped or external clock reception is stopped  COMMON DRIVER, SEGMENT DRIVER & LATCH A reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.  CONTRAST ADJUSTER A reset is applied and the display contrast adjustment circuit operation is disabled.  KEY SCAN A reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.  KEY BUFFER A reset is applied and all the key data is set to low.  GENERAL PURPOSE PORT A reset is applied, the circuit is set to the initial state.  CCB INTERFACE, SHIFT REGISTER, CONTROL REGISTER Since serial data transfer is possible, these circuits are not reset. www.onsemi.com 24 COMMON DRIVER P9/S77 S1/P1 S2/P2 S8/P8 S9 S73 COM4/S74 COM3 COM2 COM1 LC75806PTS-T GENERAL PURPOSE PORT SEGMENT DRIVER & LATCH VDD CONTRAST ADJUSTER VDD0 VDD1 CONTROL REGISTER VDD2 VSS CLOCK GENERATOR OSC DO SHIFT REGISTER CCB INTERFACE DI CL KEY BUFFER CE RES VDD KEY SCAN VDET Blocks that are reset www.onsemi.com 25 S75/KS1 KS3 S76/KS2 KS4 KS5 KS6 KI1 KI2 KI3 KI4 KI5 TEST LC75806PTS-T 3. Pin states during the reset period Pin State during reset S1/P1 to S8/P8 L *6 S9 to S73 L COM1 to COM3 L COM4/S74 L *7 KS1/S75, KS2/S76 L *6 KS3 to KS6 L *8 P9/S77 L *9 OSC Z *10 DO H *11 Note: *6. These output pins are forcibly set to the segment output function and held low. *7. This output pin is forcibly set to the common output function and held low. *8. These output pins are forcibly held fixed at the low level. *9. This output pin is forcibly set to the general-purpose output port function and held low. *10. This I/O pin is forcibly set to the high-impedance state. *11.Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 k is required. This pin remains high during the reset period even if a key data read operation is performed. Notes on the OSC Pin Peripheral Circuit 1. RC oscillator operating mode (Control data bit OC = 0) When RC oscillator operating mode is selected, an external resistor ROSC and an external capacitor COSC must be connected between the OSC pin and GND. OSC ROSC COSC 2. External clock operating mode (Control data bit OC = 1 ) When selecting the external clock operating mode, connect a current protection resistor Rg (4.7 to 47 k) between the OSC pin and the external clock output pin (external oscillator). Determine the value of the resistance according to the maximum allowable current value of the external clock output pin. Also make sure that the waveform of the external clock is not excessively distorted. External clock output pin External oscillator OSC Rg Note: Allowable current value at external clock output pin  www.onsemi.com 26 VDD Rg LC75806PTS-T Sample Application Circuit 1 1/4 duty, 1/3 bias (P1) (P2) (P8) P9 OSC *14 VDD *12 COM1 COM2 COM3 VSS S74/COM4 TEST P1/S1 P2/S2 P8/S8 S9 VDD1 VDD2 C0.047F C S73 C (S75) (S76) RES *13 *16 From the controller CE CL DI *16 To the controller To the controller power supply DO Used with the backlight controller or other circuit. KK K K K I I I I I 5 4 3 2 1 S 7 6 / K K K K K S S S S S 6 5 4 3 2 S 7 5 / K S 1 P9/S77 (S77) LCD panel (up to 304 segments) +5V (General-purpose output port) *15 Key matrix (up to 30 keys) Note: *12. Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75806PTS-T is reset by the VDET. *13. If the RES pin is not used for system reset, it must be connected to the power supply VDD. *14. When RC oscillator operating mode is used, the external resistor ROSC and the external capacitor COSC must be connected between the OSC pin and GND, and when external clock operating mode is selected the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *15. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *16. The pins to be connected to the controller (CE, CL, DI, DO, RES) can handle 3.3 V or 5 V. www.onsemi.com 27 LC75806PTS-T Sample Application Circuit 2 1/3 duty, 1/3 bias (P1) (P2) (P8) P9 OSC *14 VDD *12 COM1 COM2 COM3 VSS TEST P1/S1 P2/S2 P8/S8 S9 VDD1 S73 VDD2 C0.047F C C CE CL DI *16 To the controller To the controller power supply COM4/S74 RES *13 *16 From the controller DO Used with the backlight controller or other circuit. K K K K K I I I I I 5 4 3 2 1 S 7 6 / K K K K K S S S S S 6 5 4 3 2 S 7 5 / K S 1 P9/S77 (S75) (S76) (S77) LCD panel (up to 231 segments) +5V (General-purpose output port) *15 Key matrix (up to 30 keys) Note: *12. Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75806PTS-T is reset by the VDET. *13. If the RES pin is not used for system reset, it must be connected to the power supply VDD. *14. When RC oscillator operating mode is used, the external resistor ROSC and the external capacitor COSC must be connected between the OSC pin and GND, and when external clock operating mode is selected the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *15. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *16. The pins to be connected to the controller (CE, CL, DI, DO, RES) can handle 3.3 V or 5 V. Notes on Transferring Display Data from The Controller When using the LC75806PTS-T in 1/4 duty, applications transfer the display data (D1 to D304) in four operations, and in 1/3 duty, they transfer the display data (D1 to D231) in three operations. In either case, applications should transfer all of the display data within 30 ms to maintain the quality of displayed image. www.onsemi.com 28 LC75806PTS-T Notes on the Controller Key Data Read Techniques 1. Timer based key data acquisition (1) Flowchart CE=”L” NO DO=”L” YES Key data read processing (2) Timing chart Key on Key on Key input Key scan t3 t4 t3 t3 CE t6 Key address DI t5 t6 t6 t5 Key data read t5 DO Key data read request t7 Controller determination (Key on) t7 Controller determination (Key on) t7 Controller determination (Key off) t7 Controller determination (Key on) Controller determination (Key off) t3 ····· Key scan execution time when the key data agreed for two key scans. (615T[s]) t4 ····· Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T[s]) 1 1 t5 ····· Key address (43H) transfer time T= f = OSC fCK t6 ····· Key data read time (3) Explanation In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t7 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t7 in this technique must satisfy the following condition. t7>t4+t5+t6 If a key data read operation is executed when DO is high (DO does not generate a key data read request output), the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. www.onsemi.com 29 LC75806PTS-T 2. Interrupt based key data acquisition (1) Flowchart CE=”L” NO DO=”L” YES Key data read processing Wait for at least t8 CE=”L” NO DO=”H” YES Key OFF (2) Timing chart Key on Key on Key input Key scan t3 t4 t3 t3 CE t6 Key address DI t5 t6 t6 t5 Key data read t6 t5 t5 DO Key data read request Controller determination (Key on) t8 Controller determination (Key off) Controller determination (Key on) t8 t8 t8 Controller determination (Key on) Controller determination (Key on) Controller determination (Key off) t3 ····· Key scan execution time when the key data agreed for two key scans. (615T[s]) t4 ····· Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T[s]) 1 1 T= f = t5 ····· Key address (43H) transfer time OSC fCK t6 ····· Key data read time (3) Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t8 has elapsed by checking the DO state when CE is low and reading the key data. The period t8 in this technique must satisfy the following condition. t8>t4 If a key data read operation is executed when DO is high (DO does not generate a key data read request output), the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. www.onsemi.com 30 LC75806PTS-T About Data Communication Method with The Controller 1. About data communication method of 4 line type CCB format The 4 line type CCB format is the data communication method of before. The LC75806PTS-T must connect to the controller as followings. *17 *18 (INT) Rup Note: *17. Connect the pull-up resistor Rup. Select a resistance (between 1 to 10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. DI LC75806PTS-T *18. The (INT) pin is an input port for the key data read request CL signal (a low level on DO) detection. CE DI Controller DO DO CL CE 2. About data communication method of 3 line type CCB format The 3 line type CCB format is the data communication method that made a common use of the data input DI in the data output DO. The LC75806PTS-T must connect to the controller as followings. *18 (INT) *17 Rup CL Note: *17. Connect the pull-up resistor Rup. Select a resistance (between 1 to 10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. DI LC75806PTS-T *18. The (INT) pin is an input port for the key data read request CL signal (a low level on DO) detection. CE CE DIO DO Controller In this case, Applications must transfer the data communication start command before the serial data input (CCB address “42H”, display data and control data transfer) or serial data output (CCB address “43H” transfer, key data read) to avoid the collision of the data input signal DI and the data output signal DO. Then applications must transfer the data communication stop command when the controller wants to detect the key data read request signal (a low level on DO) during a movement stop of the serial data input and the serial data output. 1 Data communication start command (1) When CL is stopped at the low level (2) When CL is stopped at the high level CE CE CL CL DI/DO 0 0 0 0 0 0 0 0 0 CCB address “00H” DI/DO 0 1 1 0 1 1 1 Command data CE CL CL 1 0 0 1 1 0 1 1 1 Command data (2) When CL is stopped at the high level CE 0 0 0 0 0 0 0 0 CCB address “00H” 0 CCB address “00H” 2 Data communication stop command (1) When CL is stopped at the low level DI/DO 0 0 0 0 0 0 0 1 0 0 0 1 1 1 Command data DI/DO 0 0 0 0 0 0 0 CCB address “00H” www.onsemi.com 31 0 1 1 0 0 0 1 1 1 Command data LC75806PTS-T Data Communication Flowchart of 4 Line Type or 3 Line Type CCB Format 1. Flowchart of the initial setting when power is turned on. Power on (Applications must observe that the power supply VDD rise time is at least 1ms.) Power supply stability (Applications must wait till the level of the power supply is stable) Serial data input (Display and control data transfer) Note: The flowchart of initial setting when power is turned on is same regardless of the 4 line type or 3 line type CCB format. Take explanation about "system reset" into account. System reset clear (Display on, Key scanning is enabled, General-purpose output port state setting are enabled) 2. Flowchart of the serial data input Data communication start command transfer *19 Serial data input (Display and control data transfer) NO The controller wants to detect the key data read request signal (a low level on DO). Note: *19. In the case of the 4 line type CCB format, the transfers of data communication start command and data communication stop command are unnecessary, and, in the case of the 3 line type CCB format, these transfers are necessary. YES Data communication stop command transfer *19 3. Flowchart of the serial data output NO The controller acknowledges the key data read request (When the CE is low, the DO is low) Note: *20. In the case of the 4 line type CCB format, the transfer of data communication start command is unnecessary, and, in the case of the 3 line type CCB format, the transfer is necessary. *21. Because the serial data output has the role of the data communication stop command, it is not necessary to transfer the data communication stop command some other time. YES Data communication start command transfer *20 Serial data output (Key data and sleep acknowledge data read) *21 www.onsemi.com 32 LC75806PTS-T Timing Chart of 4 Line Type and 3 Line Type CCB Format 1. Timing chart of 4 line type CCB format Example 1 Key on Key off Key input Key scan Key scan execution *22 CE CCB address (42H) DI CCB address CCB address (42H) (42H) Key scan execution *22 CCB address (42H) CCB address (43H) DO Serial data input (Display and control data transfer) Serial data output (Key data read) Key data read request Key data read request Example 2 Key input Key off Key off Key on Key on Key scan Key scan execution *22 Key scan execution *22 CE DI CCB address (42H) CCB address CCB address (42H) (42H) CCB address (43H) CCB address (42H) CCB address (43H) DO Serial data input (Display and control data tranfer) Serial data output (Key data read) Key data read request Serial data output (Key data read) Key data read request Example 3 Key on Key input Key off Key off Key scan CE Key scan execution *22 Key scan execution *22 CCB address CCB address CCB address CCB address (42H) (42H) (42H) (42H) DI CCB address (43H) CCB address (43H) DO Key data read request Serial data input (Display and control data transfer) Serial data output (Key data read) Key data read request Note: *22. When the key data agrees for two key scans, the key scan execution time is 615T[s]. And, when the key data does not agree for two key scans and the key scan is executed again, the key scan execution time is 1230T[s]. www.onsemi.com 33 Serial data output (Key data read) 1 1 T= f = OSC fCK LC75806PTS-T 2. Timing chart of 3 line type CCB format Example 1 Key on Key off Key input Key scan Key scan execution *22 CE CCB address (42H) DI/DO Data communication start command CCB address (42H) CCB address (42H) CCB address (42H) CCB address (43H) Data communication start command Data communication stop command Serial data input (Display and control data transfer) Key scan execution *22 Key data read request Serial data output (Key data read) Key data read request Example 2 Key on Key on Key off Key input Key off Key scan Key scan execution *22 Key scan execution *22 CE CCB address (42H) DI/DO Data communication start command CCB address (42H) CCB address CCB address (42H) (42H) Serial data input (Display and control data transfer) CCB address (43H) Data communication stop command Data communication start command Key data read request CCB address (43H) Serial data Data output communication (Key data start command read) Key data read request Serial data output (Key data read) Example 3 Key on Key input Key off Key off Key scan CE Key scan execution *22 Key scan execution *22 CCB address (42H) DI/DO Data communication start command CCB address CCB address CCB address (42H) (42H) (42H) Serial data input (Display and control data transfer) Key data read request CCB address (43H) Serial data output (Key data read) CCB address (43H) Data communication start command Key data read request Note: *22. When the key data agrees for two key scans, the key scan execution time is 615T[s]. And, when the key data does not agree for two key scans and the key scan is executed again, the key scan execution time is 1230T[s]. www.onsemi.com 34 Serial data output (Key data read) 1 1 T= f = OSC fCK LC75806PTS-T Package Dimensions unit : mm TQFP100 14x14 / TQFP100 CASE 932AY ISSUE A 0.50.2 16.00.2 16.00.2 100 14.00.1 14.00.1 1 2 0.5 0.125 0.2 0.10 (1.0) 0 to 10 0.10.1 1.2 MAX (1.0) 0.10 SOLDERING FOOTPRINT* GENERIC MARKING DIAGRAM* 15.40 XXXXXXXX YMDDD 15.40 (Unit: mm) XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 0.50 0.28 1.00 *This information is generic. Please refer to device data sheet for actual part marking. NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 35 LC75806PTS-T ORDERING INFORMATION Device LC75806PTS-T-H Package Shipping (Qty / Packing) TQFP100 14x14 / TQFP100 (Pb-Free / Halogen Free) 450 / Tray JEDEC ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. www.onsemi.com 36