LC75812PT-8565-H

LC75812PT 1/8, 1/9-Duty Dot Matrix LCD Controller / Driver with Key Input Function www.onsemi.com Overview The LC75812PT is 1/8, 1/9 duty dot matrix LCD display controllers/drivers that support the display of characters, numbers, and symbols. In addition to generating dot matrix LCD drive signals based on data transferred serially from a microcontroller, the LC75812PT also provide on-chip character display ROM and RAM to allow display systems to be implemented easily. These products also provide up to 3 general-purpose output ports and incorporate a key scan circuit that accepts input from up to 35 keys to reduce printed circuit board wiring. Features Key input function for up to 35 keys (A key scan is performed only when a key is pressed.) Controls and drives a 57 or 58 dot matrix LCD. Supports accessory display segment drive (up to 65 segments) Display technique: 1/8 duty 1/4 bias drive (57 dots) 1/9 duty 1/4 bias drive (58 dots) Display digits: 13 digits1 line (57 dots), 12 digits1 line (58 dots) Display control memory CGROM: 240 characters (57 or 58 dots) CGRAM: 16 characters (57 or 58 dots) ADRAM: 135 bits DCRAM: 528 bits Instruction function Display on/off control Display shift function Sleep mode can be used to reduce current drain. Built-in display contrast adjustment circuit Switching between key scan output and general-purpose output ports can be controlled with instructions. PWM output for adjusting the LED backlight brightness The frame frequency of the common and segment output waveforms can be controlled by instructions. Serial data control of switching between the RC oscillator operating mode and external clock operating mode. Independent LCD driver block power supply VLCD A voltage detection type reset circuit is provided to initialize the IC and prevent incorrect display. The INH pin is provided. This pin turns off the display, disables key scanning, and forces the general-purpose output ports to the low level. RC oscillator circuit TQFP100 14x14 / TQFP100 * Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and the bus addresses are controlled by ON Semiconductor. ORDERING INFORMATION See detailed ordering and shipping information on page 55 of this data sheet. © Semiconductor Components Industries, LLC, 2017 June 2017 - Rev. 1 1 Publication Order Number : LC75812PT/D LC75812PT Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum supply voltage Symbol Conditions Ratings Unit VDD max VDD 0.3 to +4.2 VLCD max VLCD 0.3 to +11.0 VIN1 CE, CL, DI, INH Input voltage V 0.3 to +4.2 CE, CL, DI, INH 0.3 to +6.5 VDD=2.7 to 3.6V V 0.3 to VDD +0.3 0.3 to VLCD +0.3 VIN2 OSC, KI1 to KI5, TEST VIN3 VLCD1, VLCD2, VLCD3, VLCD4 VOUT1 VOUT2 OSC, KS1 to KS7, P1 to P3 VOUT3 VLCD0, S1 to S65, COM1 to COM9 IOUT1 S1 to S65 IOUT2 COM1 to COM9 3 IOUT3 KS1 to KS7 1 IOUT4 P1 to P3 5 Allowable power dissipation Pd max Ta = 85C Operating temperature Topr 40 to +85 C Storage temperature Tstg 55 to +125 C Output voltage Output current DO -0.3 to +6.5 0.3 to VDD +0.3 V 0.3 to VLCD +0.3 300 200 A mA mW Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Range at Ta = 40C to +85C, VSS = 0 V Parameter Supply voltage Symbol Conditions VDD VDD VLCD Output voltage VLCD0 VLCD When the display contrast adjustment circuit is used. VLCD When the display contrast adjustment circuit is not used. VLCD0 Input voltage VLCD1 VLCD1 VLCD2 VLCD3 Input high level voltage Input low level voltage VLCD4 VIH1 VIH2 VIH3 VIL1 VIL2 Ratings min typ max 2.7 3.6 7.0 10.0 unit V 4.5 10.0 VLCD4 +4.5 VLCD VLCD2 VLCD3 3/4 (VLCD0 VLCD4) VLCD0 2/4 (VLCD0 VLCD4) VLCD0 1/4 (VLCD0 VLCD4) VLCD0 VLCD4 CE, CL, DI, INH 0 0.8VDD 1.5 CE, CL, DI, INH VDD = 2.7 to 3.6 V OSC external clock operating mode KI1 to KI5 0.8VDD 5.5 0.8VDD 0.6VDD VDD VDD CE, CL, DI, INH, KI1 to KI5 OSC external clock operating mode 0 0.2VDD 0 0.2VDD V V 3.6 V V Continued on next page. www.onsemi.com 2 LC75812PT Continued from preceding page. Parameter Symbol Output pull-up voltage Recommended external resistor for RC oscillation Recommended external capacitor for RC oscillation Guaranteed range of RC oscillation External clock operating frequency External clock duty cycle Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width DO output delay time VOUP Rosc DO OSC RC oscillator operating mode Cosc OSC RC oscillator operating mode Ratings typ min 0 fosc OSC RC oscillator operating mode fCK OSC external clock operating mode [Figure 4] DCK tds tdh tcp tcs tch tH OSC external clock operating mode [Figure 4] CL, DI [Figure 2],[Figure 3] CL, DI [Figure 2],[Figure 3] CE, CL [Figure 2],[Figure 3] CE, CL [Figure 2],[Figure 3] CE, CL [Figure 2],[Figure 3] CL [Figure 2],[Figure 3] tL CL tdc DO RPU = 4.7 kΩ CL = 10 pF *1 [Figure 2],[Figure 3] DO RPU = 4.7 kΩ CL = 10 pF *1 [Figure 2],[Figure 3] tdr DO rise time Conditions [Figure 2],[Figure 3] max 5.5 unit V 10 kΩ 470 pF 150 300 600 kHz 100 300 600 kHz 30 160 160 160 160 160 50 70 % ns ns ns ns ns 160 ns 160 ns 1.5 s 1.5 s Note: *1. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance CL. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Hysteresis VH Power-down detection voltage Input high level current VDET IIH1 Pins Conditions Ratings typ min CE, CL, DI, INH, KI1 to KI5 0.1VDD 2.0 CE, CL, DI, INH VI = 3.6 V VI = 5.5 V VDD = 2.7 to 3.6 V VI = VDD external clock operating mode VI = 0 V 2.4 5.0 OSC Input low level current IIL1 IIL2 CE, CL, DI, INH OSC Input floating voltage Pull-down resistance Output off leakage current Output high level voltage VIF KI1 to KI5 RPD KI1 to KI5 VDD = 3.3 V IOFFH DO VO = 5.5 V VOH1 S1 to S65 IO = 20 A VOH2 COM1 to COM9 IO = 100 A VLCD00.6 VLCD00.6 VOH3 KS1 to KS7 IO = 250 A VDD0.8 VOH4 VOL1 P1 to P3 IO = 1 mA VDD0.9 S1 to S65 IO = 20 A VOL2 COM1 to COM9 IO = 100 A VOL3 KS1 to KS7 VOL4 VOL5 P1 to P3 DO IO = 12.5 A IO = 1 mA IO = 1 mA VI = 0 V external clock operating mode 2.2 V V 5.0 IIH2 Output low level voltage unit max A 5.0 5.0 A 5.0 50 100 VDD0.4 0.05VDD V 250 kΩ 6.0 A VDD0.1 V VLCD4+0.6 VLCD4+0.6 0.1 0.4 1.2 0.1 0.9 0.3 V Continued on next page. www.onsemi.com 3 LC75812PT Continued from preceding page. Parameter Output middle level voltage *2 Symbol Pins Conditions VMID1 S1 to S65 IO = 20 A VMID2 COM1 to COM9 IO = 100 A COM1 to COM9 IO = 100 A Oscillator frequency fosc OSC Current drain IDD1 IDD2 VDD VDD ILCD1 ILCD2 VLCD VLCD Rosc = 10 k, Cosc = 470 pF sleep mode VDD = 3.6 V, output open, fosc = 300 kHz sleep mode VLCD = 10.0 V, output open, fosc = 300 kHz, When the display contrast adjustment circuit is used. VLCD = 10.0 V, output open, fosc = 300 kHz, When the display contrast adjustment circuit is not used. VLCD Ratings typ 2/4 (VLCD0 VLCD4) 0.6 3/4 (VLCD0 VLCD4) 0.6 1/4 (VLCD0 VLCD4) 0.6 VMID3 ILCD3 min 210 unit max 2/4 (VLCD0 VLCD4) +0.6 3/4 (VLCD0 VLCD4) +0.6 1/4 (VLCD0 VLCD4) +0.6 300 390 V kHz 100 500 1000 15 450 900 200 400 A Note: *2. Excluding the bias voltage generation divider resistor built into the VLCD0, VLCD1, VLCD2, VLCD3, and VLCD4. (See Figure 1.) VLCD CONTRAST ADJUSTER VLCD0 VLCD1 To the common and segment drivers VLCD2 VLCD3 VLCD4 Excluding these resistors [Figure 1] Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 4 LC75812PT (1) When CL is stopped at the low level      tcs tcp   DI VIH1 VIL1 tdc tdh tds VIL1   tL tH VIH1 CL 50% VIL1  VIH1 CE DO tdr D1  D0 tch [Figure 2]  (2) When CL is stopped at the high level VIH1 VIL1  CE  VIH1 50% VIL1 tcp tcs VIH1 DI VIL1 tds tdh DO D0 D1 tdc tch     tH      tL CL tdr [Figure 3] (3) OSC pin clock timing in external clock operating mode OSC VIH2 50% VIL2 tCKH tCKL fCK= 1 tCKH + tCKL DCK= t [Figure 4] www.onsemi.com 5 [kHz] tCKH 100[%] CKH + tCKL LC75812PT Package Dimensions unit : mm TQFP100 14x14 / TQFP100 CASE 932AY ISSUE A 0.50.2 16.00.2 16.00.2 100 14.00.1 14.00.1 1 2 0.5 0.125 0.2 0.10 (1.0) 0 to 10  0.10.1 1.2 MAX (1.0) 0.10 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 15.40 XXXXXXXX YMDDD 15.40 (Unit: mm) XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 0.50 0.28 1.00 *This information is generic. Please refer to device data sheet for actual part marking. NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6 LC75812PT KS2/P2 KS1/P1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S65/COM9 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 Pin Assignments 75 50 LC75812PT (TQFP100) 100 26 1 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 25 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 KS3 KS4 KS5 KS6 KI1 KI2 KI3 KI4 KI5 P3/KS7 VDD VLCD VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VSS TEST OSC INH DO CE CL DI 51 76 www.onsemi.com 7 Top view LC75812PT VDD VDET S1 S63 S64 S65/COM9 COM8 COM1 Block Diagram COMMON DRIVER SEGMENT DRIVER LATCH VSS TEST INSTRUCTION DECODER ADRAM 65 bits INSTRUCTION REGISTER ADDRESS COUNTER VLCD CONTRAST ADJUSTER VLCD0 CGRAM 5816 bits CGROM 58240 bits DCRAM 528 bits VLCD1 ADDRESS REGISTER VLCD2 VLCD3 VLCD4 SHIFT REGISTER CCB INTERFACE KEY BUFFER TIMING GENERATOR GENERAL PURPOSE PORT www.onsemi.com 8 P1/KS1 P2/KS2 KS4 KS3 KS5 KS6 P3/KS7 KI1 KI2 KI3 KI4 KI5 CE CL DO DI KEY SCAN INH OSC CLOCK GENERATOR LC75812PT Pin Functions Pin Pin No. S1 to S64 1 to 64 S65/COM9 65 Function Handling Active I/O - O OPEN - O OPEN - O OPEN H I GND - I/O VDD H I when unused Segment driver outputs. S65/COM9 can be used as common driver output pin under the "set display technique" instruction. COM1 to COM8 73 to 66 Common driver outputs. KS1/P1 74 Key scan outputs. Although normal key scan timing lines require KS2/P2 75 diodes to be inserted in the timing lines to prevent shorts, since KS3 to KS6 76 to 79 these outputs are unbalanced CMOS transistor outputs, these KS7/P3 85 outputs will not be damaged by shorting when these outputs are used to form a key matrix. KS1/P1, KS2/P2, and KS7/P3 can be used as general-purpose output ports under the "set key scan output port/general-purpose output port state" instruction. KI1 to KI5 80 to 84 Key scan inputs. These pins have built-in pull-down resistors. OSC 95 Oscillator connections. An oscillator circuit is formed by connecting an external resistor and capacitor to this pin. This pin can also be used as the external clock input pin with the "set display technique" instruction. CE 98 CL 99 DI 100 DO 97 INH 96 Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. I CE: Chip enable CL: Synchronization clock GND - I - O OPEN L I VDD - I - - O OPEN - I OPEN - I OPEN DI: Transfer data DO: Output data Input that turns the display off, disables key scanning, and forces the general-purpose output ports low. When INH is low (VSS): Display off S1 to S64=”L” (VLCD4) S65/COM9=”L” (VLCD4) COM1 to COM8=”L” (VLCD4) General-purpose output ports P1 to P3=low (VSS) Key scanning disabled: KS1 to KS7=low (VSS) All the key data is reset to low. When INH is high (VDD): Display on The state of the pins as key scan output pins or general-purpose output ports can be set with the "set key scan output port/general-purpose output port state" instruction. Key scanning is enabled. However, serial data can be transferred when the INH pin is low. TEST 94 This pin must be connected to ground. VLCD0 88 LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit. However, (VLCD0 - VLCD4) must be greater than or equal to 4.5V. Also, external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. VLCD1 89 LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply the 3/4 (VLCD - VLCD4) voltage level externally. VLCD2 90 LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply the 2/4 (VLCD0 - VLCD4) voltage level externally. Continued on next page. www.onsemi.com 9 LC75812PT Continued from preceding page. Pin Pin No. VLCD3 91 Function Handling Active I/O - I OPEN - I GND - - - - - - - - - when unused LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be used to supply the 1/4 (VLCD0 - VLCD4) voltage level externally. VLCD4 92 LCD drive 0/4 bias voltage (low level) supply pin. Fine adjustment of the display contrast can be implemented by connecting an external variable resistor to this pin. However, (VLCD0 - VLCD4) must be greater than or equal to 4.5V, and VLCD4 must be in the range 0V to 1.5V, inclusive. VDD 86 Logic block power supply connection. Provide a voltage of between 2.7 to 3.6V. VLCD 87 LCD driver block power supply connection. Provide a voltage of between 7.0 to 10.0V when the display contrast adjustment circuit is used and provide a voltage of between 4.5 to 10.0V when the circuit is not used. VSS Power supply connection. Connect to ground. 93 Block Functions AC (address counter) AC is a counter that provides the addresses used for DCRAM and ADRAM. The address is automatically modified internally, and the LCD display state is retained. DCRAM (data control RAM) DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 57 or 58 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of 528 bits, and can hold 52 characters. The table below lists the correspondence between the 6-bit DCRAM address loaded into AC and the display position on the LCD panel. When the DCRAM address loaded into AC is 00H. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 DCRAM address (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 DCRAM address (hexadecimal) 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 DCRAM address (hexadecimal) 33 00 01 02 03 04 05 06 07 08 09 0A 0B Note: *3. The DCRAM address is expressed in hexadecimal. Most significant bit  MSB Least significant bit  LSB DCRAM address DA0 DA1 DA2 DA3 Hexadecimal DA4 DA5 Hexadecimal Example: When the DCRAM address is 2EH. DA0 DA1 DA2 DA3 DA4 DA5 0 1 1 1 0 1 Note: *4. 57 dots ·········· 13th digit display 57 dots 58 dots ·········· 13th digit display 48 dots www.onsemi.com 10 (shift left) (shift right) LC75812PT ADRAM (Additional data RAM) ADRAM is RAM that is used to store the ADATA display data. ADRAM has a capacity of 135 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence between the 4-bit ADRAM address loaded into AC and the display position on the LCD panel. When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 13) Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 ADRAM address (hexadecimal) 0 1 2 3 4 5 6 7 8 9 A B C However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 ADRAM address (hexadecimal) 1 2 3 4 5 6 7 8 9 A B C 0 Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 ADRAM address (hexadecimal) C 0 1 2 3 4 5 6 7 8 9 A B (shift left) (shift right) Note: *5. The ADRAM address is expressed in hexadecimal. Least significant bit  LSB ADRAM address RA0 RA1 Most significant bit  MSB RA2 RA3 Hexadecimal Example: When the ADRAM address is AH. RA0 RA1 RA2 RA3 0 1 0 1 Note: *6. 57 dots ··········· 13th digit display 5 dots 58 dots ··········· 13th digit display 4 dots CGROM (Character generator ROM) CGROM is ROM that is used to generate the 240 kinds of 57 or 58 dot matrix character patterns from the 8-bit character codes. CGROM has a capacity of 24040 bits. When a character code is written to DCRAM, the character pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD corresponding to the DCRAM address loaded into AC. CGRAM (Character generator RAM) CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 57 or 58 dot matrix character patterns can be stored. CGRAM has a capacity of 1640 bits. www.onsemi.com 11 LC75812PT Serial Data Input (1) When CL is stopped at the low level CE CL DI 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D0 D1 D2 D3 D4 D118 D119 Instruction data (Up to 120 bits) DO (2) When CL is stopped at the high level CE CL DI 0 B0 1 B1 0 B2 0 B3 0 A0 0 A1 1 A2 0 A3 D0 D1 D2 D3 D4 D118 D119 Instruction data (Up to 120 bits) DO B0 to B3, A0 to A3: CCB address 42H D0 to D119: Instruction data The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. www.onsemi.com 12 13 www.onsemi.com Notes: … CD1…CD16 D0…D56…D71 W10…W15 W20 W21 CD17 … CD24 D72…D77 D78 D79 W22…W25…W33 CD25 … CD32 D80…D85 D86 D87 W34 W35 PC10…PC31 CD33 … CD40 D88…D93 D94 D95 X X X X X X X X X X PC32 PF0 PF1 PF2 PF3 KC1 KC2 KC3 X AD1 AD2 AD3 AD4 AD5 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 D96 D97 D98 D99 D100 D101 D102 D103 X X X X X X X X X X X X X X KC4 KC5 K C6 K C7 KP1 KP 2 KP3 CT0 CT1 CT2 CT3 X X CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 RA0 RA1 RA2 RA3 DA0 DA1 DA2 DA3 DA4 DA5 DA0 DA1 DA2 DA3 DA4 DA5 DG9 DG10 DG11 DG12 DG13 0 X X X CTC X X IM1 IM2 IM1 IM2 X X X X X X X X X X 1 1 0 0 0 0 SP RA0 RA1 RA2 RA3 R/L SC 0 A A 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 27s 300 = 39s, 108s 300 = 155s, tis 300 = ti1.43s 210 210 210 0s 0s 27s *10 27s/tis *9 27s/tis 27s 27s *8 0s/27s 108s *7 0s/ *11 Execution time X: don't care 0 0 1 1 0 0 1 1 0 D116 D117 D118 D119 X M M DT FC0 FC1 OC D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 *7. Be sure to execute the "set display technique" instruction first after power-on (VDET-based system reset). Note that the execution time of this first instruction is 108s (fosc=300kHz, fCK=300kHz). *8.When the sleep mode (SP = 1) is set, the execution time is 27s (when fosc = 300kHz, fCK = 300kHz). *9. The data format differs when the DCRAM data write instruction is executed in the normal increment mode (IM1=1, IM2=0) or in the super increment mode (IM1=0, IM2=1). Note that the execution time for the DCRAM data write instruction executed in the super increment mode is tis (fosc=300kHz, fCK=300kHz). (See the detailed descriptions.) *10. The data format differs when the ADRAM data write instruction is executed in the normal increment mode (IM1=1, IM2=0) or in the super increment mode (IM1=0, IM2=1). Note that the execution time for the ADRAM data write instruction executed in the super increment mode is tis (fosc=300kHz, fCK=300kHz). (See the detailed descriptions.) *11. The execution times listed here apply when fosc=300kHz, fCK=300kHz. The execution times differ when the oscillator frequency fosc or the external clock frequency fCK differs. Example: When fosc = 210kHz, fCK = 210kHz Set key scan output port/ general-purpose output port state contrast Set display write CGRAM data write *10 ADRAM data write *9 DCRAM data address Set AC Display shift Display on/off control *7 Set display technique Instruction Instruction Table LC75812PT LC75812PT Detailed Instruction Descriptions Set display technique ... (Display technique) Note: Be sure to execute the "set display technique" instruction first after power-on (VDET-based system reset). Code D112 D113 D114 D115 DT FC0 FC1 OC D116 D117 D118 D119 0 0 0 1 X: don’t care DT: Sets the display technique Output pins DT Display technique 0 1/8 duty, 1/4 bias drive S65 1 1/9 duty, 1/4 bias drive COM9 S65/COM9 Note: *12. S65: Segment output COM9: Common output FC0, FC1: Sets the frame frequency of the common and segment output waveforms Frame frequency FC0 FC1 1/8 duty, 1/4 bias drive 1/9 duty, 1/4 bias drive f8[Hz] f9[Hz] 0 0 fosc/3072, fCK/3072 fosc/3456, fCK/3456 1 0 fosc/1536, fCK/1536 fosc/1728, fCK/1728 0 1 fosc/768, fCK/768 fosc/864, fCK/864 OC: Sets the RC oscillator operating mode and external clock operating mode. OC OSC pin function 0 RC oscillator operating mode 1 External clock operating mode Note: *13. When selecting the RC oscillator operating mode, be sure to connect an external resistor Rosc and an external capacitor Cosc to the OSC pin. Display on/off control ... (Display ON/OFF control) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 D109 D110 D111 D112 D113 D114 D115 DG9 DG10 DG11 DG12 DG13 X X X M A SC D116 D117 D118 D119 SP 0 0 1 0 X: don’t care M, A: Specifies the data to be turned on or off M A Display operating state 0 0 Both MDATA and ADATA are turned off (The display is forcibly turned off regardless of the DG1 to DG13 data.) 0 1 Only ADATA is turned on (The ADATA of display digits specified by the DG1 to DG13 data are turned on.) 1 0 1 1 Only MDATA is turned on (The MDATA of display digits specified by the DG1 to DG13 data are turned on.) Both MDATA and ADATA are turned on (The MDATA and ADATA of display digits specified by the DG1 to DG13 data are turned on.) Note: *14. MDATA, ADATA 57 dot matrix display ----- ADATA --- MDATA 58 dot matrix display ----- ADATA --- MDATA www.onsemi.com 14 LC75812PT DG1 to DG13: Specifies the display digit Display digit 1 2 3 4 5 6 7 8 9 10 11 12 13 Display digit data DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 DG13 For example, if DG1 to DG7 are 1, and DG8 to DG13 are 0, then display digits 1 to 7 will be turned on, and display digits 8 to 13 will be turned off (blanked). SC: Controls the common and segment output pins SC Common and segment output pin states 0 Output of LCD drive waveforms 1 Fixed at the VLCD4 level (all segments off) Note: *15. When SC is 1, the S1 to S65 and COM1 to COM9 output pins are set to the VLCD4 level, regardless of the M, A, and DG1 to DG13 data. SP: Controls the normal mode and sleep mode SP Mode 0 Normal mode Sleep mode The common and segment pins go to the VLCD4 level and the oscillator on the OSC pin is stopped (although it operates during key scan operations) in RC oscillator operating mode (OC="0") and reception of the external clock is stopped (external clock is received during key scan operations) in external clock operating mode (OC="1"), to reduce current drain. Although the "display on/off control", "set display contrast" and "set key scan output port/general-purpose output port state" 1 (disallowed to set pins P1 to P3 for PWM signal output and pin P3 for clock signal output) instructions can be executed in this mode, applications must return the IC to normal mode to execute any of the other instruction setting. When the IC is in external clock operating mode, be sure to stop the external clock input after the lapse of the instruction execution time (27s: fCK=300kHz). Display shift ... (Display shift) Code D112 D113 D114 D115 D116 D117 D118 D119 M A R/L X 0 0 1 1 X: don’t care M, A: Specifies the data to be shifted M A 0 0 Shift operating state Neither MDATA nor ADATA is shifted 0 1 Only ADATA is shifted 1 0 Only MDATA is shifted 1 1 Both MDATA and ADATA are shifted R/L: Specifies the shift direction R/L Shift direction 0 Shift left 1 Shift right www.onsemi.com 15 LC75812PT Set AC address... (Set AC) Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 DA0 DA1 DA2 DA3 DA4 DA5 X X RA0 RA1 RA2 RA3 0 1 0 0 X: don’t care DA0 to DA5: DCRAM address DA0 DA1 DA2 DA3 DA4 LSB  Least significant bit DA5 MSB  Most significant bit RA0 to RA3: ADRAM address RA0 RA1 RA2 LSB  Least significant bit RA3 MSB  Most significant bit This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC. DCRAM data write ... (Write data to DCRAM) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X IM1 IM2 X X 0 1 0 X: don’t care DA0 to DA5: DCRAM address DA0 DA1 DA2 DA3 LSB  Least significant bit DA4 DA5 MSB  Most significant bit AC0 to AC7: DCRAM data (character code) AC0 AC1 AC2 LSB  Least significant bit AC3 AC4 AC5 AC6 AC7 MSB  Most significant bit This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a 57 or 58 dot matrix display data using CGROM or CGRAM. IM1, IM2: Sets the method of writing data to DCRAM IM1 IM2 0 0 Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.) DCRAM data write method 1 0 Normal increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.) 0 1 Super increment mode DCRAM data write (Writes 2 to 13 characters of DCRAM data in single operation.) www.onsemi.com 16 1 LC75812PT Notes: *16. DCRAM data write method when IM1 = 0, IM2 = 0 CE CCB address CCB address DI CCB address CCB address (1) (1) (1) (1) 24 bit 24 bit 24 bit 24 bit DCRAM Instruction Instruction Instruction execution time execution time execution time (27s) DCRAM data (27s) DCRAM data (27s) write finishes write finishes Instruction execution time (27s) DCRAM data DCRAM data write finishes write finishes DCRAM data write method when IM1 = 1, IM2 = 0 (Instructions other than the “DCRAM data write” instruction cannot be executed.) CE CCB address DI CCB address CCB address CCB address CCB address (2) (3) (3) (3) 24 bit 8 bit 8 bit 8 bit CCB address (4) (3) 8 bit 16 bit DCRAM Instruction execution time (27s) DCRAM data write finishes Instruction Instruction Instruction Instruction Instruction execution time execution time execution time execution time execution time (27s) (27s) (27s) (27s) (27s) DCRAM data DCRAM data DCRAM data DCRAM data write finishes write finishes write finishes write finishes DCRAM data write finishes Instructions other than the “DCRAM data write” instruction cannot be executed. DCRAM data write method when IM1 = 0, IM2 = 1 CE CCB address DI CCB address CCB address (5) (5) (5) n bit n bit n bit DCRAM Instruction execution time (tis) DCRAM data write finishes Instruction execution time (tis) DCRAM data write finishes Instruction execution time (tis) DCRAM data write finishes ti=13.5s×( n -1) 8 (n=8m+16, m is an integer between 2 and 13 that is the number of characters written as DCRAM data.) For example When n= 32 bits (m=2): ti= 40.5s (fosc=300kHz, fCK=300kHz) When n= 80 bits (m=8) : ti=121.5s (fosc=300kHz, fCK=300kHz) When n=120 bits (m=13): ti=189.0s (fosc=300kHz, fCK=300kHz) Note that the instruction execution time of 27s and ti values in s apply when fosc=300kHz and fCK=300kHz, and that these execution times will differ when the CR oscillator frequency fosc and external clock frequency fCK differ. www.onsemi.com 17 LC75812PT Data format at (1) (24 bits) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X 0 0 X X 0 1 0 1 X: don’t care Data format at (2) (24 bits) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 X X 1 0 X X 0 1 0 1 X: don’t care Data format at (3) (8 bits) Code D112 D113 D114 D115 D116 D117 D118 D119 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 Data format at (4) (16 bits) Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 0 0 X X 0 1 0 1 Data format at (5) (n bit) Code Dz+1 Dz+2 Dz+3 Dz+4 Dz+5 Dz+6 Dz+7  AC01 AC11 AC21 AC31 AC41 AC51 AC61 AC71  Dz D88 D89 D90 D91 D92 D93 D94 D95 AC0m-1 AC1m-1 AC2m-1 AC3m-1 AC4m-1 AC5m-1 AC6m-1 AC7m-1 Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AC0m AC1m AC2m AC3m AC4m AC5m AC6m AC7m DA0 1 DA11 DA21 DA31 DA41 DA51 X X 0 1 X X 0 1 0 1 X: don’t care Here, n=8m+16, z=104-8m (m is an integer between 2 and 13 that is the number of characters written as DCRAM data.) Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DA01 to DA51 AC01 to AC71 (DA01 to DA51)+1 AC02 to AC72 (DA01 to DA51)+2 AC03 to AC73 (DA01 to DA51)+(m-3) AC0m-2 to AC7m-2 (DA01 to DA51)+(m-2) AC0m-1 to AC7m-1 (DA01 to DA51)+(m-1) AC0m to AC7m www.onsemi.com 18 LC75812PT Example 1: When n=32 bits (m=2: 2 characters DCRAM data write operation) Code D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 AC01 AC11 AC21 AC31 AC41 AC51 AC61 AC71 AC02 AC12 AC22 AC32 AC42 AC52 AC62 AC72 Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 DA0 1 DA11 DA21 DA31 DA41 DA51 X X 0 1 X X 0 1 0 1 X: don’t care Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DA0 1 to DA5 1 AC0 1 to AC7 1 (DA0 1 to DA5 1)+1 AC0 2 to AC72 Example 2: When n=80 bits (m=8: 8 characters DCRAM data write operation) Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 AC0 1 AC11 AC21 AC31 AC41 AC51 AC61 AC71 AC02 AC12 AC22 AC32 AC42 AC52 AC62 AC72 Code D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 AC03 AC13 AC23 AC33 AC43 AC53 AC63 AC73 AC04 AC14 AC24 AC34 AC44 AC54 AC64 AC74 Code D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 AC05 AC15 AC25 AC35 AC45 AC55 AC65 AC75 AC06 AC16 AC26 AC36 AC46 AC56 AC66 AC76 Code D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 AC07 AC17 AC27 AC37 AC47 AC57 AC67 AC77 AC08 AC18 AC28 AC38 AC48 AC58 AC68 AC78 Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 DA01 DA11 DA21 DA31 DA41 DA51 X X 0 1 X X 0 1 0 1 X: don't care Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DA01 to DA51 AC01 to AC71 (DA01 to DA51)+1 AC02 to AC72 (DA01 to DA51)+2 AC03 to AC73 (DA01 to DA51)+3 AC04 to AC74 (DA01 to DA51)+4 AC05 to AC75 (DA01 to DA51)+5 AC06 to AC76 (DA01 to DA51)+6 AC07 to AC77 (DA01 to DA51)+7 AC08 to AC78 www.onsemi.com 19 LC75812PT Example 3: When n=120 bits (m=13: 13 characters DCRAM data write operation) Code D0 D1 D2 D3 D4 D5 D6 D7 D8 AC01 AC11 AC21 AC31 AC41 AC51 AC61 AC71 D9 D10 D11 D12 D13 D14 D15 AC02 AC12 AC22 AC32 AC42 AC52 AC62 AC72 Code D16 D17 D18 D19 D20 D21 D22 D23 AC03 AC13 AC23 AC33 AC43 AC53 AC63 AC73 D24 D25 D26 D27 D28 D29 D30 D31 AC04 AC14 AC24 AC34 AC44 AC54 AC64 AC74 Code D32 D33 D34 D35 D36 D37 D38 D39 AC05 AC15 AC25 AC35 AC45 AC55 AC65 AC75 D40 D41 D42 D43 D44 D45 D46 D47 AC06 AC16 AC26 AC36 AC46 AC56 AC66 AC76 Code D48 D49 D50 D51 D52 D53 D54 D55 AC07 AC17 AC27 AC37 AC47 AC57 AC67 AC77 D56 D57 D58 D59 D60 D61 D62 D63 AC08 AC18 AC28 AC38 AC48 AC58 AC68 AC78 Code D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 AC09 AC19 AC29 AC39 AC49 AC59 AC69 AC79 AC010 AC110 AC210 AC310 AC410 AC510 AC610 AC710 Code D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 AC011 AC111 AC211 AC311 AC411 AC511 AC611 AC711 AC012 AC112 AC212 AC312 AC412 AC512 AC612 AC712 Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 AC013 AC113 AC213 AC313 AC413 AC513 AC613 AC713 DA01 DA11 DA21 DA31 DA41 DA51 X X Code D112 D113 D114 D115 D116 D117 D118 D119 0 1 X X 0 1 0 1 X: don't care Correspondence between the DCRAM address and the DCRAM data DCRAM address DCRAM data DCRAM address DCRAM data DA01 to DA51 AC01 to AC71 (DA01 to DA51)+7 AC08 to AC78 (DA01 to DA51)+1 AC02 to AC72 (DA01 to DA51)+8 AC09 to AC79 (DA01 to DA51)+2 AC03 to AC73 (DA01 to DA51)+9 AC010 to AC710 (DA01 to DA51)+3 AC04 to AC74 (DA01 to DA51)+10 AC011 to AC711 (DA01 to DA51)+4 AC05 to AC75 (DA01 to DA51)+11 AC012 to AC712 (DA01 to DA51)+5 AC06 to AC76 (DA01 to DA51)+12 AC013 to AC713 (DA01 to DA51)+6 AC07 to AC77 www.onsemi.com 20 LC75812PT ADRAM data write ... (Write data to ADRAM) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AD1 AD2 AD3 AD4 AD5 X X X RA0 RA1 RA2 RA3 X X X X IM1 IM2 X X 0 1 1 0 X: don’t care RA0 to RA3:ADRAM address RA0 RA1 RA2 LSB  Least significant bit RA3 MSB  Most significant bit AD1 to AD5: ADATA display data In addition to the 57 or 58 dot matrix display data (MDATA), this IC supports direct display of the five accessory display segments provided in each digit as ADATA. This display function does not use CGROM or CGRAM. The figure below shows the correspondence between the data and the display. When ADn = 1(where n is an integer between 1 and 5) the segment corresponding to that data will be turned on. S5m+1 S5m+5 (m is an integer between 0 and 12) ADATA Corresponding output pin AD1 S5m+1 (m is an integer between 0 and 12) AD2 S5m+2 AD3 S5m+3 AD4 S5m+4 AD5 S5m+5 IM1, IM2: Sets the method of writing data to ADRAM IM1 IM2 0 0 ADRAM data write method Normal ADRAM data write (Specifies the ADRAM address and writes the ADRAM data.) 1 0 Nomal increment mode ADRAM data write (Increments the ADRAM address by +1 each time data is written to ADRAM.) 0 1 Super increment mode ADRAM data write (Writes 2 to 13 digits of ADRAM data in single operation.) www.onsemi.com 21 LC75812PT Notes: *17. ADRAM data write method when IM1 = 0, IM2 = 0 CE CCB address CCB address CCB address CCB address (6) (6) (6) (6) 24 bit 24 bit 24 bit 24 bit Instruction Instruction Instruction execution time execution time execution time (27s) ADRAM data (27s) ADRAM data (27s) write finishes write finishes Instruction execution time (27s) DI ADRAM ADRAM data write finishes ADRAM data write finishes ADRAM data write method when IM1 = 1, IM2 = 0 (Instructions other than the “ADRAM data write” instruction cannot be executed.) CE CCB address DI CCB address CCB address CCB address CCB address CCB address (7) (8) (8) (8) (8) (9) 24 bit 8 bit 8 bit 8 bit 8 bit 16 bit Instruction execution time (27s) Instruction execution time (27s) ADRAM Instruction execution time (27s) Instruction execution time (27s) ADRAM data write finishes Instruction execution time (27s) ADRAM data write finishes Instruction execution time (27s) ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes Instructions other than the “ADRAM data write” instruction cannot be executed. ADRAM data write method when IM1 = 0, IM2 = 1 CE CCB address DI CCB address CCB address (10) (10) n bit n bit (10) n bit ADRAM Instruction execution time (tis) ADRAM data write finishes Instruction execution time (tis) ADRAM data write finishes Instruction execution time (tis) ADRAM data write finishes n ti=13.5s×( -1) 8 (n=8m+16, m is an integer between 2 and 13 that is the number of characters written as ADRAM data.) For example When n= 32 bits (m=2): ti= 40.5s (fosc=300kHz, fCK=300kHz) When n= 80 bits (m=8): ti=121.5s (fosc=300kHz, fCK=300kHz) When n=120 bits (m=13): ti=189.0s (fosc=300kHz, fCK=300kHz) Note that the instruction execution time of 27s and ti values in μs apply when fosc=300kHz and fCK=300kHz, and that these execution times will differ when the CR oscillator frequency fosc and external clock frequency fCK differ. www.onsemi.com 22 LC75812PT Data format at (6) (24 bits) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AD1 AD2 AD3 AD4 AD5 X X X RA0 RA1 RA2 RA3 X X X X 0 0 X X 0 1 1 0 X: don’t care Data format at (7) (24 bits) Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AD1 AD2 AD3 AD4 AD5 X X X RA0 RA1 RA2 RA3 X X X X 1 0 X X 0 1 1 0 X: don’t care Data format at (8) (8 bits) Code D112 D113 D114 D115 D116 D117 D118 D119 AD1 AD2 AD3 AD4 AD5 X X X Data format at (9) (16 bits) Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AD1 AD2 AD3 AD4 AD5 X X X 0 0 X X 0 1 1 0 X: don’t care Data format at (10) (n bit) Code Dz Dz+1 Dz+2 Dz+3 Dz+4 Dz+5 Dz+6 Dz+7 AD11 AD21 AD31 AD41 AD51 X X  D88  X D89 D90 D91 D92 AD1m-1 AD2m-1 AD3m-1 AD4m-1 AD5m-1 D93 D94 D95 X X X Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 AD1m AD2m AD3m AD4m AD5m X X X RA0 1 RA11 RA21 RA31 X X X X 0 1 X X 0 1 1 0 X: don’t care Here, n=8m+16, z=104-8m (m is an integer between 2 and 13 that is the number of characters written as ADRAM data.) Correspondence between the ADRAM address and theADRAM data ADRAM address ADRAM data RA01 to RA31 AD11 to AD51 (RA01 to RA31)+1 AD12 to AD52 (RA01 to RA31)+2 AD13 to AD53 (RA01 to RA31)+(m-3) AD1m-2 to AD5m-2 (RA01 to RA31)+(m-2) AD1m-1 to AD5m-1 (RA01 to RA31)+(m-1) AD1m to AD5m www.onsemi.com 23 LC75812PT Example 1: When n=32 bits (m=2: 2 characters ADRAM data write operation) Code D88 D89 D90 D91 D92 AD11 AD21 AD31 AD41 AD51 D93 D94 D95 X X X D96 D97 D98 D99 D100 D101 D102 D103 AD12 AD22 AD33 AD44 AD55 X X X Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 RA0 1 RA11 RA21 RA31 X X X X 0 1 X X 0 1 1 0 X: don’t care Correspondence between the ADRAM address and the ADRAM data ADRAM address ADRAM data RA0 1 to RA3 1 AD1 1 to AD5 1 (RA0 1 to RA3 1)+1 AD1 2 to AD52 Example 2: When n=80 bits (m=8: 8 characters ADRAM data write operation) Code D40 D41 D42 D43 D44 AD11 AD21 AD31 AD41 AD51 D45 D46 D47 X X X D48 D49 D50 D51 D52 D53 D54 D55 X X X D69 D70 D71 X X X D85 D86 D87 X X X AD12 AD22 AD32 AD42 AD52 Code D56 D57 D58 D59 D60 AD13 AD23 AD33 AD43 AD53 D61 D62 D63 X X X D77 D78 D79 X X X D93 D94 D95 X X X D64 D65 D66 D67 D68 AD14 AD24 AD34 AD44 AD54 Code D72 D73 D74 D75 D76 AD15 AD25 AD35 AD45 AD55 D80 D81 D82 D83 D84 AD16 AD26 AD36 AD46 AD56 Code D88 D89 D90 D91 D92 AD17 AD27 AD37 AD47 AD57 D96 D97 D98 D99 D100 D101 D102 D103 AD18 AD28 AD38 AD48 AD58 X X X Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 RA0 1 RA11 RA21 RA31 X X X X 0 1 X X 0 1 1 0 X: don't care Correspondence between the ADRAM address and the ADRAM data ADRAM address ADRAM data RA01 to RA31 AD11 to AD51 (RA01 to RA31)+1 AD12 to AD52 (RA01 to RA31)+2 AD13 to AD53 (RA01 to RA31)+3 AD14 to AD54 (RA01 to RA31)+4 AD15 to AD55 (RA01 to RA31)+5 AD16 to AD56 (RA01 to RA31)+6 AD17 to AD57 (RA01 to RA31)+7 AD18 to AD58 www.onsemi.com 24 LC75812PT Example 3: When n=120 bits (m=13: 13 characters ADRAM data write operation) Code D0 D1 D2 D3 D4 AD11 AD21 AD31 AD41 AD51 D5 D6 D7 X X X D8 D21 D22 D23 X X X D37 D38 D39 X X X D9 D10 D11 D12 D13 D14 D15 X X X D29 D30 D31 X X X D45 D46 D47 X X X D61 D62 D63 X X X D77 D78 D79 X X X D93 D94 D95 X X X AD12 AD22 AD32 AD42 AD52 Code D16 D17 D18 D19 D20 AD13 AD23 AD33 AD43 AD53 D24 D25 D26 D27 D28 AD14 AD24 AD34 AD44 AD54 Code D32 D33 D34 D35 D36 AD15 AD25 AD35 AD45 AD55 D40 D41 D42 D43 D44 AD16 AD26 AD36 AD46 AD56 Code D48 D49 D50 D51 D52 AD17 AD27 AD37 AD47 AD57 D53 D54 D55 X X X D56 D57 D58 D59 D60 AD18 AD28 AD38 AD48 AD58 Code D69 D70 D71 AD19 AD29 AD39 AD49 AD59 D64 D65 D66 D67 D68 X X X D80 D85 D86 D87 X X X D72 D73 D74 D75 D76 AD110 AD210 AD310 AD410 AD510 Code D81 D82 D83 D84 AD111 AD211 AD311 AD411 AD511 D88 D89 D90 D91 D92 AD112 AD212 AD312 AD412 AD512 Code D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 AD113 AD213 AD313 AD413 AD513 X X X RA0 1 RA11 RA21 RA31 X X X X Code D112 D113 D114 D115 D116 D117 D118 D119 0 1 X X 0 1 1 0 X: don't care Correspondence between the ADRAM address and the ADRAM data ADRAM address ADRAM data ADRAM address ADRAM data RA01 to RA31 AD11 to AD51 (RA01 to RA31)+7 AD18 to AD58 (RA01 to RA31)+1 AD12 to AD52 (RA01 to RA31)+8 AD19 to AD59 (RA01 to RA31)+2 AD13 to AD53 (RA01 to RA351)+9 AD110 to AD510 (RA01 to RA31)+3 AD14 to AD54 (RA01 to RA31)+10 AD111 to AD511 (RA01 to RA31)+4 AD15 to AD55 (RA01 to RA31)+11 AD112 to AD512 (RA01 to RA31)+5 AD16 to AD56 (RA01 to RA31)+12 AD113 to AD513 (RA01 to RA31)+6 AD17 to AD57 www.onsemi.com 25 LC75812PT CGRAM data write ... (Write data to CGRAM) Code D56 D57 D58 D59 D60 D61 D62 D63 D64 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 CD16 D65 D66 D67 D68 D69 D70 D71 Code D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 Code D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 X X X CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 D99 D100 D101 D102 D103 X X X X X Code D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 X X X X 0 1 1 1 X: don’t care CA0 to CA7: CGRAM address CA0 CA1 CA2 CA3 CA4 LSB  Least significant bit CA5 CA6 CA7 MSB  Most significant bit CD1 to CD40: CGRAM data (57 or 58 dot matrix display data) The bit CDn (where n is an integer between 1 and 40) corresponds to the 57 or 58 dot matrix display data. The figure below shows that correspondence. When CDn is 1 the dots which correspond to that data will be turned on. CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 Note: *18. CD1 to CD35: 57 dot matrix display data CD1 to CD40: 58 dot matrix display data www.onsemi.com 26 LC75812PT Set display contrast… (Set display contrast) Code D104 D105 D106 D107 D108 D109 CT0 CT1 CT3 X X CT2 D110 D111 X X D112 D113 D114 D115 CTC X X X D116 D117 1 0 D118 D119 0 0 X: don’t care CT0 to CT3: Sets the display contrast (11 steps) CT0 CT1 CT2 CT3 0 0 0 0 0.94VLCD=VLCD-(0.03VLCD2) LCD drive 4/4 bias voltage supply VLCD0 level 1 0 0 0 0.91VLCD=VLCD-(0.03VLCD3) 0 1 0 0 0.88VLCD=VLCD-(0.03VLCD4) 1 1 0 0 0.85VLCD=VLCD-(0.03VLCD5) 0 0 1 0 0.82VLCD=VLCD-(0.03VLCD6) 1 0 1 0 0.79VLCD=VLCD-(0.03VLCD7) 0 1 1 0 0.76VLCD=VLCD-(0.03VLCD8) 1 1 1 0 0.73VLCD=VLCD-(0.03VLCD9) 0 0 0 1 0.70VLCD=VLCD-(0.03VLCD10) 1 0 0 1 0.67VLCD=VLCD-(0.03VLCD11) 0 1 0 1 0.64VLCD=VLCD-(0.03VLCD12) CTC: Sets the display contrast adjustment circuit state CTC Display contrast adjustment circuit state 0 The display contrast adjustment circuit is disabled, and the VLCD0 pin level is forced to the VLCD level. 1 The display contrast adjustment circuit operates, and the display contrast is adjusted. Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is also possible to apply fine adjustments to the contrast by connecting an external variable resistor to the VLCD4 pin and modifying the VLCD4 pin voltage. However, the following conditions must be met: VLCD0-VLCD44.5V, and 1.5VVLCD4 0V. www.onsemi.com 27 LC75812PT Set key scan output port/general-purpose output port state ... (Key scan output port and General-purpose output port control) Code D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 W10 W11 D72 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC10 PC11 PC20 PC21 PC30 PC31 D87 D88 D89 D90 D91 D92 D93 D94 D95 Code D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 PC32 PF0 D96 PF1 PF2 PF3 KC1 KC2 KC3 KC4 KC5 KC6 KC7 KP1 KP2 KP3 X X X X X 1 0 0 1 X: don’t care KP1 to KP3: Set the output pins KS1/P1, KS2/P2, and KS7/P3 as either key scan output ports or general-purpose output ports. General- Output pin KP1 KP2 KP3 KS1/P1 KS2/P2 Max. Key purpose Input Output KS7/P3 Port Number Number 0 0 0 KS1 KS2 KS7 35 0 1 0 0 P1 KS2 KS7 30 1 0 1 0 KS1 P2 KS7 30 1 0 0 1 KS1 KS2 P3 30 1 1 1 0 P1 P2 KS7 25 2 0 1 1 KS1 P2 P3 25 2 1 0 1 P1 KS2 P3 25 2 1 1 1 P1 P2 P3 20 3 *19) KSn(n=1,2,7): Key scan output port Pn(n=1 to 3): General-purpose output port KC1 to KC7: Sets the key scan output pin KS1 to KS7 state Output pin KS1 KS2 KS3 KS4 KS5 KS6 KS7 Key scan output state setting data KC1 KC2 KC3 KC4 KC5 KC6 KC7 If, for example, the output pins KS1/P1, KS2/P2, and KS7/P3 are set as key scan output ports, the output pins KS1 to KS3 will go high (VDD) and KS4 to KS7 go low (VSS) in the key scan standby state when KC1 to KC3 are set to 1 and KC4 to KC7 are set to 0. Note that key scan output signals are not output from output pins that are set to the low level. PC10, PC11: Sets the general-purpose output port P1 state PC20, PC21: Sets the general-purpose output port P2 state PC10 PC11 Output pin (P1) state PC20 PC21 Output pin (P2) state 0 0 “L”(VSS) 0 0 “L”(VSS) 1 0 “H”(VDD) 1 0 “H”(VDD) 0 1 PWM signal output 0 1 PWM signal output PC30 to PC32: Sets the general-purpose output port P3 state PC30 PC31 PC32 Output pin (P3) state 0 0 0 “L”(VSS) 1 0 0 “H”(VDD) 0 1 0 PWM signal output 1 1 0 Clock signal output (fosc/2, fCK/2) 0 0 1 Clock signal output (fosc/8, fCK/8) www.onsemi.com 28 LC75812PT PF0 to PF3: Set the frame frequency of the PWM output waveforms. (when general-purpose outout ports P1 to P3 are set to select the PWM signal generation function.) PF0 PF1 PF2 PF3 PWM Output Waveform Frame Frequency fp[Hz] 0 0 0 0 fosc/1536, fCK/1536 1 0 0 0 fosc/1408, fCK/1408 0 1 0 0 fosc/1280, fCK/1280 1 1 0 0 fosc/1152, fCK/1152 0 0 1 0 fosc/1024, fCK/1024 1 0 1 0 fosc/896, fCK/896 0 1 1 0 fosc/768, fCK/768 1 1 1 0 fosc/640, fCK/640 0 0 0 1 fosc/512, fCK/512 1 0 0 1 fosc/384, fCK/384 0 1 0 1 fosc/256, fCK/256 W10 to W15, W20 to W25, W30 to W35: Set the pulse width of the PWM output waveforms. (when general-purpose outout ports P1 to P3 are set to select the PWM signal generation function.) Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 PWM Signal Pn PWM Signal Pn Wn0 Wn1 Wn2 Wn3 Wn4 Wn5 (1/64) Tp 0 0 0 0 0 1 (33/64) Tp 0 (2/64) Tp 1 0 0 0 0 1 (34/64) Tp 0 0 (3/64) Tp 0 1 0 0 0 1 (35/64) Tp 0 0 (4/64) Tp 1 1 0 0 0 1 (36/64) Tp 0 0 0 (5/64) Tp 0 0 1 0 0 1 (37/64) Tp 1 0 0 0 (6/64) Tp 1 0 1 0 0 1 (38/64) Tp 1 0 0 0 (7/64) Tp 0 1 1 0 0 1 (39/64) Tp 1 1 0 0 0 (8/64) Tp 1 1 1 0 0 1 (40/64) Tp 0 0 0 1 0 0 (9/64) Tp 0 0 0 1 0 1 (41/64) Tp 1 0 0 1 0 0 (10/64) Tp 1 0 0 1 0 1 (42/64) Tp 0 1 0 1 0 0 (11/64) Tp 0 1 0 1 0 1 (43/64) Tp 1 1 0 1 0 0 (12/64) Tp 1 1 0 1 0 1 (44/64) Tp 0 0 1 1 0 0 (13/64) Tp 0 0 1 1 0 1 (45/64) Tp 1 0 1 1 0 0 (14/64) Tp 1 0 1 1 0 1 (46/64) Tp 0 1 1 1 0 0 (15/64) Tp 0 1 1 1 0 1 (47/64) Tp 1 1 1 1 0 0 (16/64) Tp 1 1 1 1 0 1 (48/64) Tp 0 0 0 0 1 0 (17/64) Tp 0 0 0 0 1 1 (49/64) Tp 1 0 0 0 1 0 (18/64) Tp 1 0 0 0 1 1 (50/64) Tp 0 1 0 0 1 0 (19/64) Tp 0 1 0 0 1 1 (51/64) Tp 1 1 0 0 1 0 (20/64) Tp 1 1 0 0 1 1 (52/64) Tp 0 0 1 0 1 0 (21/64) Tp 0 0 1 0 1 1 (53/64) Tp 1 0 1 0 1 0 (22/64) Tp 1 0 1 0 1 1 (54/64) Tp 0 1 1 0 1 0 (23/64) Tp 0 1 1 0 1 1 (55/64) Tp 1 1 1 0 1 0 (24/64) Tp 1 1 1 0 1 1 (56/64) Tp 0 0 0 1 1 0 (25/64) Tp 0 0 0 1 1 1 (57/64) Tp 1 0 0 1 1 0 (26/64) Tp 1 0 0 1 1 1 (58/64) Tp 0 1 0 1 1 0 (27/64) Tp 0 1 0 1 1 1 (59/64) Tp 1 1 0 1 1 0 (28/64) Tp 1 1 0 1 1 1 (60/64) Tp 0 0 1 1 1 0 (29/64) Tp 0 0 1 1 1 1 (61/64) Tp 1 0 1 1 1 0 (30/64) Tp 1 0 1 1 1 1 (62/64) Tp 0 1 1 1 1 0 (31/64) Tp 0 1 1 1 1 1 (63/64) Tp 1 1 1 1 1 0 (32/64) Tp 1 1 1 1 1 1 (64/64) Tp Pulse Width Pulse Width Note: *20. Wn0 to Wn5 (n=1 to 3): PWM data for the PWM output waveforms at general-purpose output ports Pn (n=1 to 3). 1 Tp= fp www.onsemi.com 29 LC75812PT Serial Data Output (1) When CL is stopped at the low level CE CL DI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 DO X KD34 KD35 SA KD1 KD2 X X X Output data X: don’t care (2) When CL is stopped at the high level CE CL DI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 DO X KD1 KD2 KD3 KD35 SA X X X X Output data X: don’t care B0 to B3, A0 to A3: CCB address 43H KD1 to KD35: Key data SA: Sleep acknowledge data Note: *21. When key data read operation is executed with DO set high (no key data read request present), the key data (KD1 to KD35) and sleep acknowledge data (SA) are invalid. Output Data (1) KD1 to KD35: Key data When a key matrix of up to 35 keys is formed from the KS1 to KS7 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. KI1 KI2 KI3 KI4 KI5 KS1/P1 KD1 KD2 KD3 KD4 KD5 KS2/P1 KD6 KD7 KD8 KD9 KD10 KS3 KD11 KD12 KD13 KD14 KD15 KS4 KD16 KD17 KD18 KD19 KD20 KS5 KD21 KD22 KD23 KD24 KD25 KS6 KD26 KD27 KD28 KD29 KD30 KS7/P3 KD31 KD32 KD33 KD34 KD35 KD1 to KD10 are all set to 0 when the output pins KS1/P1 and KS2/P2 are set as general-purpose output ports with the "set key scan output port/general-purpose output port state" instruction and a key matrix of maximum 25 keys is formed from the output pins KS3 to KS6 and KS7/P3 and the input pins KI1 to KI5. (2) SA: Sleep acknowledge data This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in Sleep mode and 0 in normal mode. www.onsemi.com 30 LC75812PT Key Scan Operation Functions (1) Key scan timing The key scan period is 2296T(s). To reliably determine the on/off state of the keys, the LC75812PT scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 4800T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it scans the keys again. Thus the LC75812PT cannot detect a key press shorter than 4800T(s). KS1 *22 KS2 *22 KS3 *22 KS4 *22 KS5 *22 KS6 *22 KS7 *22 1 *22 1 2 *22 2 3 *22 3 4 1 fosc T= 1 fCK *22 4 5 T= *22 5 6 *22 6 7 7 *22 4592T[s] Key on Note: *22. Not that the high/low states of these pins are determined by the "set key scan output port/general-purpose output port state" instruction, and that key scan output signals are not output from pins that are set to low. (2) In normal mode The pins KS1 to KS7 are set to high or low with the "set key scan output port/general-purpose output port state" instruction. If a key on one of the lines corresponding to a KS1 to KS7 pin which is set high is pressed, a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. If a key is pressed for longer than 4800T(s) (Where T=1/fosc, T=1/fCK) the LC75812PT outputs a key data read request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75812PT performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1k and 10k). Key input 1 Key input 2 Key scan 4800T[s] 4800T[s] 4800T[s] CE Serial data transfer Serial data transfer Key address (43H) Serial data transfer Key address Key address DI DO Key data read Key data read Key data read request Key data read request Key data read Key data read request T= www.onsemi.com 31 1 fosc T= 1 fCK LC75812PT (3) In sleep mode The pins KS1 to KS7 are set to high or low with the "set key scan output port/general-purpose output port state" instruction. If a key on one of the lines corresponding to a KS1 to KS7 pin which is set high is pressed in the RC oscillator operating mode, the oscillator on the OSC pin is started (the IC starts receiving the external clock in external clock operating mode) and a key scan is performed . Keys are scanned until all keys released. Multiple key presses are recognized by determining whether multiple key data bits are set. If a key is pressed for longer than 4800T(s) (Where T=1/fosc, T=1/fCK) the LC75812PT outputs a key data read request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75812PT performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1k and 10k). Sleep mode key scan example Example: When a "display on/off control (SP=1)" instruction and a "set key scan output port/general-purpose output port state (KP1 to KP3=0, KC1 to KC6= 0, KC7=1)" instruction are executed. (i.e. sleep mode with only KS7 high.) “L” KS1 “L” KS2 “L” KS3 When any one of these keys is pressed in RC oscillator operating mode, the oscillator on the OSC pin is started (the IC starts receiving the external clock in external clock operating mode) and the keys are scanned. “L” KS4 “L” KS5 “L” KS6 “H” KS7 *23 KI1 KI2 KI3 KI4 KI5 Note: *23. These diodes are required to reliably recognize multiple key presses on the KS7 line when sleep mode state with only KS7 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS7 key scan output signal when keys on the KS1 to KS6 lines are pressed at the same time. Key input (KS7 line) Key scan 4800T[s] 4800T[s] CE Serial data transfer Serial data transfer Key address Serial data transfer Key address (43H) DI T= 1 fosc T= 1 fCK DO Key data read Key data read request Key data read Key data read request Multiple Key Presses Although the LC75812PT is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS7 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. www.onsemi.com 32 LC75812PT 1/8 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 COM1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 COM2 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 COM8 VLCD2 VLCD3 VLCD4 VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned off VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 LCD driver output when only LCD segments corresponding to COM1 are turned on VLCD1 LCD driver output when only LCD segments corresponding to COM2 are turned on VLCD1 VLCD2 VLCD3 LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned on VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD4 VLCD0 VLCD2 VLCD3 VLCD4 T8 8 T8 T8= 1 f8 f When a "set display technique" instruction with FC0 = 0, FC1 = 0 are executed: f8 = fosc , f8 = CK 3072 3072 fCK fosc When a "set display technique" instruction with FC0 = 1, FC1 = 0 are executed: f8 = , f8 = 1536 1536 fCK fosc When a "set display technique" instruction with FC0 = 0, FC1 =1 are executed: f8 = , f8 = 768 768 www.onsemi.com 33 LC75812PT 1/9 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 COM1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 COM2 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 COM9 VLCD3 VLCD4 VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned off VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 LCD driver output when only LCD segments corresponding to COM1 are turned on VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 LCD driver output when only LCD segments corresponding to COM2 are turned on VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned on VLCD1 VLCD2 VLCD3 VLCD4 T9 9 T9 T9= 1 f9 f When a "set display technique" instruction with FC0 = 0, FC1 = 0 are executed: f9 = fosc , f9 = CK 3456 3456 fCK fosc When a "set display technique" instruction with FC0 = 1, FC1 = 0 are executed: f9 = , f9 = 1728 1728 fCK fosc When a "set display technique" instruction with FC0 = 0, FC1 =1 are executed: f9 = , f9 = 864 864 www.onsemi.com 34 LC75812PT PWM Output Waveform VDD P1 VDD P2  VSS (56/64)  Tp (56/64)  Tp (48/64)  Tp (48/64)  Tp VSS VDD P3 (40/64)  Tp (40/64)  Tp VSS VDD P1 (8/64)  Tp VSS (8/64)  Tp VDD P2  VSS (16/64)  Tp (16/64)  Tp VDD P3 VSS (24/64)  Tp (24/64)  Tp VDD P1 VSS (32/64)  Tp (32/64)  Tp VDD P2  VSS (32/64)  Tp (32/64)  Tp VDD P3 VSS (32/64)  Tp (32/64)  Tp Tp 1 Tp= fp Tp PWM Output "Set key scan output port/general-purpose output port state" Instruction Data Waveform of General-purpose W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1  1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0  1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0  Output Ports P1 to P3 "Set key scan output port/general-purpose output port state" Instruction Data PWM Output Waveform Frame Frequency PF0 PF1 PF2 PF3 0 0 0 0 fosc/1536, fCK/1536 1 0 0 0 fosc/1408, fCK/1408 0 1 0 0 fosc/1280, fCK/1280 1 1 0 0 fosc/1152, fCK/1152 0 0 1 0 fosc/1024, fCK/1024 1 0 1 0 fosc/896, fCK/896 0 1 1 0 fosc/768, fCK/768 1 1 1 0 fosc/640, fCK/640 0 0 0 1 fosc/512, fCK/512 1 0 0 1 fosc/384, fCK/384 0 1 0 1 fosc/256, fCK/256 www.onsemi.com 35 fp[Hz] LC75812PT Clock Signal Output Waveform P3 Tc/2 Tc= 1 fc Tc "Set Key Scan Output Port/ General-purpose port P3 General-purpose Port State" clock signal frequency Instruction Data fc (=1/Tc) [Hz] PC30 PC31 PC32 1 1 0 Clock signal output (fosc/2, fCK/2) 0 0 1 Clock signal output (fosc/8, fCK/8) Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,which is 2.2 V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1ms. (See Figure 5.) Power Supply Sequence The following sequences must be observed when power is turned on and off. (See Figure 5.) Power on: Logic block power supply(VDD) on LCD driver block power supply (VLCD) on Power off: LCD driver block power supply(VLCD) off Logic block power supply (VDD) off When 5 V signal is applied to the CE, CL, DI, and INH pins which are to be connected to the controller and if the logic block power supply (VDD) is off, set the input voltage at the CE, CL, DI, and INH pins to 0 V and apply the 5 V signal to these pins after turning on the logic block power supply (VDD). System Reset 1. Reset function The LC75812PT performs a system reset with the VDET. When a system reset is applied, the display is turned off, key scanning is disabled, the key data is reset, and the general-purpose output ports are set to and held at the low level (VSS). These states that are created as a result of the system reset can be cleared by executing the instruction described below. (See Figure 5.) Clearing the display off state Display operation can be enabled by executing a “display on/off control” instruction. However, since the contents of the DCRAM, ADRAM, and CGRAM are undefined, applications must set the contents of these memories before turning on display with the “display on/off control” instruction. That is, applications must execute the following instructions. Set display technique (The "set display technique" instruction must be executed first.) DCRAM data write ADRAM data write (If the ADRAM is used.) CGRAM data write (If the CGRAM is used.) Set AC address Set display contrast (If the display contrast adjustment circuit is used.) After executing the above instructions, applications must turn on the display with a “display on/off control” instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off control” instruction or the INH pin. www.onsemi.com 36 LC75812PT Clearing the key scan disable and key data reset states By executing the following instructions not only create a state in which key scanning can be performed, but also clear the key data reset.  Set display technique (The "set display technique" instruction must be executed first.) Set key scan output port/general-purpose output port state Clearing the general-purpose output ports locked at the low level (VSS) state By executing the following instructions clear the general-purpose output ports locked at the low level (VSS) state and set the states of the general-purpose output ports. Set display technique (The "set display technique" instruction must be executed first.) Set key scan output port/general-purpose output port state t3 t4 t1 t2 VDD VDET VDET VLCD Instruction execution Key scan General-purpose output ports Display state Initial state settings Execution enabled Disabled Fixed at the low level (VSS) Can be set to such states as high (VDD), or low (VSS) level Display off “Set display technique” and “Set key scan output port/ general-purpose output port state” instruction execution Display on “Display on/off control” instruction execution (Turning the display on) Display off ”Display on/off control“ instruction execution (Turning the display off) t1  1 [ms] (Logic block power supply voltage VDD rise time) t2  0 t3  0 t4  1 [ms] (Logic block power supply voltage VDD fall time) Initial state settings Set display technique (The "set display technique" instruction must be executed first.) DCRAM data write ADRAM data write (If the ADRAM is used.) CGRAM data write (If the CGRAM is used.) Set AC address Set display contrast (If the display contrast adjustment circuit is used.) [Figure 5] www.onsemi.com 37 LC75812PT 2. Block states during a system reset (1) CLOCK GENERATOR,TIMING GENERATOR When a reset is applied, these circuits are forcibly initialized internally. Then, when the "set display technique" instruction is executed, oscillation of the OSC pin starts in RC oscillator operating mode (the IC starts receiving the external clock in external clock operating mode), execution of the instruction is enabled. (2) INSTRUCTION REGISTER, INSTRUCTION DECODER When a reset is applied, these circuits are forcibly initialized internally. Then, when instruction execution starts, the IC operates according to those instructions. (3) ADDRESS REGISTER, ADDRESS COUNTER When a reset is applied, these circuits are forcibly initialized internally. Then, the DCRAM and the ADRAM addresses are set when “Set AC address” instruction is executed. (4) DCRAM, ADRAM, CGRAM Since the contents of the DCRAM, ADRAM, and CGRAM become undefined during a reset, applications must execute “DCRAM data write”, “ADRAM data write (If the ADRAM is used.)”, and “CGRAM data write (If the CGRAM is used.)” instructions before executing a “display on/off control” instruction. (5) CGROM Character patterns are stored in this ROM. (6) LATCH Although the value of the data in the latch is undefined during a reset, the ADRAM, CGROM, and CGRAM data is stored by executing a “display on/off control” instruction. (7) COMMON DRIVER, SEGMENT DRIVER These circuits are forced to the display off state when a reset is applied. (8) CONTRAST ADJUSTER Display contrast adjustment circuit operation is disabled when a reset is applied. After that, the display contrast can be set by executing a “set display contrast” instruction. (9) KEY SCAN, KEY BUFFER When a reset is applied, these circuits are forcibly initialized internally, and key scan operation is disabled. Also, the key data is all set to 0. After that, key scanning can be performed by executing a "set key scan output port/general-purpose output port state" instruction. (10) GENERAL PURPOSE PORT When a reset is applied, the general-purpose output port state is locked at the low level (VSS). (11) CCB INTERFACE, SHIFT REGISTER These circuits go to the serial data input wait state. www.onsemi.com 38 VDD VDET S1 S63 S64 S65/COM9 COM8 COM1 LC75812PT COMMON DRIVER SEGMENT DRIVER LATCH VSS TEST INSTRUCTION DECODER ADRAM 65 bits INSTRUCTION REGISTER ADDRESS COUNTER VLCD CONTRAST ADJUSTER VLCD0 CGRAM 5816 bits CGROM 58240 bits DCRAM 528 bits VLCD1 ADDRESS REGISTER VLCD2 VLCD3 VLCD4 SHIFT REGISTER CCB INTERFACE KEY BUFFER TIMING GENERATOR GENERAL PURPOSE PORT P1/KS1 KS3 P2/KS2 KS5 KS4 KS6 P3/KS7 KI1 KI2 KI3 KI4 KI5 CE CL DO OSC DI KEY SCAN INH CLOCK GENERATOR Blocks that are reset (3) Output pin states during the reset period Output pin State during reset S1 to S64 L (VLCD4) S65/COM9 L (VLCD4) L (VLCD4) *24 COM1 to COM8 KS1/P1, KS2/P2 L (VSS) *25 KS3 to KS6 L (VSS) KS7/P3 L (VSS) *25 OSC Z (high-impedance) *26 DO H *27 *24 This output pin is forcibly set to the segment output function and held low (VLCD4). If the "set display technique" instruction is executed, however, either segment output or common output is selected according to the instruction. *25 This output pin is forcibly set to general-purpose output port and held low (VSS). If the “set display technique” and the "set key scan output port/general-purpose output port state" instructions are executed, however, either key scan output port or general-purpose output port is selected according to the instructions. *26 This I/O pin is forcibly set to the high-impedance state. *27 Since this output pin is an open-drain output, a pull-up resistor (between 1 k and 10 k) is required. This pin is held at the high level even if a key data read operation is performed before executing the "set display technique" or "set key scan output port/general-purpose output port state" instruction. www.onsemi.com 39 LC75812PT OSC Pin Peripheral Circuit (1) RC oscillator operating mode (when the "set display technique (OC=0)" instruction is executed) When RC oscillator operating mode is selected, an external resistor Rosc and an external capacitor Cosc must be connected between the OSC pin and GND. OSC Rosc Cosc (2) External clock operating mode (when the "set display technique (OC=1)" instruction is executed) When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22 k) between the OSC pin and external clock output pin (external oscillator). Determine the value of the resistance according to the maximum allowable current value at the external clock output pin. Also make sure that the waveform of the external clock is not heavily distorted. External clock output pin OSC Rg External oscillator Note: *28. Allowable current value at external clock output pin > VDD Rg Pins P1 to P3 peripheral circuit It is recommended that the following circuit be used when adjusting the brightness of the LED backlight in PWM mode using the general-purpose output ports P1 to P3 (when PWM signal output function is selected with the general-purpose output ports P1 to P3 under the "set key scan output port/general-purpose output port state" instruction): VCC LED P1 to P3 Note when applying a 5 V signal to the CE, CL, DI, and INH pins When applying a 5V signal to the CE, CL, DI, and INH pins which are to be connected to the controller, set the input voltage to the CE, CL, DI, and INH pins to 0 V if the logic block power supply (VDD) is off, and apply the 5 V signal to those pins after turning on the logic block power supply (VDD). www.onsemi.com 40 LC75812PT Sample Application Circuit 1 1/8 duty, 1/4 bias drive technique (for use with normal panels) LCD panel +3.3V *29 VDD COM1 TEST COM2 COM3 COM4 COM5 COM6 COM7 COM8 VSS +8V VLCD OPEN C C VLCD0 VLCD1 VLCD2 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 VLCD3 C VLCD4 *30 C0.047F OSC *31 *34 From the controller To the controller To the controller power supply *33 INH *32 CE CL DI DO KKKKK I I I I I 5 4 3 2 1 S61 S62 S63 S64 COM9/S65 P 3 / KK K K K SS S S S 76 5 4 3 P 2 / K S 2 P 1 / K S 1 General-purpose output ports used with the backlight controller or other circuit Key matrix (up to 35 keys) Note *29. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the VDET. *30. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *31. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22 k) between the OSC pin and the external clock output pin (external oscillator). (See the “OSC Pin Peripheral Circuit” section.) *32. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *33. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 k and 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *34 When applying a 5 V signal to the CE, CL, DI, and INH pins, set the input voltage to 0 V if the logic block power supply (VDD) is off and apply the 5 V signal to those pins after turning on the logic block power supply (VDD). www.onsemi.com 41 LC75812PT Sample Application Circuit 2 1/8 duty, 1/4 bias drive technique (for use with large panels) LCD panel +3.3V *29 +8V VDD COM1 TEST VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 VLCD VLCD0 R R R C C C R VLCD1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 VLCD2 VLCD3 VLCD4 *30 C0.047F 10kR2.2k OSC *31 *34 From the controller To the controller To the controller power supply *33 INH *32 CE CL DI DO KKKKK I I I I I 5 4 3 2 1 S61 S62 S63 S64 COM9/S65 PP P 2 1 3 / / / K K K K KK K S S S S SS S 7 6 5 4 32 1 General-purpose output ports used with the backlight controller or other circuit Key matrix (up to 35 keys) Note *29. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the VDET. *30. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *31. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22 k) between the OSC pin and the external clock output pin (external oscillator). (See the “OSC Pin Peripheral Circuit” section.) *32. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *33. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 k and 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *34 When applying a 5 V signal to the CE, CL, DI, and INH pins, set the input voltage to 0 V if the logic block power supply (VDD) is off and apply the 5 V signal to those pins after turning on the logic block power supply (VDD). www.onsemi.com 42 LC75812PT Sample Application Circuit 3 1/9 duty, 1/4 bias drive technique (for use with normal panels) LCD panel VDD +3.3V *29 COM1 TEST VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 S65/COM9 VLCD +8V OPEN VLCD0 VLCD1 VLCD2 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 VLCD3 C C C VLCD4 *30 C0.047F OSC *31 *34 From the controller To the controller To the controller power supply *33 INH *32 CE CL DI DO KKKKK I I I I I 5 4 3 2 1 S61 S62 S63 S64 PP P 2 1 3 / / / KKKKKKK SSSSSSS 7 6 5 4 3 2 1 General-purpose output ports used with the backlight controller or other circuit Key matrix (up to 35 keys) Note *29. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the VDET. *30. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *31. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22 k) between the OSC pin and the external clock output pin (external oscillator). (See the “OSC Pin Peripheral Circuit” section.) *32. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *33. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 k and 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *34 When applying a 5 V signal to the CE, CL, DI, and INH pins, set the input voltage to 0 V if the logic block power supply (VDD) is off and apply the 5 V signal to those pins after turning on the logic block power supply (VDD). www.onsemi.com 43 LC75812PT Sample Application Circuit 4 1/9 duty, 1/4 bias drive technique (for use with large panels) LCD panel +3.3V VDD *29 COM1 TEST VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 S65/COM9 VLCD +8V VLCD0 R R R C C C R VLCD1 VLCD2 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 VLCD3 VLCD4 *30 C0.047F 10kR2.2k OSC *31 *34 From the controller To the controller To the controller power supply *33 INH *32 CE CL DI DO KKKKK I I I I I 5 4 3 2 1 S61 S62 S63 S64 PP P 2 1 3 / / / KKKKKKK SSSSSSS 7 6 5 4 3 2 1 General-purpose output ports used with the backlight controller or other circuit Key matrix (up to 35 keys) Note *29. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75812PT is reset by the VDET. *30. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *31. In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22 k) between the OSC pin and the external clock output pin (external oscillator). (See the “OSC Pin Peripheral Circuit” section.) *32. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *33. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 k and 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *34 When applying a 5 V signal to the CE, CL, DI, and INH pins, set the input voltage to 0 V if the logic block power supply (VDD) is off and apply the 5 V signal to those pins after turning on the logic block power supply (VDD). www.onsemi.com 44 LC75812PT Sample Correspondence between Instructions and the Display (When the LC75812PT-8565 is used) LSB No. Instruction (hexadecimal) D100 to D104 to D108 to D112 to D116 to D99 D103 D107 D111 D115 D119 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 The display is in the off state. Sets to 1/8 duty 1/4 bias display drive 0 technique 8 DCRAM data write (normal increment mode) 0 2 0 0 1 Writes the display data “ ” to DCRAM address 00H A DCRAM data write (normal increment mode) 3 Writes the display data “S” to DCRAM address 01H 5 DCRAM data write (normal increment mode) 1 Writes the display data “A” to DCRAM address 02H 4 DCRAM data write (normal increment mode) E Writes the display data “N” to DCRAM address 03H 4 DCRAM data write (normal increment mode) 9 Writes the display data “Y” to DCRAM address 04H 5 DCRAM data write (normal increment mode) F Writes the display data “O” to DCRAM address 05H 4 DCRAM data write (normal increment mode) 0 Writes the display data “ ” to DCRAM address 06H 2 DCRAM data write (normal increment mode) C Writes the display data “L” to DCRAM address 07H 4 DCRAM data write (normal increment mode) 3 Writes the display data “S” to DCRAM address 08H 5 DCRAM data write (normal increment mode) 9 Writes the display data “I” to DCRAM address 09H 4 DCRAM data write (normal increment mode) 0 Writes the display data “ ” to DCRAM address 0AH 2 DCRAM data write (normal increment mode) C Writes the display data “L” to DCRAM address 0BH 4 DCRAM data write (normal increment mode) 3 Writes the display data “C” to DCRAM address 0CH 4 DCRAM data write (normal increment mode) 7 Writes the display data “7” to DCRAM address 0DH 3 DCRAM data write (normal increment mode) 5 Writes the display data “5” to DCRAM address 0EH 3 DCRAM data write (normal increment mode) 8 Writes the display data “8” to DCRAM address 0FH 3 DCRAM data write (normal increment mode) 1 Writes the display data “1” to DCRAM address 10H 3 DCRAM data write (normal increment mode) 2 Writes the display data “2” to DCRAM address 11H 3 DCRAM data write (normal increment mode) 0 2 Operation Initializes the IC. Set display technique 2 4 Display Power application (Initialization with the VDET) 1 3 MSB D96 to 0 Writes the display data “ ” to DCRAM address 12H A Continued on next page. www.onsemi.com 45 LC75812PT Continued from preceding page. LSB No. Instruction (hexadecimal) D100 to D104 to D108 to D112 to D116 to D99 D103 D107 D111 D115 D119 0 2 1 4 1 C 1 C 1 C 1 C 1 C 1 C 8 4 1 4 0 2 0 F F 1 ADRAM address 0H into AC SANYO SANYO Display shift ANYO Display shift 26 NYO Display shift 27 YO Display shift 28 O Display shift 29 32 Operation Loads the DCRAM address 00H and the Display shift 25 31 0 Display on/off control F 24 30 Display Set AC address 22 23 MSB D96 to LSI LSI LSI LC75 Shifts the display (MDATA only) to the left LC758 Shifts the display (MDATA only) to the left LC7581 Shifts the display (MDATA only) to the left LC75812 Shifts the display (MDATA only) to the left LC75812 Display on/off control 0 0 F F 0 0 1 0 digits LSI Set AC address 0 Shifts the display (MDATA only) to the left Set to sleep mode, turns off the LCD for all Display on/off control F MDATA Shifts the display (MDATA only) to the left LSI LSI Turns on the LCD for all digits (13 digits) in LC7 LSI LSI LC LC75812 Turns on the LCD for all digits (13 digits) in MDATA SANYO LSI LC Loads the DCRAM address 00H and the ADRAM address 0H into AC *35) The sample correspondence between the instructions and the display assumes the use of 13 digits1 row 57 dot matrix LCD. Neither CGRAM nor ADRAM are used. www.onsemi.com 46 LC75812PT *36) Given below are the data formats of the "DCRAM data write" instructions (No. 3 to No. 21) for the sample correspondence between the instructions and the display executed in the super increment mode. In the super increment mode processing example shown below, 19 characters of DCRAM data is divided and written into DCRAM in two operations. Instruction (HEX) No. 3 to 15 LSB MSB D0 to D4 to D8 to D12 to D16 to D20 to D24 to D28 to D32 to D36 to D40 to D44 to D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 0 2 3 5 9 5 F 4 DCRAM data write (Super increment mode) 1 4 E 4 DCRAM data write (Super increment mode) 16 to 21 Instruction (HEX) No. 3 to 15 LSB MSB D48 to D52 to D56 to D60 to D51 D55 D59 D63 D64 to D68 to D72 to D76 to D80 to D84 to D88 to D92 to D67 D71 D75 D79 D83 D87 D91 D95 0 2 C 4 1 3 2 3 DCRAM data write (Super increment mode) 0 2 C 4 7 3 3 5 9 4 DCRAM data write (Super increment mode) 16 to 21 5 3 8 3 Instruction (HEX) No. LSB MSB D96 to D100 to D99 D103 D104 to D108 to D112 to D116 to D107 D111 D115 D119 DCRAM data write Display data “ ” “S” “A” “N” “Y” “O” “ ” “L” “S” “I” “ ” “L” “C” (Super increment mode) 3 to 15 3 4 0 0 are written sequentially to DCRAM addresses 00H to 2 A DCRAM data write 0 2 D 0 0CH. Display data “7” “5” “8” “1” “2” “ ” are written sequentially (Super increment mode) 16 to 21 Operation 2 A www.onsemi.com 47 to DCRAM addresses 0DH to 12H. LC75812PT Notes on the controller key data read techniques 1. Timer based key data acquisition Flowchart CE=”L” NO DO=”L” YES Key data read processing Timing chart Key on Key on Key input Key scan t5 t6 t5 t5 CE DI t8 Key address t7 t8 Key data read t8 t7 t7 DO Key data read request t9 Controller determination (Key on) t9 Controller determination (Key on) t9 Controller determination (Key off) t9 Controller determination (Key on) Controller Determination (Key off) t5: Key scan execution time when the key data agreed for two key scans. (4800T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600T(s)) 1 1 t7: Key address (43H) transfer time T= T= fCK fosc t8: Key data read time Explanation In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 When key data read operation is executed with DO set high (no key data read request present), the key data (KD1 to KD35) and sleep acknowledge data (SA) are invalid. www.onsemi.com 48 LC75812PT 2. Interrupt based key data acquisition Flowchart CE=”L” NO DO=”L” YES Key data read processing Wait for at least t10 CE=”L” NO DO=”H” YES Key OFF Timing chart Key on Key on Key input Key scan t5 t5 CE DI t8 t8 Key address t7 t5 t6 Key data read t8 t7 t8 t7 t7 DO Key data read request t10 Controller determination (Key on) Controller determination (Key off) t10 Controller determination (Key on) Controller determination (Key on) t10 Controller determination (Key on) t10 Controller determination (Key off) t5: Key scan execution time when the key data agreed for two key scans. (4800T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600T(s)) 1 1 t7: Key address (43H) transfer time T= T= fCK fosc t8: Key data read time Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t10 has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must satisfy the following condition. t10 > t6 When key data read operation is executed with DO set high (no key data read request present), the key data (KD1 to KD35) and sleep acknowledge data (SA) are invalid. www.onsemi.com 49 LC75812PT About Data Communication Method with The Controller 1. About data communication method of 4 line type CCB format The 4 line type CCB format is the data communication method of before. The LC75812PT must connect to the controller as followings. *38 (INT) Controller *37 Rup DI DO DO DI CL CL CE CE LC75812PT Note: *37. Connect the pull-up resistor Rup. Select a resistance (between 1 to 10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *38. The (INT) pin is an input port for the key data read request signal (a low level on DO) detection. 2. About data communication method of 3 line type CCB format The 3 line type CCB format is the data communication method that made a common use of the data input DI in the data output DO. The LC75812PT must connect to the controller as followings. *38 (INT) *37 Rup DIO DO Controller DI CL CL CE CE LC75812PT Note: *37. Connect the pull-up resistor Rup. Select a resistance (between 1 to 10k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. *38. The (INT) pin is an input port for the key data read request signal (a low level on DO) detection. In this case, Applications must transfer the data communication start command before the serial data input (CCB address “42H”, display data and control data transfer) or serial data output (CCB address “43H” transfer, key data read) to avoid the collision of the data input signal DI and the data output signal DO. Then applications must transfer the data communication stop command when the controller wants to detect the key data read request signal (a low level on DO) during a movement stop of the serial data input and the serial data output. 1 Data communication start command (1) When CL is stoped at the low level (2) When CL is stoped at the high level CE CE CL CL DI/DO 0 0 0 0 0 0 0 0 0 CCB address “00H” DI/DO 0 1 1 0 1 1 1 Command data CE CL CL CCB address “00H” 1 0 0 1 1 0 1 1 1 Command data (2) When CL is stoped at the high level CE 0 0 0 0 0 0 0 0 0 CCB address “00H” 2 Data communication stop command (1) When CL is stoped at the low level DI/DO 0 0 0 0 0 0 0 DI/DO 1 0 0 0 1 1 1 0 0 0 0 0 0 0 CCB address “00H” Command data www.onsemi.com 50 0 1 1 0 0 0 1 1 1 Command data LC75812PT Data Communication Flowchart of 4 Line Type or 3 Line Type CCB Format 1. Flowchart of the initial setting when power is turned on. Power on (Applications must observe that the power supply VDD rise time is at least 1ms.) Power supply stability (Applications must wait till the level of the power supply is stable) Serial data input (Execute instructions) Note: The flowchart for power-on time initialization is the same for the 4- and 3-wire CCB formats. See "Power Supply Sequence" and "System Reset." System reset clear (Display on, Key scanning is enabled, General-purpose output port state setting are enabled) 2. Flowchart of the serial data input Data communication start command transfer *39 Serial data input (Execute instructions) NO The controller wants to detect the key data read request signal (a low level on DO). Note: *39. In the case of the 4 line type CCB format, the transfers of data communication start command and data communication stop command are unnecessary, and, in the case of the 3 line type CCB format, these transfers are necessary. YES Data communication stop command transfer *39 3. Flowchart of the serial data output NO The controller acknowledges the key data read request (When the CE is low, the DO is low) Note: *40. In the case of the 4 line type CCB format, the transfer of data communication start command is unnecessary, and, in the case of the 3 line type CCB format, the transfer is necessary. *41. Because the serial data output has the role of the data communication stop command, it is not necessary to transfer the data communication stop command some other time. YES Data communication start command transfer *40 Serial data output (Key data and sleep acknowledge data read) *41 www.onsemi.com 51 LC75812PT Timing Chart of 4 Line Type and 3 Line Type CCB Format 1. Timing chart of 4 line type CCB format Example 1 Key on Key off Key input Key scan Key scan execution *42 CE CCB address (42H) Key scan execution *42 CCB address CCB address (42H) (42H) CCB address (43H) DI DO Serial data input (Execute instructions) Serial data output (Key data read) Key data read request Key data read request Example 2 Key input Key off Key off Key on Key on Key scan Key scan execution *42 Key scan execution *42 CE CCB address (42H) CCB address CCB address (42H) (42H) CCB address (43H) CCB address (43H) DI DO Serial data input (Execute instructions) Serial data output (Key data read) Key data read request Serial data output (Key data read) Key data read request Example 3 Key on Key input Key off Key off Key scan CE Key scan execution *42 Key scan execution *42 CCB address (42H) CCB address CCB address (42H) (42H) CCB address (43H) CCB address (43H) DI DO Key data read request Serial data input (Execute instructions) Serial data output (Key data read) Key data read request Note: *42. When the key data agrees for two key scans, the key scan execution time is 4800T[s]. And, when the key data does not agree for two key scans and the key scan is executed again, the key scan execution time is 9600T[s]. www.onsemi.com 52 T= 1 fosc Serial data output (Key data read) 1 T= f CK LC75812PT 2. Timing chart of 3 line type CCB format Example 1 Key on Key off Key input Key scan Key scan execution *42 CE CCB address (42H) CCB address (42H) CCB address (42H) Key scan execution *42 CCB address (43H) DI/DO Data communication start command Serial data input (Execute instructions) Data communication stop command Data communication start command Key data read request Serial data output (Key data read) Key data read request Example 2 Key on Key on Key off Key input Key off Key scan Key scan execution *42 Key scan execution *42 CE CCB address (42H) CCB address (42H) CCB address (42H) CCB address (43H) CCB address (43H) DI/DO Data communication start command Serial data input (Execute instructions) Data communication stop command Data communication start command Key data read request Serial data Data output communication (Key data start command read) Key data read request Serial data output (Key data read) Example 3 Key on Key input Key off Key off Key scan CE Key scan execution *42 Key scan execution *42 CCB address (42H) CCB address CCB address CCB address (42H) (42H) (43H) CCB address (43H) DI/DO Data communication start command Serial data input (Execute instructions) Key data read request Serial data output (Key data read) Data communication start command Key data read request Note: *42. When the key data agrees for two key scans, the key scan execution time is 4800T[s]. And, when the key data does not agree for two key scans and the key scan is executed again, the key scan execution time is 9600T[s]. www.onsemi.com 53 T= 1 fosc Serial data output (Key data read) 1 T= f CK Upper 4BIT (4) (5) (6) 0011 0100 0101 (8) (9) (10) (11) (12) (13) (14) (15) (16) 0111 1000 1001 1010 1011 1100 1101 1110 1111 (7) (3) 0010 0110 (2) MSB 0000 CG RAM(1) 0001 0000 LSB Lower 4BIT 0001 ( E 5 % www.onsemi.com 54 J K L M N O : ; < = > ? . / , I 9 * H 8 ) G 7 F D 4 $ 6 C 3 # & B 2 @ 0100 A 0 0011 1 ! 0010 LC75812PT-8565 Character Font (Standard) [ _ Z ] Y X W V U T S R Q P 0101 Î Ï Í Ì ij i I n IJ g o n £ n e å a Å ã s Ü Ù S Û Ú õ Ö Ò Õ G o Ë È Ô Ê É Ó Ä Â 1111 À Á 1110 ç 1101 Ç 1100 Ã ü ù 1011 ñ û ú 1010 Ñ ö ô ï ò ó ì î ë è í ê ä à é â 1001 á 1000 m l k z y i j x w v u t s r q p 0111 h g f e d c b a 0110 LC75812PT LC75812PT ORDERING INFORMATION Device Package Shipping (Qty / Packing) LC75812PT-8565-H TQFP100 14x14 / TQFP100 (Pb-Free / Halogen Free) 90 / Tray JEDEC LC75812PTH-8565-H TQFP100 14x14 / TQFP100 (Pb-Free / Halogen Free) 450 / Tray JEDEC LC75812PTS-8565-H TQFP100 14x14 / TQFP100 (Pb-Free / Halogen Free) 450 / Tray JEDEC ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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