LC75833E-E

Ordering number : EN 5580A CMOS LSI LC75833E, 75833W, 75833JE 1/3 Duty General-Purpose LCD Display Drivers Overview Package Dimensions The LC75833E, LC75833W, and LC75833JE are 1/3-duty general-purpose LCD display drivers that can be used for frequency display in electronic tuners under the control of a microcontroller. The LC75833E and LC75833W can drive an LCD with up to 105 segments directly, the LC75833JE can drive an LCD with up to 93 segments directly. The LC75833E and LC75833W and LC75833JE can also control up to 8 general-purpose output ports. Since the LC75833E, LC75833W, and LC75833JE use separate power supply systems for the LCD drive block and the logic block, the LCD driver block power-supply voltage can be set to any voltage in the range 2.7 to 6.0 volts, regardless of the logic block power-supply voltage. unit: mm 3156-QFP48E Features unit: mm 3163A-SQFP48 • Supports both 1/3 duty 1/2 bias and 1/3 duty 1/3 bias LCD drive under serial data control. LC75833E, LC75833W: up to 105 segments LC75833JE: up to 93 segments (without the S12, S23, S24, S35 segment output pins from the LC75833E, LC75833W) • Serial data input supports CCB format communication with the system controller. • Serial data control of the power-saving mode based backup function and all the segments forced off function • Serial data control of switching between the segment output port and the general-purpose output port functions • High generality, since display data is displayed directly without decoder intervention. • Independent VLCD for the LCD driver block (VLCD can be set to any voltage in the range 2.7 to 6.0 volts, regardless of the logic block power-supply voltage.) • The INH pin can force the display to the off state. • RC oscillator circuit [LC75833E] SANYO: QFP48E [LC75833W] SANYO: SQFP48 unit: mm 3148-QFP44MA [LC75833JE] • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. SANYO: QIP44MA 33098HA(OT)/22897HA(OT) No. 5580-1/19 LC75833E, 75833W, 75833JE Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage Conditions Ratings Unit VDD max VDD –0.3 to +7.0 V VLCD max VLCD –0.3 to +7.0 V Input voltage Output voltage Output current Allowable power dissipation VIN 1 CE, CL, DI, INH VIN 2 OSC VIN 3 VOUT 1 –0.3 to +7.0 V –0.3 to VDD + 0.3 V VLCD 1, VLCD 2 OSC –0.3 to VLCD + 0.3 V –0.3 to VDD + 0.3 V VOUT 2 S1 to S35, COM1 to COM3, P1 to P8 –0.3 to VLCD + 0.3 V IOUT 1 S1 to S35 300 µA IOUT 2 COM1 to COM3 3 mA IOUT 3 P1 to P8 5 mA Pd max Ta = 85°C 150 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Note: The LC75833JE does not have the S12, S23, S24, S35 output pins. Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V Ratings Parameter Supply voltage Input voltage Input high-level voltage Input low-level voltage Symbol Conditions min typ max Unit VDD VDD 2.7 6.0 V VLCD VLCD 2.7 6.0 V VLCD1 VLCD1 2/3 VLCD VLCD V VLCD2 VLCD2 1/3 VLCD VLCD V 6.0 V VIH CE, CL, DI, INH 0.8 VDD VIL CE, CL, DI, INH 0 Recommended external resistance ROSC OSC Recommended external capacitance COSC OSC Guaranteed oscillation range fOSC OSC 0.2 VDD 39 1000 19 38 V kΩ pF 76 kHz Data setup time tds CL, DI: Figure 2 160 ns Data hold time tdh CL, DI: Figure 2 160 ns CE wait time tcp CE, CL: Figure 2 160 ns CE setup time tcs CE, CL: Figure 2 160 ns CE hold time tch CE, CL: Figure 2 160 ns High-level clock pulse width tøH CL: Figure 2 160 ns Low-level clock pulse width tøL CL: Figure 2 160 Rise time tr CE, CL, DI: Figure 2 Fall time tf CE, CL, DI: Figure 2 INH switching time tc INH, CE: Figure 3 ns 160 160 10 ns ns µs No. 5580-2/19 LC75833E, 75833W, 75833JE Electrical Characteristics for the Allowable Operating Ranges Ratings Parameter Symbol Conditions Hysteresis width VH CE, CL, DI, INH Input high level current IIH CE, CL, DI, INH; VI = 6.0 V Input low level current Output high-level voltage Output low-level voltage Output middle-level voltage*1 Oscillator frequency Current drain IIL CE, CL, DI, INH; VI = 0 V min typ Unit max 0.1 VDD V 5.0 µA –5.0 µA VOH 1 S1 to S35; IO = –20 µA VLCD – 0.9 V VOH 2 COM1 to COM3; IO = –100 µA VLCD – 0.9 V VOH 3 P1 to P8; IO = –1 mA VLCD – 0.9 VOL 1 S1 to S35; IO = 20 µA 0.9 V VOL 2 COM1 to COM3; IO = 100 µA 0.9 V VOL 3 P1 to P8; IO = 1 mA 0.9 V VMID 1 COM1 to COM3; 1/2 bias, IO = ±100 µA 1/2 VLCD – 0.9 1/2 VLCD + 0.9 V VMID 2 S1 to S35; 1/3 bias, IO = ±20 µA 2/3 VLCD – 0.9 2/3 VLCD + 0.9 V VMID 3 S1 to S35; 1/3 bias, IO = ±20 µA 1/3 VLCD – 0.9 1/3 VLCD + 0.9 V VMID 4 COM1 to COM3; 1/3 bias, IO = ±100 µA 2/3 VLCD – 0.9 2/3 VLCD + 0.9 V VMID 5 COM1 to COM3; 1/3 bias, IO = ±100 µA 1/3 VLCD – 0.9 1/3 VLCD + 0.9 V fOSC OSC; ROSC = 39 kΩ COSC = 1000 pF IDD 1 VDD; power saving mode IDD 2 ILCD 1 VDD; VDD = 6.0 V, output open, fosc = 38 k Hz VLCD; power saving mode ILCD 2 VLCD; VLCD = 6.0 V, output open 1/2 bias, fosc = 38 k Hz ILCD 3 VLCD; VLCD = 6.0 V, output open 1/3 bias, fosc = 38 k Hz 30.4 V 38 45.6 kHz 5 µA 500 µA 5 µA 100 200 µA 60 120 µA 250 Note: *1 Excluding the bias voltage generation divider resistors built in the VLCD1 and VLCD2. (See Figure 1.) The LC75833JE does not have the S12, S23, S24, S35 output pins. No. 5580-3/19 LC75833E, 75833W, 75833JE VLCD VLCD1 To the common segments drivers VLCD2 Except these resistors VSS A06550 Figure 1 1. When CL is stopped at the low level VIH CE VIL tøH CL tr DI tøL VIH 50% VIL tf tcp tcs tch VIH VIL tds tdh A06551 2. When CL is stopped at the high level VIH CE VIL tøL tøH VIH 50% VIL CL tf tr tcp tcs tch VIH VIL DI tds tdh A06552 Figure 2 No. 5580-4/19 LC75833E, 75833W, 75833JE COM1 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 COM2 COM1 S34 S33 S32 S31 S30 S29 S28 S27 S26 Pin Assignments 36 37 25 24 LC75833E LC75833W 48 1 23 22 LC75833JE 44 1 12 11 S25 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 P1/S1 P2/S2 P3/S3 P4/S4 P5/S5 P6/S6 P7/S7 P8/S8 S9 S10 S11 13 12 33 34 COM3 VDD VLCD VLCD1 VLCD2 VSS OSC INH CE CL DI S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 P1/S1 P2/S2 P3/S3 P4/S4 P5/S5 P6/S6 P7/S7 P8/S8 S9 S10 S11 S12 COM2 COM3 VDD VLCD VLCD1 VLCD2 VSS OSC INH CE CL DI A06582 A06549 Common driver S2/P2 S1/P1 S9 S8/P8 S35 S34 COM1 COM2 COM3 Block Diagram Segment driver & latch INH OSC Clock generator Shift register VDD VLCD VLCD1 Address detector VLCD2 CE CL DI VSS A06553 Note: The LC75833JE does not have the S12, S23, S24, S35 output pins. No. 5580-5/19 LC75833E, 75833W, 75833JE Pin Functions Pin No. Pin LC75833E, 75833W LC75833JE Active I/O Handling when unused Segment outputs for displaying the display data transferred by serial data input. The pins S1/P1 to S8/P8 can be used as general-purpose output ports when so set up by the control data. — O Open Functions S1/P1 to S8/P8 S9 to S35 1 to 8 1 to 8 9 to 35 9 to 31 COM1 COM2 COM3 36 37 38 32 33 34 Common driver outputs. The frame frequency fO is given by: fO = (fOSC/384) Hz. — O Open OSC 44 40 Oscillator connection An oscillator circuit is formed by connecting an external resistor and capacitor to this pin. — I/O VDD CE CL DI 46 47 48 42 43 44 Serial data transfer inputs. These pins are connected to the control microprocessor. I GND L I GND CE: Chip enable CL: Synchronization clock DI: Transfer data H — INH 45 41 Display off control input •INH = low (VSS): Off S1/P1 to S8/P8 = Low (These pins are forcibly set to the segment output port function and fixed at the VSS level.) S9 to S35 = Low (VSS), COM1 to COM3 = Low (VSS) •INH = high (VDD): On Note that serial data transfers can be performed when the display is forced off by this pin. VLCD1 41 37 Used to apply the LCD drive 2/3-bias voltage externally. This pin must be connected to VLCD2 when 1/2-bias drive is used. — I Open VLCD2 42 38 Used to apply the LCD drive 1/3-bias voltage externally. This pin must be connected to VLCD1 when 1/2-bias drive is used. — I Open VDD 39 35 Logic block power supply. Provide a voltage in the range 2.7 to 6.0 V. — — — VLCD 40 36 LCD driver block power supply. Provide a voltage in the range 2.7 to 6.0 V. — — — VSS 43 39 Ground pin. Connect to ground. — — — Note: The LC75833JE does not have the S12, S23, S24, S35 output pins. No. 5580-6/19 LC75833E, 75833W, 75833JE Serial Data Transfer Format 1. When CL is stopped at the low level CE CL DI 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D3 CCB address 8 bits 0 0 0 P0 Display data 36 bits 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D37 D38 D39 CCB address 8 bits 0 1 1 0 0 0 1 0 B1 B2 B3 A0 A1 A2 A3 D73 D68 D69 D70 D71 D72 D74 D75 Display data 33 bits D104 D105 P1 P2 P3 DR SC BU Control data 10 bits 0 0 0 0 Display data 36 bits B0 CCB address 8 bits D32 D33 D34 D35 D36 0 0 0 0 0 0 0 0 0 Fixed data 13 bits 0 0 DD 2 bits 0 0 0 0 Fixed data 10 bits 0 0 0 1 DD 2 bits 0 0 0 0 1 0 DD 2 bits A06554 Note: DD ... Direction data No. 5580-7/19 LC75833E, 75833W, 75833JE 2. When CL is stopped at the high level CE CL DI 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D3 CCB address 8 bits 0 0 0 P0 Display data 36 bits 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D37 D38 D39 CCB address 8 bits 0 1 1 0 0 0 1 0 B1 B2 B3 A0 A1 A2 A3 D68 D69 D70 D71 D72 D73 D74 D75 Display data 33 bits D104 D105 P1 P2 P3 DR SC BU Control data 10 bits 0 0 0 0 Display data 36 bits B0 CCB address 8 bits D32 D33 D34 D35 D36 0 0 0 0 0 0 0 0 0 Fixed data 13 bits 0 0 DD 2 bits 0 0 0 0 Fixed data 10 bits 0 0 0 1 DD 2 bits 0 0 0 0 1 0 DD 2 bits A06555 Note: DD ... Direction data • CCB address...............46H • D1 to D105.................Display data (At the LC75833JE, the display data D34 to D36, D67 to D72, D103 to D105 must be set to 0. • P0 to P3 ......................Segment output port/general-purpose output port switching control data • DR ..............................1/2-bias drive or 1/3-bias drive switching control data • SC...............................Segments on/off control data • BU ..............................Normal mode/power-saving mode control data No. 5580-8/19 LC75833E, 75833W, 75833JE Serial Data Transfer Examples • At the LC75833E and LC75833W when 73 or more segments are used, at the LC75833JE when 64 or more segments are used. 144 bits of serial data must be sent. 8 bits 48 bits 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D3 D31 D32 D33 D34 D35 D36 0 0 0 P0 P1 P2 P3 DR SC BU 0 0 D37 D38 D39 D67 D68 D69 D70 D71 D72 0 0 0 0 0 0 0 0 0 0 0 1 D73 D74 D75 D103 D104 D105 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 A06556 Note: At the LC75833JE, the display data D34 to D36, D67 to D72, D103 to D105 must be set to 0. • At the LC75833E and LC75833W when used with less than 73 segments, at the LC75833JE when used with less than 64 segments. Transfer either 48 bits or 96 bits of serial data depending on the number of segments used. However, the serial data shown in the figure below (the display data D1 to D36 and the control data) must be sent. 8 bits 48 bits 0 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D3 D31 D32 D33 D34 D35 D36 0 0 0 P0 P1 P2 P3 DR SC BU 0 0 A06557 Note: At the LC75833JE, the display data D34 to D36 must be set to 0. Control Data Functions 1. P0 to P3: Segment output port/general-purpose output port switching control data. These control data bits switch the S1/P1 to S8/P8 output pins between their segment output port and general-purpose output port functions. Control data Output pin states P0 P1 P2 P3 S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8 0 0 0 0 S1 S2 S3 S4 S5 S6 S7 S8 0 0 0 1 P1 S2 S3 S4 S5 S6 S7 S8 0 0 1 0 P1 P2 S3 S4 S5 S6 S7 S8 0 0 1 1 P1 P2 P3 S4 S5 S6 S7 S8 0 1 0 0 P1 P2 P3 P4 S5 S6 S7 S8 0 1 0 1 P1 P2 P3 P4 P5 S6 S7 S8 0 1 1 0 P1 P2 P3 P4 P5 P6 S7 S8 0 1 1 1 P1 P2 P3 P4 P5 P6 P7 S8 1 0 0 0 P1 P2 P3 P4 P5 P6 P7 P8 Note: Sn (n = 1 to 8): Segment output ports Pn (n = 1 to 8): General-purpose output ports No. 5580-9/19 LC75833E, 75833W, 75833JE Also note that when the general-purpose output port function is selected, the output pins and the display data will have the correspondences listed in the tables below. Output pin Corresponding display data Output pin Corresponding display data S1/P1 D1 S5/P5 D13 S2/P2 D4 S6/P6 D16 S3/P3 D7 S7/P7 D19 S4/P4 D10 S8/P8 D22 For example, if the output pin S4/P4 has the general-purpose output port function selected, it will output a high level (VLCD) when the display data D10 is 1, and will output a low level (VSS) when D10 is 0. 2. DR: 1/2-bias drive or 1/3-bias drive switching control data This control data bit selects either 1/2-bias drive or 1/3-bias drive. DR Drive type 0 1/3-bias drive 1 1/2-bias drive 3. SC: Segments on/off control data This control data bit controls the on/off state of the segments. SC Display state 0 On 1 Off However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 4. BU: Normal mode/power-saving mode control data This control data bit selects either normal mode or power-saving mode. BU Mode 0 Normal mode 1 Power saving mode (The OSC pin oscillator is stopped, and the common and segment output pins go to the VSS level. However, the S1/P1 to S8/P8 output pins that are set to be general-purpose output ports by the control data P0 to P3 can be used as generalpurpose output ports.) No. 5580-10/19 LC75833E, 75833W, 75833JE Display Data to Segment Output Pin Correspondence Segment output pin COM1 COM2 COM3 Segment output pin COM1 COM2 COM3 S1/P1 D1 D2 D3 S19 D55 D56 D57 S2/P2 D4 D5 D6 S20 D58 D59 D60 S3/P3 D7 D8 D9 S21 D61 D62 D63 S4/P4 D10 D11 D12 S22 D64 D65 D66 S5/P5 D13 D14 D15 S23 D67 D68 D69 S6/P6 D16 D17 D18 S24 D70 D71 D72 S7/P7 D19 D20 D21 S25 D73 D74 D75 S8/P8 D22 D23 D24 S26 D76 D77 D78 S9 D25 D26 D27 S27 D79 D80 D81 S10 D28 D29 D30 S28 D82 D83 D84 S11 D31 D32 D33 S29 D85 D86 D87 S12 D34 D35 D36 S30 D88 D89 D90 S13 D37 D38 D39 S31 D91 D92 D93 S14 D40 D41 D42 S32 D94 D95 D96 S15 D43 D44 D45 S33 D97 D98 D99 S16 D46 D47 D48 S34 D100 D101 D102 S17 D49 D50 D51 S35 D103 D104 D105 S18 D52 D53 D54 Note: This applies to the case where the S1/P1 to S8/P8 output pins are set to be segment output ports. The LC75833JE do not have the S12, S23, S24, S35 output pins. For example, the table below lists the segment output states for the S11 output pin. Display data D31 D32 D33 Segment output pin (S11) state 0 0 0 The LCD segments corresponding to COM1 to COM3 are off. 0 0 1 The LCD segments corresponding to COM3 is on. 0 1 0 The LCD segments corresponding to COM2 is on. 0 1 1 The LCD segments corresponding to COM2 and COM3 are on. 1 0 0 The LCD segments corresponding to COM1 is on. 1 0 1 The LCD segments corresponding to COM1 and COM3 are on. 1 1 0 The LCD segments corresponding to COM1 and COM2 are on. 1 1 1 The LCD segments corresponding to COM1 to COM3 are on. No. 5580-11/19 LC75833E, 75833W, 75833JE 1/3-Duty 1/2-Bias Drive Technique fosc [Hz] 384 VLCD COM1 VLCD1, VLCD2 0V VLCD COM2 VLCD1, VLCD2 0V VLCD COM3 VLCD1, VLCD2 0V VLCD LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off. VLCD1, VLCD2 0V VLCD LCD driver output when only LCD segments corresponding to COM1 are on (lit). VLCD1, VLCD2 0V VLCD LCD driver output when only LCD segments corresponding to COM2 are on. VLCD1, VLCD2 0V VLCD LCD driver output when LCD segments corresponding to COM1 and COM2 are on. VLCD1, VLCD2 0V VLCD LCD driver output when only LCD segments corresponding to COM3 are on. VLCD1, VLCD2 0V VLCD LCD driver output when LCD segments corresponding to COM1 and COM3 are on. VLCD1, VLCD2 0V VLCD LCD driver output when LCD segments corresponding to COM2 and COM3 are on. VLCD1, VLCD2 0V VLCD LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on. VLCD1, VLCD2 0V A06558 1/3-Duty 1/2-Bias Waveforms No. 5580-12/19 LC75833E, 75833W, 75833JE 1/3-Duty 1/3-Bias Technique fosc [Hz] 384 COM1 VLCD VLCD1 VLCD2 0V COM2 VLCD VLCD1 VLCD2 0V COM3 VLCD VLCD1 VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off. VLCD VLCD1 VLCD2 0V LCD driver output when only LCD segments corresponding to COM1 are on (lit). VLCD VLCD1 VLCD2 0V LCD driver output when only LCD segments corresponding to COM2 are on. VLCD VLCD1 VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM2 are on. VLCD VLCD1 VLCD2 0V LCD driver output when only LCD segments corresponding to COM3 are on. VLCD VLCD1 VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM3 are on. VLCD VLCD1 VLCD2 0V LCD driver output when LCD segments corresponding to COM2 and COM3 are on. VLCD VLCD1 VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on. VLCD VLCD1 VLCD2 0V A06559 1/3-Duty 1/3-Bias Waveforms No. 5580-13/19 LC75833E, 75833W, 75833JE The INH pin and Display Control Since the LSI internal data (the display data and the control data) is undefined when power is first applied, applications should set the INH pin low at the same time as power is applied to turn off the display (LC75833E, LC75833W: This sets the S1/P1 to S8/P8, S9 to S35, and COM1 to COM3 to the VSS level. LC75833JE: This sets the S1/P1 to S8/P8, S9 to S11, S13 to S22, S25 to S34, and COM1 to COM3 to the VSS level.) and during this period send serial data from the controller. The controller should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless displays at power on. (See Figure 3.) Notes on the Power On/Off Sequences Applications should observe the following sequence when turning the LC75833E, LC75833W, and LC75833JE power on and off. • At power on: Logic block power supply (VDD) on → LCD driver block power supply (VLCD) on • At power off: LCD driver block power supply (VLCD) off → Logic block power supply (VDD) off However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. t2 t1 t3 VDD VLCD INH VIL tc CE D1 to D36 Internal data P0 to P3 DR, SC, BU Internal data (D37 to D72) Internal data (D73 to D105) VIL Display and control data transfer Undefined Defined Undefined Undefined Defined Undefined Undefined Defined Undefined Note: t1 ≥ 0 t2 > 0 t3 ≥ 0 (t2 > t3) tc ... 10 µs min Note: At the LC75833JE, the display data D34 to D36, D67 to D72, D103 to D105 must be set to 0. A06560 Figure 3 Notes on Controller Transfer of Display Data Since the LC75833E, LC75833W, and LC75833JE accept display data divided into three separate transfer operations, we recommend that applications transfer all of the display data within a period of less than 30 ms to prevent observable degradation of display quality. No. 5580-14/19 LC75833E, 75833W, 75833JE Sample Application Circuit 1 1/2 Bias (for use with normal size panels) • LC75833E, LC75833W (P1) (P2) *2 VDD OSC VSS +5 V COM1 COM2 COM3 P1/S1 P2/S2 VLCD VLCD1 C ≥ 0.047 µF C P8/S8 S9 VLCD2 S33 S34 S35 INH CE CL DI From the controller Used for functions such as backlight control LCD panel (up to 105 segments) +3 V (P8) General-purpose output ports A06561 Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. • LC75833JE *2 +3 V VDD VSS +5 V COM1 COM2 COM3 P1/S1 P2/S2 VLCD VLCD1 C ≥ 0.047 µF From the controller OSC C VLCD2 INH CE CL DI P8/S8 S9 S10 S11 S13 S22 S25 (P8) General-purpose output ports Used for functions such as backlight control LCD panel (up to 93 segments) (P1) (P2) S34 A06583 Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. No. 5580-15/19 LC75833E, 75833W, 75833JE Sample Application Circuit 2 1/2 Bias (for use with large panels) • LC75833E, LC75833W (P1) (P2) *2 VDD OSC VSS +5 V C ≥ 0.047 µF 10kΩ ≥ R ≥ 1kΩ COM1 COM2 COM3 P1/S1 P2/S2 LCD panel (up to 105 segments) +3 V (P8) VLCD C R VLCD1 R VLCD2 P8/S8 S9 S33 S34 S35 INH CE CL DI From the controller General-purpose output ports Used for functions such as backlight control A06562 Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. • LC75833JE *2 +3 V VDD VSS +5 V From the controller COM1 COM2 COM3 P1/S1 P2/S2 VLCD R C ≥ 0.047 µF 10kΩ ≥ R ≥ 1kΩ OSC C R VLCD1 VLCD2 INH CE CL DI P8/S8 S9 S10 S11 S13 S22 S25 (P8) General-purpose output ports Used for functions such as backlight control LCD panel (up to 93 segments) (P1) (P2) S34 A06584 Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. No. 5580-16/19 LC75833E, 75833W, 75833JE Sample Application Circuit 3 1/3 Bias (for use with normal size panels) • LC75833E, LC75833W (P1) (P2) *2 VDD OSC VSS +5 V VLCD VLCD1 C ≥ 0.047 µF COM1 COM2 COM3 P1/S1 P2/S2 LCD panel (up to 105 segments) +3 V (P8) C C P8/S8 S9 VLCD2 S33 S34 S35 INH CE CL DI From the controller General-purpose output ports Used for functions such as backlight control A06562 Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. • LC75833JE *2 +3 V VDD VSS +5 V From the controller COM1 COM2 COM3 P1/S1 P2/S2 VLCD VLCD1 C ≥ 0.047 µF OSC C C VLCD2 INH CE CL DI P8/S8 S9 S10 S11 S13 S22 S25 (P8) General-purpose output ports Used for functions such as backlight control LCD panel (up to 93 segments) (P1) (P2) S34 A06584 Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. No. 4801-17/19 LC75833E, 75833W, 75833JE Sample Application Circuit 4 1/3 Bias (for use with large panels) • LC75833E, LC75833W *2 +3 V VDD VSS +5 V R R C ≥ 0.047 µF 10 kΩ ≥ R ≥ 1 kΩ From the controller C C R OSC COM1 COM2 COM3 P1/S1 P2/S2 VLCD VLCD1 VLCD2 INH CE CL DI P8/S8 S9 S33 S34 S35 (P8) General-purpose output ports Used for functions such as backlight control LCD panel (up to 105 segments) (P1) (P2) A06563 Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. No. 5580-18/19 LC75833E, 75833W, 75833JE • LC75833JE *2 +3 V VDD VSS +5 V R R C ≥ 0.047 µF 10 kΩ ≥ R ≥ 1 kΩ From the controller C C R OSC COM1 COM2 COM3 P1/S1 P2/S2 VLCD VLCD1 VLCD2 INH CE CL DI P8/S8 S9 S10 S11 S13 S22 S25 (P8) General-purpose output ports Used for functions such as backlight control LCD panel (up to 93 segments) (P1) (P2) S34 A06585 Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ① Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March 1998. Specifications and information herein are subject to change without notice. PS No. 5580-19/19