LC75841PES-H

LC75841PE Static Drive, 1/2-Duty Drive General-Purpose LCD Driver Overview The LC75841PE is static drive or 1/2-duty drive, microcontroller-controlled general-purpose LCD driver that can be used in applications such as frequency display in products with electronic tuning. In addition to being capable to drive up to 54 segments directly, it can control up to 4 generalpurpose output ports. Features  Serial data control of switching between static drive mode and 1/2 duty drive mode. When 1/1-duty: Capable of driving up to 27 segments When 1/2-duty: Capable of driving up to 54 segments  Serial data input supports CCB* format communication with the system controller.  Serial data control of the power-saving mode based backup function and the all segments forced off function.  Serial data control of switching between the segment output port and general-purpose output port functions (up to 4 general-purpose output ports).  Serial data control of the frame frequency of the common and segment output waveforms.  Either RC oscillator operating or external clock operating mode can be selected with the serial control data.  High generality, since display data is displayed directly without the intervention of a decoder circuit.  The INH pin allows the display to be forced to the off state.  Allows compatible operation with the LC75842 (842 mode transfer function). www.onsemi.com LQFP36 7x7 / QFP36 * Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and the bus addresses are controlled by ON Semiconductor. ORDERING INFORMATION See detailed ordering and shipping information on page 19 of this data sheet. © Semiconductor Components Industries, LLC, 2017 June 2017 - Rev. 1 1 Publication Order Number : LC75841PE/D LC75841PE Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max VDD 0.3 to +7.0 Input voltage VIN1 CE, CL, DI, INH 0.3 to +7.0 VIN2 OSC 0.3 to VDD+0.3 0.3 to VDD+0.3 V 300 A V V Output voltage VOUT S1 to S27, COM1, COM2, P1 to P4, OSC Output current IOUT1 IOUT2 S1 to S27 COM1, COM2 3 IOUT3 P1 to P4 5 Allowable power dissipation Pd max Ta = 105C Operating temperature Topr 40 to +105 C Storage temperature Tstg 55 to +125 C 50 mA mW Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ranges at Ta = 40 to +105C, VSS = 0 V Parameter Symbol Conditions Ratings min typ max Supply voltage VDD VDD 4.0 6.0 Input high-level voltage VIH1 CE, CL, DI, INH 0.45VDD 6.0 VIH2 OSC External clock operating mode 0.45VDD VDD VIL1 CE, CL, DI, INH 0 VIL2 OSC External clock operating mode 0 0.2VDD 0.2VDD Rosc OSC RC oscillator operating mode Input low-level voltage Recommended external resistor for RC oscillation Recommended external capacitor for RC oscillation Guaranteed range of RC oscillation External clock operating frequency External clock duty cycle Cosc unit V V V 39 kΩ 1000 pF OSC RC oscillator operating mode fosc OSC RC oscillator operating mode fCK 19 38 76 kHz 19 38 76 kHz 30 50 70 % Data setup time tds OSC External clock operating mode [Figure 3] OSC External clock operating mode [Figure 3] CL, DI [Figure 1], [Figure 2] 160 ns Data hold time tdh CL, DI [Figure 1], [Figure 2] 160 ns CE wait time tcp CE, CL [Figure 1], [Figure 2] 160 ns CE setup time tcs CE, CL [Figure 1], [Figure 2] 160 ns CE hold time tch CE, CL [Figure 1], [Figure 2] 160 ns High-level clock pulse width tH CL [Figure 1], [Figure 2] 160 ns 160 ns DCK Low-level clock pulse width tL CL [Figure 1], [Figure 2] Rise time tr CE, CL, DI [Figure 1], [Figure 2] 160 Fall time tf CE, CL, DI [Figure 1], [Figure 2] 160 INH switching time tc INH, CE [Figure 4], [Figure 5], [Figure 6] 10 ns ns s Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2 LC75841PE Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Pin Conditions Ratings min typ max Hysteresis VH CE, CL, DI, INH Input high-level current IIH1 CE, CL, DI, INH VI = 6.0 V IIH2 OSC Input low-level current IIL1 CE, CL, DI, INH VI = VDD External clock operating mode VI = 0 V IIL2 OSC Output high-level voltage VOH1 S1 to S27 VOH2 COM1, COM2 VOH3 P1 to P4 IO = 100 A IO = 1 mA VOL1 S1 to S27 IO = 20 A 0.9 VOL2 COM1, COM2 0.9 VOL3 P1 to P4 IO = 100 A IO = 1 mA Output low-level voltage 0.03VDD VI = 0 V External clock operating mode IO = 20 A Output middle-level voltage Oscillator frequency VMID COM1, COM2 1/2 bias IO = 100 A fosc OSC Current drain IDD1 VDD RC oscillator operating mode, Rosc = 39 kΩ, Cosc = 1000 pF Power-saving mode IDD2 VDD IDD3 IDD4 IDD5 VDD VDD VDD VDD = 6.0 V, Output open, RC oscillator operating mode, fosc = 38 kHz, Static VDD = 6.0 V, Output open, RC oscillator operating mode, fosc = 38 kHz, 1/2 duty VDD = 6.0 V, Output open, External clock operating mode, fCK = 38 kHz, VIH2 = 0.5VDD, VIL2 = 0.1VDD, Static VDD = 6.0 V, Output open, External clock operating mode, fCK = 38 kHz, VIH2 = 0.5VDD, VIL2 = 0.1VDD, 1/2 duty unit V 5.0 5.0 A 5.0 A 5.0 VDD0.9 VDD0.9 V VDD0.9 V 0.9 1/2VDD 0.9 30.4 1/2VDD +0.9 38 45.6 V kHz 15 350 700 1500 3000 450 900 1600 3200 A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 3 LC75841PE 1. When CL is stopped at the low level CL VIH1 tcp VIL1 tds    tf   DI tL tr VIL1   tH VIH1 50% VIL1  VIH1 CE tcs tch tdh [Figure 1] 2. When CL is stopped at the high level  VIH1 CE  VIL1 tH CL VIH1 50% VIL1 tr DI VIL1 tds tcp tcs   VIH1    tf  tL tdh [Figure 2] 3. OSC pin clock timing in external clock operating mode tCKH OSC tCKL fCK= VIH2 50% VIL2 1 tCKH+ tCKL [kHz] tCKH 100[%] DCK= tCKH+ tCKL [Figure 3] www.onsemi.com 4 tch LC75841PE Package Dimensions unit : mm LQFP36 7x7 / QFP36 CASE 561AV ISSUE A 0.50.2 9.00.2 9.00.2 36 7.00.1 7.00.1 1 2 0.65 0.30.1 (1.5) 0 to 10 0.10.1 1.7 MAX (0.9) 0.150.05 0.13 0.10 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 8.40 XXXXXXXX YDD 8.40 (Unit: mm) XXXXX = Specific Device Code Y = Year DD = Additional Traceability Data XXXXXXXX YMDDD XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 0.65 0.43 1.00 *This information is generic. Please refer to device data sheet for actual part marking. NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 LC75841PE S27 S26 S25 S24 S23 S22 S21 S20 S19 27 26 25 24 23 22 21 20 19 Pin Assignment OSC 28 18 S18 VDD 29 17 S17 INH 30 16 S16 VSS 31 15 S15 CE 32 14 S14 CL 33 13 S13 DI 34 12 S12 COM2 35 11 S11 COM1 36 10 S10 9 Top view S9 8 S7 S8 7 6 S6 5 S5 4 P4/S4 3 P3/S3 2 P2/S2 P1/S1 1 LC75841PE COMMON DRIVER SEGMENT DRIVER & LATCH INH OSC CONTROL REGISTER CLOCK GENERATOR SHIFT REGISTER CCB INTERFACE VDD www.onsemi.com 6 CE CL DI VSS S1/P1 S2/P2 S3/P3 S4/P4 S5 S26 S27 COM2 COM1 Block Diagram LC75841PE Pin Functions Handling Symbol Pin No. Function Active I/O when unused S1/P1 to S4/P4 1 to 4 S5 to S27 5 to 27 COM1 36 COM2 35 OSC 28 Segment outputs for displaying the display data transferred by serial data input. The S1/P1 to S4/P4 pins can be used as general-purpose output ports when so set - O OPEN - O OPEN - I/O VDD H I up by the control data. Common driver outputs. The frame frequency is fo [Hz]. Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor to this pin. This pin can be used as the external clock input pin if external clock operating mode is selected with the control data. Serial data transfer inputs. Must be connected to the controller. CE 32 CE: Chip enable CL 33 CL: Synchronization clock DI 34 DI: Transfer data I GND - I L I GND Display off control input • INH = low (VSS) ...Display forced off S1/P1 to S4/P4 = low (VSS) (These pins are forcibly set to the segment output port function and held at the VSS level.) INH 30 S5 to S27 = low (VSS) COM1, COM2 = low (VSS) OSC = Z (high impedance) RC oscillation stopped Inhibits external clock input. • INH = high (VDD)...Display on RC oscillation enabled (RC oscillator operating mode) Enables external clock input (external clock operating mode) However, serial data transfer is possible when the display is forced off. VDD 29 Power supply. Provide a voltage in the range 4.0 to 6.0 V. - - - VSS 31 Ground pin. Must be connected to ground. - - - www.onsemi.com 7 LC75841PE Serial Data Transfer Formats (1) Static drive mode 1. When CL is stopped at the low level CE CL DI 0 0 1 0 0 0 1 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 0 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 27 bits Control data 12 bits DD 1 bit 2. When CL is stopped at the high level CE CL DI 0 0 1 0 0 0 1 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 0 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 27 bits Control data 12 bits Note: DD is the direction data. • CCB address ....... "44H" • D1 to D27 ......... Display data • P0 to P2 .............. Segment output port/general-purpose output port switching control data • DT ...................... Static drive or 1/2 duty drive switching control data • FC0 to FC2 ......... Common/segment output waveform frame frequency control data • OC ...................... RC oscillator operating mode/external clock operating mode switching control data • SC ...................... Segments on/off control data • BU ...................... Normal mode/power-saving mode control data www.onsemi.com 8 DD 1 bit LC75841PE (2) 1/2 duty drive mode 1. When CL is stopped at the low level CL DI 0 0 1 0 0 0 1 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 28 bits Control data 11 bits DD 1 bit     CCB address 8 bits     CE 0 0 1 0 0 0 1 0 D29 D30 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 0 0 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Fixed data 13 bits Display data 26 bits DD 1 bit 2. When CL is stopped at the high level CL 0 0 1 0 0 0 1 DI 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 28 bits Control data 11 bits DD 1 bit     CCB address 8 bits     CE 0 0 1 0 0 0 1 0 D29 D30 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Fixed data 13 bits Display data 26 bits Note: DD is the direction data. • CCB address ....... "44H" • D1 to D54 ......... Display data • P0 to P2 .............. Segment output port/general-purpose output port switching control data • DT ...................... Static drive or 1/2 duty drive switching control data • FC0 to FC2 ......... Common/segment output waveform frame frequency control data • OC ...................... RC oscillator operating mode/external clock operating mode switching control data • SC ...................... Segments on/off control data • BU ...................... Normal mode/power-saving mode control data www.onsemi.com 9 DD 1 bit LC75841PE Serial Data Transfer Formats (When in 842 mode data transfer) (1) 1/2 duty drive mode (When in 842 mode data transfer) 1. When CL is stopped at the low level CL DI 0 0 1 0 0 0 1 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 BU SC 0 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 28 bits Control data DD 3 bits 1bit     CCB address 8 bits     CE 0 0 1 0 0 0 1 0 D29 D30 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits Display data 26 bits Fixed data 5 bits DD 1bit 2. When CL is stopped at the high level CL 0 0 1 0 0 0 1 DI 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 BU SC 0 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 28 bits Control DD data 1 bit 3 bits     CCB address 8 bits     CE 0 0 1 0 0 0 1 0 D29 D30 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bits D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 1 Display data 26 bits Note: DD is the direction data. • CCB address ....... "44H" • D1 to D54 ......... Display data • BU ...................... Normal mode/power-saving mode control data • SC ...................... Segments on/off control data www.onsemi.com 10 Fixed data 5 bits DD 1 bit LC75841PE Serial Data Transfer Examples (1) Static drive mode The serial data shown in the figure below must be sent. 8 bits 0 0 1 0 0 40 bits 0 1 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 0 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 (2) 1/2 duty drive mode • When 29 or more segments are used 96 bits of serial data (including CCB address bits) must be sent. 8 bits 0 0 1 0 0 40 bits 0 1 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 D29 D30 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 B0 B1 B2 B3 A0 A1 A2 A3 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 • When fewer than 29 segments are used The serial data shown below (the D1 to D28 display data and the control data) must always be sent. 8 bits 0 0 1 0 0 40 bits 0 1 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 Serial Data Transfer Examples (When in 842 mode data transfer) (1) 1/2 duty drive mode (When in 842 mode data transfer) • When 29 or more segments are used 80 bits of serial data (including CCB address bits) must be sent. 8 bits 0 0 1 0 0 32 bits 0 1 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 BU SC 0 0 D29 D30 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 0 1 B0 B1 B2 B3 A0 A1 A2 A3 0 0 1 0 0 0 1 0 0 0 0 0 B0 B1 B2 B3 A0 A1 A2 A3 • When fewer than 29 segments are used The serial data shown in the figure below (the D1 to D28 display data, and the control data) must be sent. 8 bits 0 0 1 0 0 32 bits 0 1 0 D1 D2 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 BU SC 0 B0 B1 B2 B3 A0 A1 A2 A3 www.onsemi.com 11 0 LC75841PE Control Data Functions 1. P0 to P2: Segment output port/general-purpose output port switching control data These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S4/P4 output pins. However, segment output port is forcibly selected when in 842 mode data transfer. Control data Output pin state P0 P1 P2 S1/P1 S2/P2 S3/P3 S4/P4 0 0 0 S1 S2 S3 S4 0 0 1 P1 S2 S3 S4 0 1 0 P1 P2 S3 S4 0 1 1 P1 P2 P3 S4 1 0 0 P1 P2 P3 P4 Note: Sn (n = 1 to 4): Segment output ports Pn (n = 1 to 4): General-purpose output ports Note that when the general-purpose output port function is selected, the correspondence between the output pins and the display data will be that shown in the table. Corresponding display data Output pin Static drive mode 1/2 duty drive mode S1/P1 D1 D1 S2/P2 D2 D3 S3/P3 D3 D5 S4/P4 D4 D7 For example, if the general-purpose output port function is selected for the S4/P4 output pin in 1/2 duty drive mode, it will output a high level (VDD) when display data D7 is 1, and a low level (VSS) when D7 is 0. 2. DT: Static drive mode or 1/2 duty drive mode switching control data This control data bit selects either static drive mode or 1/2 duty drive mode. However, 1/2 duty drive mode is forcibly selected when in 842 mode data transfer. DT Duty drive mode Output pin state (COM2) 0 Static drive mode VSS level 1 1/2 duty drive mode COM2 Note: COM2…Common output 3. FC0 to FC2: Common/segment output waveform frame frequency control data These control data bits set the frame frequency of the common and segment output waveforms. However, fo=fosc/384 is forcibly selected when in 842 mode data transfer. Control data Frame frequency fo [Hz] FC0 FC1 FC2 1 1 0 fosc/768, fCK/768 1 1 1 fosc/576, fCK/576 0 0 0 fosc/384, fCK/384 0 0 1 fosc/288, fCK/288 0 1 0 fosc/192, fCK/192 www.onsemi.com 12 LC75841PE 4. OC: RC oscillator operating mode/external clock operating mode switching control data This control data bit switches the OSC pin function (either RC oscillator operating mode or external clock operating mode). However RC oscillator operating mode is forcibly selected when in 842 mode data transfer. OC OSC pin function 0 RC oscillator operating mode 1 External clock operating mode Note: An external resistor, Rosc, and an external capacitor, Cosc, must be connected to the OSC pin if RC oscillator operating mode is selected. 5. SC: Segment on/off control data This control data bit controls the on/off state of the segments. SC Display state 0 On 1 Off Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 6. BU: Normal mode/power-saving mode control data This control data bit selects either normal mode or power-saving mode. BU 0 Mode Normal mode Power-saving mode. In RC oscillator operating mode (OC = 0), the OSC pin oscillator is stopped, and in external clock operating mode 1 (OC = 1), acceptance of the external clock is stopped. In this mode the common and segment output pins go to the VSS levels. However, S1/P1 to S4/P4 output pins that are set to be general-purpose output ports by the control data P0 to P2 can be used as general-purpose output ports. www.onsemi.com 13 LC75841PE Display Data and Output Pin Correspondence (1) Static drive mode Output pin COM1 Output pin COM1 Output pin COM1 S1/P1 D1 S11 D11 S21 D21 S2/P2 D2 S12 D12 S22 D22 S3/P3 D3 S13 D13 S23 D23 S4/P4 D4 S14 D14 S24 D24 S5 D5 S15 D15 S25 D25 S6 D6 S16 D16 S26 D26 S7 D7 S17 D17 S27 D27 S8 D8 S18 D18 S9 D9 S19 D19 S10 D10 S20 D20 Notes: This applies to the case where the S1/P1 to S4/P4 output pins are set to be segment output ports. The static drive mode cannot be selected when in 842 mode data transfer. For example, the table below lists the output states for the S11 output pin. Display data Output pin (S11) state D11 0 The LCD segment corresponding to COM1 is off 1 The LCD segment corresponding to COM1 is on (2) 1/2 duty drive mode Output pin COM1 COM2 Output pin COM1 COM2 Output pin COM1 COM2 S1/P1 D1 D2 S11 D21 D22 S21 D41 D42 S2/P2 D3 D4 S12 D23 D24 S22 D43 D44 S3/P3 D5 D6 S13 D25 D26 S23 D45 D46 S4/P4 D7 D8 S14 D27 D28 S24 D47 D48 S5 D9 D10 S15 D29 D30 S25 D49 D50 S6 D11 D12 S16 D31 D32 S26 D51 D52 S7 D13 D14 S17 D33 D34 S27 D53 D54 S8 D15 D16 S18 D35 D36 S9 D17 D18 S19 D37 D38 S10 D19 D20 S20 D39 D40 Note: This applies to the case where the S1/P1 to S4/P4 output pins are set to be segment output ports. For example, the table below lists the output states for the S11 output pin. Display data Output pin (S11) state D21 D22 0 0 The LCD segments corresponding to COM1 and COM2 are off. 0 1 The LCD segment corresponding to COM2 is on. 1 0 The LCD segment corresponding to COM1 is on. 1 1 The LCD segments corresponding to COM1 and COM2 are on. www.onsemi.com 14 LC75841PE Output Waveforms (Static drive mode) fo[Hz] VDD COM1 0V VDD LCD driver output when off 0V VDD LCD driver output when on 0V Output Waveforms (1/2 duty, 1/2 bias drive mode) fo[Hz] VDD 1/2VDD COM1 0V VDD 1/2VDD COM2 0V VDD LCD driver output when all LCD segments corresponding to COM1 and COM2 are off. 0V VDD LCD driver output when only LCD segments corresponding to COM1 are on. 0V VDD LCD driver output when only LCD segments corresponding to COM2 are on. 0V VDD LCD driver output when all LCD segments corresponding to COM1 and COM2 are on. 0V Control data Frame frequency fo [Hz] FC0 FC1 FC2 1 1 0 fosc/768, fCK/768 1 1 1 fosc/576, fCK/576 0 0 0 fosc/384, fCK/384 0 0 1 fosc/288, fCK/288 0 1 0 fosc/192, fCK/192 www.onsemi.com 15 LC75841PE Display Control and the INH Pin Since the IC’s internal data (the display data D1 to D27 and the control data when in static drive mode, and the display data D1 to D54 and the control data when in 1/2 duty drive mode) is undefined when power is first applied, applications should set the INH pin low at the same time as power is applied to turn off the display (setting S1/P1 to S4/P4 and S5 to S27, COM1, and COM2 to the VSS level) and during this period send serial data from the controller. The controller should then set the INH pin high after the data transfer has completed. This procedure prevents unnecessary display at power on. (See figure 4, figure 5 and figure 6) t1  • Static drive mode  VDD INH VIL1 Internal data D1 to D27, P0 to P2, DT, FC0 to FC2, OC, SC, BU VIL1 Display data and control data transferred Undefined    tc CE Undefined Defined Notes: t1>0 tc  10s min [Figure 4] • 1/2 duty drive mode  t1  VDD INH VIL1 Internal data D1 to D28, P0 to P2, DT, FC0 to FC2, OC, SC, BU Internal data (D29 to D54) VIL1 Display data and control data transferred Undefined Defined Undefined      tc CE Undefined Defined Undefined Notes: t1>0 tc  10s min [Figure 5] • 1/2 duty drive mode (when in 842 mode data transfer)  t1  VDD INH VIL1 CE VIL1 Display data and control data transferred Internal data (D1 to D28, BU, SC) Internal data (D29 to D54) Undefined Defined Undefined      tc Defined Notes: t1>0 tc  10s min [Figure 6] www.onsemi.com 16 Undefined Undefined LC75841PE Notes on Controller Transfer of Display Data Since the LC75841PE transfer the display data (D1 to D54) in two separate transfer operations in 1/2 duty drive mode, we recommend that applications make a point of completing all of the display data transfer within a period of less than 30 ms to prevent observable degradation of display quality. OSC Pin Peripheral Circuit (1) RC oscillator operating mode (control data OC = 0) An external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and GND if RC oscillator operating mode is selected. OSC Rosc Cosc (2) External clock operating mode (control data OC = 1) When the external clock operating mode is selected, insert a current protection resistor Rg (4.7 to 47 k) between the OSC pin and external clock output pin (external oscillator). Determine the value of the resistance according to the allowable current value at the external clock output pin. Also make sure that the waveform of the external clock is not heavily distorted. External clock output pin OSC Rg External oscillator Note: Allowable current value at external clock output pin > www.onsemi.com 17 VDD Rg LC75841PE (P1) Sample Application Circuit 1 Static drive mode (P2) (P3) *3 (P4) +5.0V OSC *2 VDD General-purpose Output ports Used for functions such as backlight control COM1 VSS LCD panel (up to 27 segments) P1/S1 P2/S2 P3/S3 P4/S4 S5 INH From the controller CE S26 *4 CL S27 DI COM2 OPEN *2: In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. If external clock operating mode is selected, a current protection resistor, Rg (4.7 to 47 k), must be inserted between the external clock output pin (on the external oscillator) and the OSC pin. (See the “OSC Pin Peripheral Circuit” section.) *3: When a capacitor except the recommended external capacitance (Cosc = 1000 pF) is connected to the OSC pin, it should be in the range 220 to 2200 pF. *4: The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3 V or 5.0 V. Sample Application Circuit 2 1/2 duty drive mode (P1) (P2) (P3) *3 (P4) +5.0V OSC *2 VDD General-purpose Output ports Used for functions such as backlight control COM1 COM2 P1/S1 P2/S2 P3/S3 P4/S4 S5 INH From the controller CE CL LCD panel (up to 54 segments) VSS S25 *4 S26 DI S27 *2: In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. If external clock operating mode is selected, a current protection resistor, Rg (4.7 to 47 k), must be inserted between the external clock output pin (on the external oscillator) and the OSC pin. (See the “OSC Pin Peripheral Circuit” section.) *3: When a capacitor except the recommended external capacitance (Cosc = 1000 pF) is connected to the OSC pin, it should be in the range 220 to 2200 pF. *4: The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3 V or 5.0 V. www.onsemi.com 18 LC75841PE ORDERING INFORMATION Package Shipping (Qty / Packing) LC75841PE-H Device LQFP36 7x7 / QFP36 (Pb-Free / Halogen Free) 1250 / Tray JEDEC LC75841PES-H LQFP36 7x7 / QFP36 (Pb-Free / Halogen Free) 1250 / Tray JEDEC ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. 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