LC823433TA
Audio Processing System LSI
for MP3 Record and Playback Devices
Overview
LC823433TA is an audio processing system for MP3 record and playback
devices.
It integrates DSP for digital signal processing and analog blocks such as
audio ADC, audio DAC, and speaker and headphone amplifier in addition
to LCD segment driver.
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Features
32-bit LPDSP32
- SRAM (246 KB)
PM 75 KB (40 KB + 35 KB : ISOLATED)
DMA 170 KB (16 KB + 154 KB:ISOLATED)
TQFP128 14x14 / TQFP128L
DMB 1 KB (ISOLATED)
ISOLATED area : Power ON/OFF control is available by register.
- ROM (264.5 KB)
PM 227.5 KB (ISOLATED)
DMA 34 KB (ISOLATED)
DMB 3 KB (ISOLATED)
ISOLATED area : Power ON/OFF control is available by the register.
- SIO (Clock Serial IO 2 ch)
SIO0 : Ch0 eSIO (Clock speed = Sysclk/1 (max))
program load and execute is possible using Serial Flash
(after internal ROM Boot)
SIO1 : Ch1 SIO (Clock speed = Sysclk/8 (max))
- UART (1 ch)
- I2C (1 ch Single Master, Full/Standard)
- Plain Timer (2 ch)
Timer0 : w/ Watch Dog Timer
Timer1 : w/o Watch Dog Timer and XT1 operation
- Multiple Timer (2 ch)
PWM output (1 ch)
- RTC (Real Time Clock)
Operating voltage is independent of internal core operating voltage.
Only RTC power supply can be active during all others inactive (ISOLATED).
Continued on next page.
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
May 2017 - Rev. 2
1
Publication Order Number :
LC823433TA/D
LC823433TA
Continued from preceding page.
- SD card IF (2 ch) (w/o CPRM)
eSD/eMMC can be connected.
SD ch0 : program load and execute using eSD/eMMC (after internal ROM Boot) is possible.
SD ch1 : SD card
- USB2.0 (480M bps/12M bps) Device IF. built-in PHY
- 10 bit A/D converter (3 ch)
- GPIO (31 ch)
(GPIOs share the terminals with other functions. Refer to the terminal list in detail).
LCD controller, LCD Driver. 18SEG * 8COM, 1/8Duty, 1/4Bias
- Internal ROM Boot is possible.
- Firmware writing function.
The firmware reading from SD ch1 and writing to the following devices:
Serial Flash connected SIO0.
eMMC/eSD connected SD ch0.
- JTAG (for debugger)
Audio Functions
- Record and Playback
Compression method : MP31 (MPEG1/2/2.5 Layer3). Stereo/Mono compatible.
Sampling frequences : 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz
Bitrate : 8k bps (*1) to 320k bps (for Decoder-VBR)
(*1) Encoder supports only Mono (one channel) for 8k bps.
- Adjusting the playback speed
Fast playback : 1.0 times to 2.0 times 10 steps.
Slow playback : 0.5 times to 1.0 times 10 steps.
- Multipurpose filter
- Audio data automatic transfer function
The audio buffer executes the data transfer between internal SRAM (DMA) and the audio block.
Wait cycle(s) is inserted to the LPDSP32 access to the SRAM while the audio buffer accesses to internal
SRAM(DMA).
- Digital volume, digital mute, BEEP, and level meter
The interrupt generation function at the operation completion
(e.g. interrupt at mute completion).
- Audio timer
LR clock count and the interrupt generation function.
- Flexible PCM audio interface (two interfaces)
Master/Slave Mode Selectable
Data Formats : I2S mode etc.
- Sample Rate Converters
0.5 times to 64 times conversion range.
- Digital microphone IF (2 ch)
Continued on next page.
1
MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and Thomson.
Supply of this product does not convey license nor imply any right to distribute content created with this product in
revenue-generating broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming
applications (via Internet, intranets and/or networks), other content distribution systems (pay-audio or audio-on-demand
applications and the like) or on physical media (compact discs, digital versatile discs, semiconductor chips, hard drives,
memory cards and the like).
Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer
Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An
independent license for such use is required. For details, please visit http://mp3licensing.com/.
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2
LC823433TA
Continued from preceding page.
Analog function
- Microphone amplifier 0 / 18 / 24 / 30 dB (2 ch)
- PGA with ALC 12 dB to 35.25 dB in 0.75 dB steps (2 ch)
- 16-bit ΔΣADC (2 ch)
- Digital filter for 16-bits ΔΣDAC (2 ch)
- AB class amplifier
The power supply only to AB class amplifier is possible (ISOLATED).
Thermal shutdown circuit built-in
Speaker amplifier (1 ch BTL) 1dB to 4.5 dB in 0.5 dB steps
Maximum output 300 mW @3.0 V, Speaker = 8[], 1 dB
Headphone amplifier (2 ch) 0 dB to 3 dB in 1 dB steps (Only same gain setting to 2 ch is possible)
Maximum output 5 mW @3.0 V, HeadPhone = 16[], Rd (Series) = 33[], 1 dB
Clock
- RCOSC : Internal RC oscillation. 1 MHz (TYP)
- XT1 : Main XTAL. 32.768 kHz.
Used as an original oscillation of the system clock and the audio clock, and a RTC clock.
- XT2 : Optional XTAL. 12 MHz (TYP) etc.
- PLL1 : For system clock generation (LPDSP32 is included).
- PLL2 : For audio clock generation
Specification
Supply voltage : 1.3 V (core, etc), 3.15 V (Audio, USB, etc)
Maximum operation frequency : 42 MHz (DSP@1.3 V)
Package : 128 pin TQFP
Application
IC Recorder, Audio Player
Radio Recorder, Home Audio (Mini compo)
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LC823433TA
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter
Supply voltage
Symbol
Domain of applicability
Ratings
Unit
Input voltage
VDD1
VDDRTC
AVDDPLL1
AVDDPHY1
VDD2
VDDLCD
AVDDPLL2
AVDDADC
AVDDAADC
AVDDADAC
AVDDSPAMP
AVDDPHY2
VI
0.3 to *VDD*+0.3 (Max 3.96)
V
Operating temperature
Topr
20 to +75
C
Storage temperature
Tstg
55 to +125
C
0.3 to +1.8
V
0.3 to +3.96
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommended Operating Conditions at Ta = 20C to +75C
Parameter
Supply voltage
Symbol
Test Conditions
VDD1
typ
max
Unit
1.15
1.3
1.65
V
0.9
1.5
1.65
V
1.15
1.3
1.65
V
VDD2
2.7
3.15
3.3
V
VDDLCD
2.7
3.15
3.3
V
AVDDPLL2
2.7
3.15
3.3
V
AVDDADC
2.7
3.15
3.3
V
AVDDAADC
2.7
2.8
3.3
V
VDDRTC
AVDDPLL1
Input voltage
min
AVDDADAC
2.7
2.8
3.3
V
AVDDSPAMP
1.8
3.15
3.8
V
AVDDPHY1
1.35
1.5
1.65
V
AVDDPHY2
3.0
3.15
3.6
V
0
*VDD*
V
0
3.6
V
0
3.3
V
VIN
VIN3
(RTC)
VIN_ADC
(AN0-AN2).
I_AN 300 A
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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LC823433TA
DC Characteristics at Ta = 20C to +75C, VDD1 = 1.15 V to 1.65 V, VDD2 = 2.7 V to 3.3 V,
VDDRTC = 0.9 V to 1.65 V
Parameter
Input high voltage
Symbol
VIH
Application
Test Conditions
3IS, 3ISUD
Input low voltage
VIL
typ
Unit
V
0.75 VDD2
V
0.7 VDDRTC
0.7 VDDRTC
V
Schmitt
V
3ICUD
3IS, 3ISUD
max
Schmitt
1IC
1IS
min
0.7 VDD2
3ICUD
Schmitt
1IC
1IS
Schmitt
0.3 VDD2
V
0.25 VDD2
0.2 VDDRTC
V
0.2 VDDRTC
V
10
A
V
Input high leakage
current
IIH
3ICUD, 3IS,
3ISUD
1IC, 1IS
VIN = VDD2
Input low leakage
current
IIL
3IS, 3ISUD
VIN = VSS
1IC, 1IS
Output high voltage
VOH
3T2
VIN = VSSRTC
IOH = 2 mA
VDD20.4
V
3T4
IOH = 4 mA
VDD20.4
V
3T4(8)
VDD20.4
V
VDD20.4
V
3T2
IOH = 4 mA
(IOH = 8 mA)
IOH = 6 mA
(IOH = 12 mA)
IOL = 2 mA
3T4
IOL = 4 mA
3T4(8)
IOL = 4 mA
(IOL = 8 mA)
IOL = 6 mA
(IOL = 12 mA)
IOL = 0.3 mA
3T6(12)
Output low voltage
VOL
3T6(12)
OD3
Output leakage current
IOZ
Pull-up resistor
Rup
Pull-down resistor
Rdn
VIN = 3.3V
3T2, 3T4,
3T4(8),
3T6(12)
3ICUD,
3ISUD
3ICUD,
3ISUD
When it outputs
Hi-Z
10
A
10
A
10
A
10
0.4
V
0.4
V
0.4
V
0.4
V
0.3
V
10
A
30
80
190
kΩ
30
80
190
kΩ
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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LC823433TA
Package Dimensions
unit : mm
TQFP128 14x14 / TQFP128L
CASE 932BA
ISSUE A
GENERIC
MARKING DIAGRAM*
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
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LC823433TA
Pin Assignment (Bonding Option)
Direction
I
Input pin
O
Output pin
B
P
Attribute
3IS
3 V Schmitt input
1IS
3ICUD
3 V CMOS input pull-up/down
1IC
Bidirectional pin
3ISUD
3 V Schmitt input pull-up/down
OD3
Power supply pin
3T2
3 V 2 mA tristate output
3T4
3 V 4 mA tristate output
X
Oscillation amplifier
Tristate output with 3 V 4 mA / 8 mA
switch function
Tristate output with 3 V 6 mA / 12 mA
switch function
3A
3 V analog through
1A
1 V analog through
3T4(8)
3T6(12)
TQFP128L
Pin No.
Name
Direction
1
AVSSSPAMP
P
2
AVDDSPAMP
P
1 V Schmitt input
(3 V tolerant correspondence)
1 V CMOS input
(3 V tolerant correspondence)
1 V 0.3 mA open drain output
(3 V tolerant correspondence)
Attribute
3
AVREFSP
O
3A
4
HPINL/SPKINM
I
3A
5
HPINR
I
3A
6
AVSSADAC
P
7
OUTMR
O
3A
8
OUTML/OUTM
O
3A
9
AVDDADAC
P
10
AVSSAADC
P
11
AVREF
O
12
AVDDAADC
P
3A
13
AINL
I
3A
14
AINR
I
3A
15
AVDDADC
P
16
AN0
I
3A
17
AN1
I
3A
18
AN2
I
3A
19
VSS
P
20
VDD2
P
21
VDD1
P
22
TIOCA0/P10
B/B
3ISUD/3T2
23
BMODE0
I
3IS
24
BMODE1
I
3IS
25
BMODE2
I
3IS
26
NRES
I
3IS
27
SDCLK1/MCLK1/P00
O/B/B
3ISUD/3T6(12)
28
SDCMD1/LRCK1/P02
B/O/B
3ISUD/3T4(8)
29
SDAT10/BCK1/P03
B/B/B
3ISUD/3T4(8)
30
SDAT11/DIN1/P04
B/I/B
3ICUD/3T4(8)
31
SDAT12/DOUT1/P05
B/O/B
3ICUD/3T4(8)
32
SDAT13/SDO1/P06
B/O/B
3ICUD/3T4(8)
33
SDWP1/SDI1/P01
I/I/B
3ISUD/3T2
34
SDCD1/SCK1/P0A
I/B/B
3ISUD/3T2
35
SDCLK0/P14
O/B
3ICUD/3T6(12)
36
VDD2
P
37
VSS
P
38
SDCMD0/P15
B/B
3ICUD/3T4(8)
Continued on next page.
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LC823433TA
Continued from preceding page.
TQFP128L
Name
Pin No.
Direction
Attribute
39
SDAT03/P16
B/B
3ICUD/3T4(8)
40
SDAT02/P17/SYSCLK
B/B/O
3ICUD/3T4(8)
41
SDAT01/P18/AUD0CLK
B/B/O
3ICUD/3T4(8)
3ICUD/3T4(8)
42
SDAT00/P19/AUD1CLK
B/B/O
43
VSS
P
44
XIN2
I
X
X
45
XOUT2
O
46
AVDDPHY1(+VDD1)
P
47
AVSSPHY1
P
48
AVSSPHY1
P
49
RREF
B
50
AVSSPHY2
P
51
AVDDPHY2
P
52
AVDDPHY2
P
53
AVSSPHY2
P
54
AVSSPHY2
P
55
AVSSPHY2
P
56
AVDDPHY2
P
57
DP
B
3A
3A
3A
58
DM
B
59
AVSSPHY2
P
60
AVDDPHY2
P
61
COM0
O
3A
62
COM1
O
3A
63
COM2
O
3A
3A
64
COM3
O
65
VDDLCD
P
66
VLCD1
O
3A
67
VLCD2
O
3A
68
VLCD3
O
3A
69
VSS
P
70
VDD1
P
71
SEG0
O
3A
72
SEG1
O
3A
73
SEG2
O
3A
74
SEG3
O
3A
75
SEG4
O
3A
76
SEG5
O
3A
77
SEG6
O
3A
78
SEG7
O
3A
79
SEG8
O
3A
80
SEG9
O
3A
81
SEG10
O
3A
82
SEG11
O
3A
83
SEG12
O
3A
84
SEG13
O
3A
85
SEG14
O
3A
86
SEG15
O
3A
87
SEG16
O
3A
88
SEG17
O
3A
89
COM4
O
3A
90
COM5
O
3A
Continued on next page.
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LC823433TA
Continued from preceding page.
TQFP128L
Name
Pin No.
Direction
Attribute
91
COM6
O
92
COM7
O
3A
93
HPDET/SDI1/SCL/P1A
I/I/O/B
3ISUD/3T2
94
HPMUTE/SDO1/SDA/P1B
O/O/B/B
3ISUD/3T2
95
JTDO/P1C
O/B
3ICUD/3T2
96
JTDI/P1D
I/B
3ICUD/3T2
97
JTMS/P1E
I/B
3ICUD/3T2
98
JTCK/P1F
I/B
3ICUD/3T2
99
VDD1
P
100
VDD2
P
SFMODE
(Internal Signal)
I
101
3A
3IS
102
VSS
TXD/SCL/P12
O/O/B
P
3ISUD/3T2
103
RXD/SDA/P13
I/B/B
3ISUD/3T2
104
SCK0/P07
B/B
3ISUD/3T4
105
SDO0/P08
O/B
3ISUD/3T4
106
SDI0/P09
I/B
3ISUD/3T2
107
MCLK0/DMCKO/SCK1/P0B
B/O/B/B
3ISUD/3T2
108
DIN0/DMDIN/P0F
I/I/B
3ISUD/3T2
109
DOUT0/P0E/NCS
O/B/O
3ISUD/3T2
110
KEYINT1
I
1IS
111
KEYINT0
I
1IS
112
RTCRSTB
I
1IC
113
PWRON
O
OD3
114
LINEFIXB
I
1IS
115
XOUT32K
O
X
X
116
XIN32K
I
117
VDDRTC
P
RTCMODE
(Internal Signal)
I
118
VSSRTC
P
119
AVDDPLL1
P
120
VCNT1
O
121
VSS
P
122
AVDDPLL2
P
123
VCNT2
O
124
AVSSPLL2
P
125
HPOUTR
O
3A
126
HPOUTL
O
3A
127
SPOUTP
O
3A
128
SPOUTN
O
3A
1IS
1A
3A
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LC823433TA
Block Diagram
JTAG
RCOSC
OSCCON System Clock
(System)
XT1
PLL1
Peripheral1 Clock
Peripheral2 Clock
System Clock
DMA
DMB
OSCCON FUNCCLK0
(FUNC) FUNCCLK1
XT1
XT2
System Clock
XT2
PLL2
BCK0, BCK1
Audio Clock1
DMIO
32
DMB
OSCCON Audio Clock0
(Audio)
XT1
64
PDM
DMA ISOLATED
Dig
MIC
SRAM
(154KB)
+
(16KB)
PGA(ALC)
MIC
0/18/24/30dB
-12 to 35.25dB
0/18/24/30dB
Plain
Timer0
64
-12 to 35.25dB
Plain
Timer1
FUNCCLK1
MUX
DF + ALC
P/S
Audio Buffer
16bit D/A
(2ch/BTL)
PWM
“Lch” or “+”
“Rch”
LPF
AVDDADAC
ISOLATED
“+”
“-”
AUDIO functions
(SRC, VOLUME, etc)
LPF
Speaker
ISOLATED
ISOLATED
16bit
A/D
PCM0 OUT
ROM
(227.5KB)
PGA(ALC)
MIC AMP
AVDDAADC
SRAM
(35KB)
+
(40KB)
ROM
(34KB)
16bit
A/D
MIC
PM ISOLATED
S/P
MIC AMP
40
ISOLATED
Arbiter
Digital MIC IF
PRG
SRAM
(1KB)
ROM
(3KB)
MCLK0, MCLK1
PCM0 IN
32
IRQ 15ch
(Write To,
Read From
DMA)
Multiple
Timer
1
eSIO
(SIO0)
SIO S-Flash Boot
Ch0
etc
UART
“Lch”
0 to 3dB(Lch, Rch common)
PCM1 OUT
10bit
A/D
Peripheral2
“Rch”
AVDDSPAMP
VDDRTC
Peripheral0
VDD1
VDD2
AVDDADC
VDDLCD
AVDDPLL1
AVDDPLL2
Logic
I/O
10bit A/D
LCDCTL
PLL1
PLL2
18seg × 8com or
36seg × 4com(TBD)
LCD
eMMC/eSD Boot
Ch0
eSD
eMMC
Ch1
SD I/F
Firmware DL
etc
USB2.0
HS
Device
ISOLATED
3
LCD
CTL
FUNCCLK1
S/P
Boot monitor
etc
GPIO
P/S
PCM1 IN
USB2.0
PHY
XT2
or
XT2/2
RTC
LCD
I2C
1 to 4.5dB
HeadPhone
PWM
SIO
Ch1
eSIO
(SIO1)
Peripheral1
XT2
ON Semiconductor
Sanyo
32bit32bit
DSP DSP
LPDSP32
LPDSP32
Peripheral0 Clock
XT2
AVDDPHY2
AVDDPHY1
XT1
32.768kHz
Note
- Refer to the pin assignment for port share
- ISOLATED SRAMs and ROMs described in this figure can be power off by a register,
in addition to the tiny SRAMs (not described in this figure) in the SD I/F, USB2.0, SRC, 16bit D/A, DF.
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LC823433TA
Pin Functions
JTAG
Pin name
Pol.
Type
Description
JTDO/
P1C
JTDI/
P1D
-/
-/
-
O/
B
I/
B
JTAG test data output/
General purpose port
JTAG test data input/
General purpose port.
The input level of the terminal JTDI is taken by rising edge of the
terminal NRES.
The value can be read as a register, and can be used as the
operation mode setting.
JTAG test mode selection/
General purpose port
The input level of the terminal JTMS is taken by rising edge of the
terminal NRES.
The value can be read as a register, and can be used as the
operation mode setting.
JTAG test clock/
General purpose port
JTMS/
P1E
-/
-
JTCK/
P1F
Pos/
-
I/
B
I/
B
Num.
1
1
1
1
Total
4
RTC
Pin name
Pol.
Type
Description
XIN32K
Pos
I
32.768 kHz oscillation amplifier input (XT1)
Num.
1
XOUT32K
-
O
32.768 kHz oscillation amplifier output (XT1)
1
RTCRSTB
Neg
I
RTC reset input
(VDET)
Neg
I
PWRON
-
O
There is an optional bonding as Power supply watch comparison
input.
Main power supply ON/OFF control
(RTCINT)
LINEFIXB
Neg
Neg
O
I
There is an optional bonding as RTC interrupt output.
RTC isolator cutting and the connection
(BACKUPB)
VDDRTC
Neg
-
I
P
There is an optional bonding as RTC operation mode selection.
RTC block power supply.
1
VSSRTC
-
P
RTC ground pin.
1
1
1
1
Total
7
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LC823433TA
SIO (synchronous serial) interface Ch0 (eSIO)/Timer PWM output/General purpose port
Pin name
Pol.
Type
Description
Num.
SCK0/
Pos/
B/
Serial I/F Ch0 clock/
P07
-
B
General purpose port
1
(It is possible to use it as an external interrupt input.)
SDO0/
-/
O/
Serial I/F Ch0 data output/
P08
-
B
General purpose port
(It is possible to use it as an external interrupt input).
1
There is an optional bonding as serial I/F Ch0 data output
(SDO0(SIO0))
-(-)
O(B)
SDI0/
-/
I/
Serial I/F Ch0 data input/
P09
-
B
General purpose port
(Data I/O 0 when at high speed operating).
(It is possible to use it as an external interrupt input).
(SDI0(SIO3))
-(-)
I(B)
There is an optional bonding as serial I/F Ch0 data input
TIOCA0/
-/
B/
MTM Ch0 A input capture and output capture/
P10
-
B
General purpose port
-
P
There is an optional bonding as VSS.
1
(Data I/O 3 when at high speed operating).
(VSS)
1
Total
4
UART (asynchronization serial) interface/I2C interface/General purpose port
Pin name
Pol.
Type
Description
Num.
TXD/
SCL/
P12
-/
-/
-
O/
O/
B
RXD/
SDA/
P13
-/
-/
-
I/
B/
B
UART transmitted serial data output/
2
I C clock output (open drain output)/
General purpose port
(It is possible to use it as an external interrupt input).
UART received serial data input/
2
I C data (open drain output)/
General purpose port
(It is possible to use it as an external interrupt input).
1
1
Total
2
Headphone control/SIO (synchronous serial) interface Ch1 (SDI, SDO)/I2C interface/General purpose port
Pin name
Pol.
Type
Description
HPDET/
SDI1/
SCL/
P1A
Pos/
-/
-/
-
I/
I/
O/
B
HPMUTE/
SDO1/
SDA/
P1B
Pos/
-/
-/
-
O/
O/
B/
B
Headphone insertion detection/
Serial I/F Ch1 data input/
2
I C clock output (open drain output)/
General purpose port
(It is possible to use it as an external interrupt input).
Headphone mute/
Serial I/F Ch1 data output/
2
I C data (open drain output)/
General purpose port
Num.
Total
1
1
2
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12
LC823433TA
PCM interface Ch0/Digital mic interface/
SIO (synchronous serial) interface Ch1 (SCK)/General purpose port/RTC (KeyInt RTC model)
Pin name
Pol.
Type
Description
MCLK0/
DMCKO/
SCK1/
P0B
Pos/
-/
-/
-
B/
O/
B/
B
KEYINT1
-
I
PCM Ch0 master clock/
Digital mic clock output/
Serial I/F Ch1 clock/
General purpose port
(It is possible to use it as an external interrupt input).
KEY interrupt1
(Notes: Operate in VDDRTC and the VSSRTC power supply).
(NHOLD(SIO1))
-
O(B)
There is an optional bonding as serial I/F Ch0 hold output
(Data I/O 1 when at high speed operating).
(BCK0/
P0C)
KEYINT0
-/
-
B/
B
I
There is an optional bonding as PCM Ch0 bit clock/
General purpose port
KEY interrupt0
(Notes: Operate in VDDRTC and the VSSRTC power supply).
O(B)
There is an optional bonding as serial I/F Ch0 write protect output
(Data I/O 2 when high speed operating).
(NWP(SIO2))
(LRCK0/
P0D)
B/
B
DIN0/
DMDIN/
P0F
-/
-/
-/
-
DOUT0/
P0E/
-/
-/
O/
B/
NCS
Neg
O
Neg
O
(NCS)
I/
I/
B
Num.
There is an optional bonding as PCM Ch0 LR clock/
General purpose port
(It is possible to use it as an external interrupt input).
PCM Ch0 data input/
Digital mic data input/
General purpose port
(It is possible to use it as an external interrupt input).
PCM Ch0 data output/
General purpose port
(It is possible to use it as an external interrupt input)/
CS for serial I/F Ch0 (When it boots from internal ROM and the
program from SerialFlash connected to serial I/F Ch0 is loaded, it
is used as CS control terminal of SerialFlash).
1
1
1
1
1
There is an optional bonding as CS for serial I/F Ch0.
Total
5
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13
LC823433TA
SD interface Ch0/General purpose port
Pin name
Pol.
Type
Description
Num.
SDCLK0/
P14
SDCMD0/
P15
SDAT03/
P16
SDAT02/
P17/
SYSCLK
SDAT01/
P18/
AUD0CLK
SDAT00/
P19/
AUD1CLK
Pos/
-/
-/
-/
-/
-/
-/
-/
-/
-
O/
B
B/
B
B/
B
B/
B/
O
B/
B/
O
B/
B/
O
SD card I/F Ch0 clock output/
General purpose port
SD card I/F Ch0 command line/
General purpose port
SD card I/F Ch0 data 3/
General purpose port
SD card I/F Ch0 data 2/
General purpose port/
System Clock output (for evaluation)
SD card I/F Ch0 data 1/
General purpose port/
Audio0 Clock output (for evaluation)
SD card I/F Ch0 data 0/
General purpose port/
Audio1 Clock output (for evaluation)
1
1
1
1
1
1
Total
6
SD interface Ch1/PCM interface Ch1/SIO (synchronous serial) interface Ch1/General purpose port
Pin name
Pol.
Type
Description
SDCLK1/
MCLK1/
P00
SDCMD1/
LRCK1/
P02
SDAT13/
SDO1/
P06
SDAT12/
DOUT1/
P05
SDAT11/
DIN1/
P04
SDAT10/
BCK1/
P03
SDWP1/
SDI1/
P01
Pos/
Pos/
-/
-/
-/
-/
-/
-/
-/
-/
-/
-/
-/
-/
-
O/
O/
B
B/
B/
B
B/
O/
B
B/
O/
B
B/
I/
B
B/
B/
B
I/
I/
B
SDCD1/
SCK1/
P0A
-/
-/
-
I/
B/
B
SD card I/F Ch1 clock output/
PCM Ch1 master clock/
General purpose port
SD card I/F Ch1 command line/
PCM Ch1 LR clock/
General purpose port
SD card I/F Ch1 data 3/
Serial I/F Ch1 data output/
General purpose port
SD card I/F Ch1 data 2/
PCM Ch1 data output/
General purpose port
SD card I/F Ch1 data 1/
PCM Ch1 data input/
General purpose port
SD card I/F Ch1 data 0/
PCM Ch1 bit clock/
General purpose port
SD card I/F Ch1 write protect/
Serial I/F Ch1 data input/
General purpose port
(It is possible to use it as an external interrupt input).
SD card I/F Ch1 card detect/
Serial I/F Ch1 clock/
General purpose port
(It is possible to use it as an external interrupt input).
Num.
Total
1
1
1
1
1
1
1
1
8
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14
LC823433TA
Oscillation amplifier and PLL
Pin name
Pol.
Type
Description
Num.
XIN2
Pos
I
Oscillation amplifier input for audio (XT2)
1
XOUT2
-
O
Oscillation amplifier output for audio (XT2)
1
VCNT1
-
O
VCO control for PLL1
1
AVDDPLL1
-
P
Analog power supply for PLL1
1
AVSSPLL1
-
P
Analog ground for PLL1
1
VCNT2
-
O
VCO control for PLL2
1
AVDDPLL2
-
P
Analog power supply for PLL2
1
AVSSPLL2
-
P
Analog ground for PLL2
1
Total
8
10-bit A/D
Pin name
Pol.
Type
Description
AN[2:0]
-
I
ADC input
Num.
3
AVDDADC
-
P
Power supply for ADC
1
VSS
-
P
Ground for ADC. It connects VSS in LSI (terminal sharing).
1
There is an optional bonding as dedicated ground AVSSADC .
(AVSSADC)
Total
5
Audio CODEC
Pin name
Pol.
Type
Description
Num.
AINL
-
I
AINR
-
I
Analog voice input Lch (stereo)
Analog voice input (monaural).
Analog voice input Rch (stereo)
AVREF
-
O
Audio ADC reference output
1
AVDDAADC
-
P
Power supply for audio ADC
1
AVSSAADC
-
P
Ground for audio ADC
1
OUTML/
OUTM
OUTMR
-/
-
O/
O
O
Audio DAC PWM output (Lch for HP)/
Audio DAC PWM output (monaural for speaker)
Audio DAC PWM output (Rch for HP)
AVDDADAC
-
P
Power supply for audio DAC
1
AVSSADAC
-
P
Ground for audio DAC
1
HPINL/
SPKINM
HPINR
-
I/
I
I
Headphone amplifier input (Lch) /
Speaker amplifier input (monaural)
Headphone amplifier input (Rch)
SPOUTP
-
O
AB class speaker amplifier output (+)
1
SPOUTN
-
O
AB class speaker amplifier output ()
1
HPOUTL
-
O
Headphone amplifier output (Lch)
1
HPOUTR
-
O
Headphone amplifier output (Rch)
1
AVREFSP
-
O
AB class amplifier reference output
1
AVDDSPAMP
-
P
Analog power supply for AB class amplifier
1
AVSSSPAMP
-
P
Analog ground for AB class amplifier
1
Total
1
1
1
1
1
1
18
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15
LC823433TA
LCD Driver (4COM/8COM bonding switch)
Pin name
Pol.
Type
Description
Num.
SEG[17:0]
-
O
Segment output for LCD
COM[7:4]
-
O
COM [7:4], Common driver output for LCD
(when 8COM is used).
(SEG[21:18])
-
O
COM[3:0]
-
O
VLCD1
-
O
There is an optional bonding as segment outputs, SEG[21:18],
for the LCD(when 4COM is used).
Common driver output for LCD.
•Both 8COM and 4COM ··· COM[3:0].
LCD drive voltage output 1
•When 1/3 bias is used ··· 2 * VDDLCD /3.
•When 1/4 bias is used ··· 3 * VDDLCD /4.
LCD drive voltage output 2
•When 1/3 bias is used ··· 1 * VDDLCD /3.
•When 1/4 bias is used ··· 2 * VDDLCD /4.
LCD drive voltage output 3
•When 1/3 bias is used ··· 1 * VDDLCD /3.
•When 1/4 bias is used ··· 1 * VDDLCD /4.
3 V power supply for LCD driver
18
4
VLCD2
-
VLCD3
-
VDDLCD
-
O
O
P
Total
4
1
1
1
1
30
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16
LC823433TA
USB 2.0 HS Device/LCD Driver (bonding switch when 4COM is used)
Pin name
Pol.
Type
Description
Num.
DP
-
B
USB D+ (Device)
(SEG32)
DM
-
O
B
There is an optional bonding as segment output 32 for LCD.
USB D (Device)
(SEG33)
RREF
-
O
B
There is an optional bonding as segment output 33 for LCD.
Reference resistance for USB PHY.
(SEG24)
AVDDPHY1
-
O
P
AVSSPHY1
-
P
There is an optional bonding as segment output 24 for LCD.
Analog 1.5 V power supply for USB PHY.
It connects VDD1 in LSI (terminal sharing).
Analog ground for USB PHY.
(SEG22)
AVSSPHY1
-
O
P
There is an optional bonding as segment output 22 for LCD.
Analog ground for USB PHY.
(SEG23)
AVDDPHY2
-
O
P
There is an optional bonding as segment output 23 for LCD.
Analog 3.3 V power supply for USB PHY.
(SEG26)
AVDDPHY2
-
O
P
There is an optional bonding as segment output 26 for LCD.
Analog 3.3 V power supply for USB PHY.
(SEG27)
AVDDPHY2
-
O
P
There is an optional bonding as segment output 27 for LCD.
Analog 3.3 V power supply for USB PHY.
(SEG31)
AVDDPHY2
-
O
P
There is an optional bonding as segment output 31 for LCD.
Analog 3.3 V power supply for USB PHY.
(SEG35)
AVSSPHY2
-
O
P
There is an optional bonding as segment output 35 for LCD.
Analog ground for USB PHY.
(SEG25)
AVSSPHY2
-
O
P
There is an optional bonding as segment output 25 for LCD.
Analog ground for USB PHY.
(SEG28)
AVSSPHY2
-
O
P
There is an optional bonding as segment output 28 for LCD.
Analog ground for USB PHY.
(SEG29)
AVSSPHY2
-
O
P
There is an optional bonding as segment output 29 for LCD.
Analog ground for USB PHY.
(SEG30)
AVSSPHY2
-
O
P
There is an optional bonding as segment output 30 for LCD.
Analog ground for USB PHY.
(SEG34)
-
O
There is an optional bonding as segment output 34 for LCD.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Total
15
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17
LC823433TA
Power supply etc.
Pin name
Pol.
Type
Description
BMODE[2:0]
-
I
Operation mode selection
NRES
Neg
I
External reset and GPIO•LCD driver output force input
•When it is active (L input), the state of the GPIO•LCD driver is
forced, and LED lighting and the LCD display is controlled until
reset depends on LSI.
When Low is input : GPIO = Hiz, LCD = Low Fixed (PIOFIXB).
•The state of JTDI and JTMS of JTAG is taken into the internal
register by rising edge of NRES
(for operation mode setting).
Digital internal power supply
There is one VDD1 which is also connected with AVDDPHY1.
Digital IO power supply
VDD1
-
P
VDD2
-
P
VSS
-
P
Num.
Digital ground
There is one VSS which is also connected with AVSSADC.
3
1
3
3
4
Total
14
Total
128
Notes : Do not open an unused digital input terminal or a digital bidirectional terminal of input state, and set
Pull-up/Pull-down register in ON (only terminals with this function) or connect to digital IO power supply or
digital ground.
Left open AINL, AINR, HPINL/SPKINM, and HPINR terminals if they are not used (do not fix to L or H).
Operational mode
Various boot modes etc. can be selected by switching BMODE[2:0] terminal.
BMODE2
BMODE1
BMODE0
0
0
0
Internal ROM boot (eMMC Physical Boot - SD interface Ch0)
Operational mode
0
0
1
Internal ROM boot (IPL Boot - SD interface Ch0)
0
1
0
Internal ROM boot (Partition Boot - SD interface Ch0)
0
1
1
1
0
0
1
0
1
1
1
0
Internal ROM boot
(External Serial Flash Boot - SIO (synchronous serial) interface Ch0)
Liberation of the terminal for SD interface Ch0 and SIO Ch0
(SDCLK0, SDCMD0, SDAT03, SDAT02, SDAT01, SDAT00, SCK0, SDO0,
SDI0, and DOUT0 (NCS) are output Hiz).
Internal ROM boot (Deletion Partition area and IPL user area –
SD interface Ch0 and SIO external Serial Flash Ch0)
LSI test mode (Do not set to this mode when working actually).
1
1
1
LSI test mode (Do not set to this mode when working actually).
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18
LC823433TA
Pin Type
EN
EN3
A
PAD
CTU
Y
3ICUD/
3T2
CTD
EN3 = 0: PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal
EN
EN3
A
PAD
CTU
3ISUD/
3T2
Y
3ISUD/
3T4
CTD
EN3 = 0: PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal
EN3
EN
CTI
CTU
3ICUD/
3T4(8)
PAD
A
Y
3ICUD/
3T6(12)
CTD
CTI current ability switch terminal 0: 4 mA 1: 8 mA / 0: 6 mA 1: 12 mA
EN3 = 0:PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal
EN3
3ISUD/
3T4(8)
3ISUD/
3T6(12)
EN
A
PAD
CTI
CTU
Y
CTD
CTI current ability switch terminal 0: 4 mA 1: 8 mA / 0: 6 mA 1: 12 mA
EN3 = 0: PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal
Continued on next page.
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19
LC823433TA
Continued from preceding page.
1IC
1IS
PAD
Y
PAD
Y
3IS
PAD
OD3
EN
ORDERING INFORMATION
Device
LC823433TA-2H
Package
Shipping (Qty / Packing)
TQFP128 14x14 / TQFP128L
(Pb-Free / Halogen Free)
450 / Tray JEDEC
2
* I C Bus is a trademark of Philips Corporation.
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