Ordering
Orderingnumber
number: :ENA0970B
ENA1951
LC87F2H08A
CMOS IC
8K-byte FROM and 256-byte RAM integrated
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F2H08A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM (On-boardprogrammable), 256-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit
timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two 8-bit timers with
a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface,
an asynchronous/synchronous SIO interface, a UART interface (full duplex), two 12-bit PWM channels, a 12/8-bit
9-channel AD converter, a system clock frequency divider, an internal reset and a 20-source 10-vector interrupt
feature.
Features
Flash ROM
• Capable of on-board programming with a wide range (2.2 to 5.5V) of voltage source.
• Block-erasable in 128 byte units
• Writable in 2-byte units
• 8192 × 8 bits
RAM
• 256 × 9 bits
Minimum Bus Cycle
• 83.3ns (12MHz at VDD=2.7V to 5.5V)
• 100ns (10MHz at VDD=2.2V to 5.5V)
• 250ns (4MHz at VDD=1.8V to 5.5V)
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.01
61808HKIM 20080603-S00001 No.A0970-1/27
LC87F2H08A
Minimum Instruction Cycle Time
• 250ns (12MHz at VDD=2.7V to 5.5V)
• 300ns (10MHz at VDD=2.2V to 5.5V)
• 750ns (4MHz at VDD=1.8V to 5.5V)
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 16 (Pin, P20, P21, P30, P31, P70 to P73)
Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
• Dedicated oscillator ports/input ports
2 (CF1/XT1, CF2/XT2)
• Reset pin
1 (RES)
• Power pins
3 (VSS1, VSS2, VDD1)
Timers
• Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM)
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts are programmable in 5 different time schemes
High-Speed Clock Counter
• Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
• Can generate output real time.
SIO
• SIO0: 8-bit Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
UART
• Full Duplex
• 7/8/9 bit data bits selectable
• 1 Stop bit (2 bits in continuous data transmission)
• Built-in baudrate generator
AD Converter: 12 bits/8 bits × 9 channels
• 12/8 bits AD converter resolution selectable
No.A0970-2/27
LC87F2H08A
PWM: Multifrequency 12-bit PWM × 2 channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC/32 tCYC/128 tCYC)
Clock Output Function
• Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as
the system clock.
• Can generate the source clock for the subclock
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Interrupts
• 20 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/T6/T7/PWM4, PWM5
10
0004BH
H or L
Port 0
INT0
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 128levels (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation Circuits
• Internal oscillation circuits
Low-speed RC oscillation circuit :
For system clock (100kHz)
Medium-speed RC oscillation circuit : For system clock (1MHz)
Multifrequency RC oscillation circuit : For system clock (8MHz)
• External oscillation circuits
Hi-speed CF oscillation circuit:
For system clock, with internal Rf
Low speed crystal oscillation circuit:
For low-speed system clock, with internal Rf
1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control.
2) Both the CF and crystal oscillator circuits stop operation on a system reset. When the reset is released, only the
CF oscillation circuit resumes operation.
No.A0970-3/27
LC87F2H08A
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and
76.8μs (at a main clock rate of 10MHz).
Internal reset function
• Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and
4.35V) through option configuration.
• Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,
2.81V, 3.79V, 4.28V).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) System resetting by watchdog timer or low-voltage detection
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4 or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillator automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer or low-voltage detection.
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4 or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
(5) Having an interrupt source established in the base timer circuit.
Note: Available only when X’tal oscillation is selected.
Onchip Debugger
• Supports software debugging with the IC mounted on the target board.
• Two channels of on-chip debugger pins are available to be compatible with small pin count devices.
DBGP0 (P0), DBGP1 (P1)
Data Security Function (flash versions only)
• Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
Package Form
• QFP36 (7×7): Lead-free type
Development Tools
• On-chip debugger: TCB87 type B + LC87F2H08A
No.A0970-4/27
LC87F2H08A
Programming Boards
Package
Programming boards
QFP36(7×7)
W87F24Q
Flash ROM Programmer
Maker
Model
Single
Programmer
Flash Support Group, Inc.
Gang
Device
AF9709/AF9709B/AF9709C
Rev 02.72 or later
LC87F2H08A
-
-
-
-
(Note 2)
LC87F2H08A
(Including Ando Electric Co., Ltd. models)
AF9723/AF9723B(Main body)
(FSG)
Supported version
AF9708
(Including Ando Electric Co., Ltd. models)
Programmer
AF9833(Unit)
(Including Ando Electric Co., Ltd. models)
Flash Support Group, Inc.
AF9101/AF9103(Main body)
(FSG)
(FSG models)
In-circuit
+
Programmer
Our company
SIB87(Inter Face Driver)
(Our company model)
(Note 1)
Our company
Single/Gang
SKK/SKK Type B
Programmer
(SANYO FWS)
1.04 or later
In-circuit/Gang
SKK-DBG Type B
Chip Data Version
Programmer
(SANYO FWS)
2.10 or later
Application Version
LC87F2H08A
For information about AF-Series:
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: sales@j-fsg.co.jp
Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company (SIB87)
together
can give a PC-less, standalone on-board-programming capabilities.
Note2: It needs a special programming devices and applications depending on the use of programming environment.
Please ask FSG or Our company for the information.
Package Dimensions
unit : mm (typ)
3162C
27
0.5
9.0
7.0
19
28
7.0
9.0
18
36
10
1
9
0.65
0.3
0.15
(1.5)
0.1
1.7max
(0.9)
SANYO : QFP36(7X7)
No.A0970-5/27
LC87F2H08A
27
26
25
24
23
22
21
20
19
P03/AN3
P02/AN2
P01/AN1
P00/AN0
VSS2
N.C.
P31/PWM5/INT5/T1IN
P30/PWM4/INT5/T1IN
P21/URX/INT4/T1IN
Pin Assignment
28
29
30
31
32
33
34
35
36
LC87F2H08A
18
17
16
15
14
13
12
11
10
P20/UTX/INT4/T1IN
P17/T1PWMH/BUZ
P16/T1PWML
N.C.
N.C.
P15/SCK1/DGBP10
P14/SI1/SB1/DBGP11
P13/SO1/DBGP12
P12/SCK0
P73/INT3/T0IN
RES
I.C.
VSS1
CF1/XT1
CF2/XT2
VDD1
P10/SO0
P11/SI0/SB0
1
2
3
4
5
6
7
8
9
P04/AN4
P05/AN5/CKO/DBGP00
P06/AN6/T6O/DBGP01
P07/T7O/DBGP02
N.C.
N.C.
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
Top view
QFP36 (7×7) “Lead-free Type”
QFP36
NAME
QFP36
NAME
1
P73/INT3/T0IN
19
P21/URX/INT4/T1IN
2
RES
20
P30/PWM4/INT5/T1IN
3
I.C.
21
P31/PWM5/INT5/T1IN
4
VSS1
22
N.C.
5
CF1/XT1
23
VSS2
6
CF2/XT2
24
P00/AN0
7
VDD1
25
P01/AN1
8
P10/SO0
26
P02/AN2
9
P11/SI0/SB0
27
P03/AN3
10
P12/SCK0
28
P04/AN4
11
P13/SO1/DBGP12
29
P05/AN5/CKO/DBGP00
12
P14/SI1/SB1/DBGP11
30
P06/AN6/T6O/DBGP01
13
P15/SCK1/DBGP10
31
P07/T7O/DBGP02
14
N.C.
32
N.C.
15
N.C.
33
N.C.
16
P16/T1PWML
34
P70/INT0/T0LCP/AN8
17
P17/T1PWMH/BUZ
35
P71/INT1/T0HCP/AN9
18
P20/UTX/INT4/T1IN
36
P72/INT2/T0IN
Note I.C. and N.C. pins must be held open (disconnected).
No.A0970-6/27
LC87F2H08A
System Block Diagram
Interrupt control
IR
PLA
Flash ROM
Standby control
SRC
RC
Clock
generator
CF/
X'tal
PC
MRC
ACC
WDT
Reset circuit
(LVD/POR)
SIO0
Reset control
RES
B register
C register
Bus interface
SIO1
Port 0
Timer 0
Port 1
Timer 1
Port 2
Timer 6
Port 3
Timer 7
Port 7
Base timer
ADC
PWM4
INT0 to 2 INT3
(Noise filter)
PWM5
Port 2 INT4
UART1
Port 3 INT5
ALU
PSW
RAR
RAM
Stack pointer
On-chip debugger
No.A0970-7/27
LC87F2H08A
Pin Description
Pin Name
I/O
Description
Option
VSS1,VSS2
-
- power supply pins
No
VDD1
-
+ power supply pin
No
Port 0
I/O
• 8-bit I/O port
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
• Pin functions
Yes
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
P00(AN0) to P06(AN6):AD converter input
P05(DBGP00) to P07(DBGP02):On-chip debugger 0 port
Port 1
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P14: SIO1 data input/bus I/O
P11: SIO0 data input/bus I/O
P15: SIO1 clock I/O
Yes
P12: SIO0 clock I/O
P16: Timer 1 PWML output
P13: SIO1 data output
P17: Timer 1 PWMH output/beeper output
P15(DBGP10) to P13(DBGP12):On-chip debugger 1 port
Port 2
I/O
• 2-bit I/O port
• I/O specifiable in 1-bit units
P20 to P21
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20: UART transmit
P21: UART receive
P20 to P21: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
Yes
timer 0H capture input
Interrupt acknowledge types
INT4
Port 3
P30 to P31
I/O
Rising
Falling
enable
enable
Rising &
Falling
enable
H level
L level
disable
disable
• 2-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P30: PWM4 output
P31: PWM5 output
P30 to P31: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
Yes
timer 0H capture input
Interrupt acknowledge types
INT5
Rising
Falling
enable
enable
Rising &
Falling
enable
H level
L level
disable
disable
Continued on next page.
No.A0970-8/27
LC87F2H08A
Continued from preceding page.
Pin Name
Port 7
I/O
Description
Option
• 4-bit I/O port
I/O
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input
P73: INT3 input (input with noise filter)/timer 0 event input/timer 0H capture input
P70(AN8),P71(AN9) : AD converter input
No
Interrupt acknowledge types
RES
CF1/XT1
I/O
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising &
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
External reset Input/internal reset output
No
• Ceramic resonator or 32.768kHz crystal oscillator input pin
I
• Pin function
No
General-purpose input port
CF2/XT2
• Ceramic resonator or 32.768kHz crystal oscillator output pin
I/O
• Pin function
No
General-purpose input port
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
P00 to P07
Option selected in
units of
1 bit
Option type
Output type
Pull-up resistor
1
CMOS
Programmable (Note 1)
2
Nch-open drain
No
CMOS
Programmable
Programmable
P10 to P17
1 bit
1
2
Nch-open drain
P20 to P21
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
P30 to P31
1 bit
P70
-
No
Nch-open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching
between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or P04 to
07).
Note: Be sure to electrically short-circuit between the VSS1 and VSS2 pins.
No.A0970-9/27
LC87F2H08A
User Option Table
Option Name
Port output type
Option to be Applied on
Flash-ROM Version
Option Selected in Units of
P00 to P07
1 bit
CMOS
Option Selection
P10 to P17
1 bit
CMOS
P20 to P21
1 bit
CMOS
Nch-open drain
Nch-open drain
Nch-open drain
P30 to P31
1 bit
CMOS
-
-
00000h
Detect function
-
Nch-open drain
Program start
address
01E00h
Low-voltage
Enable:Use
detection reset
function
Power-on reset
Disable:Not Used
Detect level
-
7-level
Power-On reset level
-
8-level
function
Recommended Unused Pin Connections
Recommended Unused Pin Connections
Port Name
Board
Software
P00 to P07
Open
Output low
P10 to P17
Open
Output low
P20 to P21
Open
Output low
P30 to P31
Open
Output low
P70 to P73
Open
Output low
CF1/XT1
Pulled low with a 100kΩ resistor or less
General-purpose input port
CF2/XT2
Pulled low with a 100kΩ resistor or less
General-purpose input port
On-chip Debugger pin connection requirements
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87
on-chip debugger installation manual" and "LC872000 series on-chip debugger pin connection requirements"
Note: Be sure to electrically short-circuit between the VSS1 and VSS2 pins.
No.A0970-10/27
LC87F2H08A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 =0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Maximum supply
VDD max
VDD1
Input voltage
VI
CF1, CF2
Input/output
VIO
Ports 0, 1, 2, 3
voltage
voltage
Peak output
Port 7
IOPH(1)
Ports 0, 1, 2, 3
High level output current
current
Mean output
CMOS output select
Per 1 applicable pin
IOPH(2)
P71 to P73
Per 1 applicable pin
IOMH(1)
Ports 0, 1, 2, 3
CMOS output select
current
Per 1 applicable pin
typ
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
-7.5
Per 1 applicable pin
Total output
ΣIOAH(1)
P71 to P73
Total of all applicable pins
-10
current
ΣIOAH(2)
P10 to P14
Total of all applicable pins
-20
P15 to P17
Total of all applicable pins
Peak output
Ports 0, 1, 2, 3
Total of all applicable pins
IOPL(1)
P02 to P07
Per 1 applicable pin
current
Mean output
(Note 1-1)
-3
-20
-25
20
Ports 1, 2, 3
IOPL(2)
P00, P01
Per 1 applicable pin
30
IOPL(3)
Port 7
Per 1 applicable pin
10
IOML(1)
P02 to P07
Per 1 applicable pin
current
IOML(2)
P00, P01
Per 1 applicable pin
20
IOML(3)
Port 7
Per 1 applicable pin
7.5
ΣIOAL(1)
Port 7
Total of all applicable pins
15
current
ΣIOAL(2)
Port 0
Total of all applicable pins
40
ΣIOAL(3)
P10 to P14
Total of all applicable pins
35
ΣIOAL(4)
Ports 1, 2, 3
Total of all applicable pins
40
ΣIOAL(5)
Ports 0, 1, 2, 3
Total of all applicable pins
70
Pd max(1)
QFP36(7×7)
Ta=-40 to +85°C
Dissipation
120
Package only
Pd max(2)
mA
15
Ports 1, 2, 3
Total output
Power
V
-5
P71 to P73
ΣIOAH(4)
unit
-10
IOMH(2)
ΣIOAH(3)
max
-0.3
(Note 1-1)
Ports 0, 2, 3
Low level output current
min
Ta=-40 to +85°C
mW
Package with thermal
275
resistance board
(Note 1-2)
Operating ambient
Topr
Temperature
Storage ambient
temperature
Tstg
-40
+85
-55
+125
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A0970-11/27
LC87F2H08A
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
max
unit
2.7
5.5
VDD(2)
0.294μs ≤ tCYC ≤ 200μs
2.2
5.5
VDD(3)
0.735μs ≤ tCYC ≤ 200μs
1.8
5.5
VDD(1)
supply voltage
Memory
typ
0.245μs ≤ tCYC ≤ 200μs
Operating
(Note 2-1)
min
VHD
VDD1
VDD1
sustaining
RAM and register contents sustained
in HOLD mode.
1.6
supply voltage
High level
VIH(1)
input voltage
Ports 1, 2, 3,
P71 to P73
P70 port input/
1.8 to 5.5
0.3VDD+0.7
VDD
1.8 to 5.5
0.3VDD+0.7
VDD
1.8 to 5.5
0.9VDD
VDD
interrupt side
VIH(2)
Ports 0
VIH(3)
Port 70 watchdog
timer side
Low level
VIH(4)
CF1, RES
1.8 to 5.5
0.75VDD
VDD
VIL(1)
Ports 1, 2, 3,
4.0 to 5.5
VSS
0.1VDD+0.4
1.8 to 4.0
VSS
0.2VDD
4.0 to 5.5
VSS
0.15VDD+0.4
1.8 to 4.0
VSS
0.2VDD
1.8 to 5.5
VSS
0.8VDD-1.0
1.8 to 5.5
VSS
0.25VDD
input voltage
V
P71 to P73
P70 port input/
interrupt side
VIL(2)
Ports 0
VIL(3)
Port 70 watchdog
timer side
VIL(4)
CF1, RES
Instruction
tCYC
2.7 to 5.5
0.245
200
cycle time
(Note 2-2)
2.2 to 5.5
0.294
200
1.8 to 5.5
0.735
200
2.7 to 5.5
0.1
12
1.8 to 5.5
0.1
4
3.0 to 5.5
0.2
24.4
2.0 to 5.5
0.2
8
(Note 2-1)
External
FEXCF
CF1
• CF2 pin open
μs
• System clock frequency division
system clock
frequency
ratio=1/1
• External system clock duty=50±5%
• CF2 pin open
MHz
• System clock frequency division
ratio=1/2
• External system clock duty=50±5%
Oscillation
FmCF(1)
CF1, CF2
range
12MHz ceramic oscillation
See Fig. 1.
frequency
FmCF(2)
CF1, CF2
(Note 2-3)
10MHz ceramic oscillation
See Fig. 1.
FmCF(3)
CF1, CF2
2.7 to 5.5
12
2.2 to 5.5
10
1.8 to 5.5
4
2.2 to 5.5
4
4MHz ceramic oscillation.
CF oscillation normal amplifier size selected.
See Fig. 1. (CFLAMP=0)
4MHz ceramic oscillation.
CF oscillation low amplifier size
selected. (CFLAMP=1)
MHz
See Fig. 1.
FmMRC
Frequency variable RC oscillation. 1/2
frequency division ration. (RCCTD=0)
2.7 to 5.5
7.44
8.0
8.56
(Note 2-4)
FmRC
Internal medium-speed RC oscillation
1.8 to 5.5
0.5
1.0
2.0
FmSRC
Internal low-speed RC oscillation
1.8 to 5.5
50
100
200
FsX’tal
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
kHz
1.8 to 5.5
32.768
Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Note 2-4: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the
multifrequency RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
No.A0970-12/27
LC87F2H08A
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High level input
IIH(1)
current
Ports 0, 1, 2, 3
Output disabled
Port 7
Pull-up resistor off
RES
VIN=VDD
(Including output Tr's off leakage
min
typ
max
unit
1.8 to 5.5
1
1.8 to 5.5
15
current)
Low level input
IIH(2)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2, 3
Output disabled
Port 7
Pull-up resistor off
RES
VIN=VSS
(Including output Tr's off leakage
CF1
VIN=VSS
current
1.8 to 5.5
-1
1.8 to 5.5
-15
μA
current)
IIL(2)
High level output
VOH(1)
Ports 0, 1, 2
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
P71 to P73
IOH=-0.35mA
2.7 to 5.5
VDD-0.4
IOH=-0.15mA
1.8 to 5.5
VDD-0.4
IOH=-6mA
4.5 to 5.5
VDD-1
VOH(5)
IOH=-1.4mA
2.7 to 5.5
VDD-0.4
VOH(6)
IOH=-0.8mA
1.8 to 5.5
VDD-0.4
VOH(3)
VOH(4)
Low level output
VOL(1)
voltage
VOL(2)
Port 3
Ports 0, 1, 2, 3
IOL=10mA
4.5 to 5.5
1.5
IOL=1.4mA
2.7 to 5.5
0.4
IOL=0.8mA
1.8 to 5.5
0.4
IOL=1.4mA
2.7 to 5.5
0.4
IOL=0.8mA
1.8 to 5.5
0.4
IOL=25mA
4.5 to 5.5
1.5
VOL(7)
IOL=4mA
2.7 to 5.5
0.4
VOL(8)
IOL=2mA
1.8 to 5.5
0.4
VOH=0.9VDD
When Port 0 selected
4.5 to 5.5
15
35
80
low-impedance pull-up.
1.8 to 4.5
18
50
230
VOH=0.9VDD
When Port 0 selected
1.8 to 5.5
VOL(3)
VOL(4)
Port 7
VOL(5)
VOL(6)
Pull-up resistance
Rpu(1)
Rpu(2)
Rpu(3)
P00, P01
Ports 0, 1, 2, 3
Port 7
Port 0
V
kΩ
100
210
400
high-impedance pull-up.
Hysteresis voltage
Pin capacitance
VHYS(1)
Ports 1, 2, 3, 7
2.7 to 5.5
0.1VDD
VHYS(2)
RES
1.8 to 2.7
0.07VDD
CP
All pins
1.8 to 5.5
10
V
For pins other than that under test:
VIN=VSS
f=1MHz
pF
Ta=25°C
No.A0970-13/27
LC87F2H08A
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Input clock
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Specification
Pin/
Conditions
Remarks
SCK0(P12)
VDD[V]
• See Fig. 5.
tSCK(2)
Low level
tSCKL(2)
tCYC
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 5.
1/2
1.8 to 5.5
tSCK
tSCKH(2)
1/2
Serial input
pulse width
Data setup time
SB0(P11),
SI0(P11)
• Must be specified with
respect to rising edge of
SIOCLK.
Data hold time
Input clock
Output delay
tdD0(1)
0.05
1.8 to 5.5
• See Fig. 5.
thDI(1)
time
SO0(P10),
SB0(P11)
0.05
• Continuous data
(1/3)tCYC
transmission/reception mode
+0.08
(Note 4-1-2)
tdD0(2)
• Synchronous 8-bit mode
tdD0(3)
(Note 4-1-2)
(Note 4-1-2)
Output clock
Serial output
tsDI(1)
unit
1
pulse width
High level
max
1
tSCKH(1)
Frequency
typ
2
1.8 to 5.5
pulse width
High level
min
pulse width
Output clock
Serial clock
Parameter
μs
1tCYC
+0.08
1.8 to 5.5
(1/3)tCYC
+0.08
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 5.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Specification
Pin/
Conditions
Remarks
SCK1(P15)
VDD[V]
See Fig. 5.
1.8 to 5.5
pulse width
High level
Frequency
SCK1(P15)
• CMOS output selected
tSCKL(4)
2
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 5.
Data hold time
thDI(2)
0.05
1.8 to 5.5
0.05
Output delay time
Serial output
tsDI(2)
unit
1
1.8 to 5.5
pulse width
High level
max
1
• See Fig. 5.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
pulse width
Output clock
Serial clock
Parameter
tdD0(4)
SO1(P13),
SB1(P14)
μs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output state
1.8 to 5.5
change in open drain output
(1/3)tCYC
+0.08
mode.
• See Fig. 5.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0970-14/27
LC87F2H08A
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1 are
INT2(P72),
enabled.
min
typ
1.8 to 5.5
1
1.8 to 5.5
2
1.8 to 5.5
64
1.8 to 5.5
256
1.8 to 5.5
200
max
unit
INT4(P20 to P21),
INT5(P30 to P31)
tPIH(2)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(2)
filter time constant is
• Event inputs for timer 0 are
1/1
enabled.
tPIH(3)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(3)
filter time constant is
• Event inputs for timer 0 are
1/32
nabled.
tPIH(4)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(4)
filter time constant is
• Event inputs for timer 0 are
1/128
tPIL(5)
RES
tCYC
enabled.
• Resetting is enabled.
μs
No.A0970-15/27
LC87F2H08A
AD Converter Characteristics at VSS1 = VSS2 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN6(P06),
AN8(P70),
accuracy
AN9(P71)
Conversion time
(Note 6-1)
(Note 6-1)
• Ta=-10 to +50°C
• See Conversion time calculation
TCAD
min
typ
2.4 to 5.5
formulas. (Note 6-2)
max
unit
12
bit
3.0 to 5.5
±16
2.4 to 3.6
±20
4.0 to 5.5
32
115
3.0 to 5.5
64
115
2.4 to 3.6
410
425
2.4 to 5.5
VSS
VDD
LSB
μs
• See Conversion time calculation
formulas. (Note 6-2)
• Ta=-10 to +50°C
Analog input
VAIN
voltage range
Analog port
IAINH
VAIN=VDD
2.4 to 5.5
input current
IAINL
VAIN=VSS
2.4 to 5.5
V
1
μA
-1
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN6(P06)
Conversion time
(Note 6-1)
TCAD
AN9(P71)
typ
max
• See Conversion time calculation
formulas. (Note 6-2)
unit
8
bit
±1.5
2.4 to 5.5
AN8(P70)
accuracy
min
2.4 to 5.5
4.0 to 5.5
20
90
3.0 to 5.5
40
90
2.4 to 3.6
250
265
2.4 to 5.5
VSS
VDD
LSB
μs
• See Conversion time calculation
formulas. (Note 6-2)
• Ta=-10 to +50°C
Analog input
VAIN
voltage range
Analog port
IAINH
VAIN=VDD
2.4 to 5.5
input current
IAINL
VAIN=VSS
2.4 to 5.5
1
-1
V
μA
Conversion time calculation formulas:
12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2)× (1/3)×tCYC
External
Operating supply
oscillation
voltage range
(FmCF)
(VDD)
System division ratio
Cycle time
(SYSDIV)
(tCYC)
AD division
AD conversion time
(TCAD)
ratio
(ADDIV)
12bit AD
8bit AD
21.5μs
4.0V to 5.5V
1/1
250ns
1/8
34.8μs
3.0V to 5.5V
1/1
250ns
1/16
69.5μs
42.8μs
4.0V to 5.5V
1/1
300ns
1/8
41.8μs
25.8μs
3.0V to 5.5V
1/1
300ns
1/16
83.4μs
51.4μs
3.0V to 5.5V
1/1
750ns
1/8
104.5μs
64.5μs
2.4V to 3.6V
1/1
750ns
1/32
416.5μs
256.5μs
CF-12MHz
CF-10MHz
CF-4MHz
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
No.A0970-16/27
LC87F2H08A
Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1=VSS2=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
POR release
PORRL
voltage
Detection
min
typ
max
• Select from option.
1.67V
1.55
1.67
1.79
(Note 7-1)
1.97V
1.85
1.97
2.09
2.07V
1.95
2.07
2.19
2.37V
2.25
2.37
2.49
2.57V
2.45
2.57
2.69
2.87V
2.75
2.87
2.99
3.86V
3.73
3.86
3.99
4.35V
4.21
4.35
4.49
0.7
0.95
unit
V
• See Fig. 7.
POUKS
voltage
(Note 7-2)
unknown state
Power supply
• Power supply rise
PORIS
rise time
100
time from 0V to 1.6V.
ms
Note7-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled.
Note7-2: POR is in an unknown state before transistors start operation.
Low Voltage Detection Reset (LVD) Characteristics at Ta = -40°C to +85°C, VSS1=VSS2=0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Option selected
voltage
LVD reset Voltage
LVDET
(Note 8-2)
• Select from option.
(Note 8-1)
(Note 8-3)
• See Fig. 8.
LVD hysteresys
LVHYS
width
Detection voltage
LVUKS
unknown state
Low voltage
detection
minimum Width
min
max
1.91V
1.81
1.91
2.01
2.01V
1.91
2.01
2.11
2.31V
2.21
2.31
2.41
2.51V
2.41
2.51
2.61
2.81V
2.71
2.81
2.91
3.79V
3.69
3.79
3.89
4.28V
4.18
4.28
4.38
1.91V
55
2.01V
55
2.31V
55
2.51V
55
2.81V
60
3.79V
65
4.28V
65
unit
V
mV
• See Fig. 8.
(Note 8-4)
TLVDW
typ
0.7
0.95
V
• LVDET-0.5V
• See Fig. 9.
0.2
ms
(Reply sensitivity)
Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled.
Note8-2: LVD reset voltage specification values do not include hysteresis voltage.
Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note8-4: LVD is in an unknown state before transistors start operation.
No.A0970-17/27
LC87F2H08A
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
Specification
Pin/
Conditions
Remarks
VDD1
VDD[V]
typ
max
unit
• FmCF=12MHz ceramic oscillation mode
consumption
• System clock set to 12MHz side
current
• Internal low speed and medium speed RC
(Note 9-1)
min
2.7 to 5.5
7.4
13.0
2.7 to 3.6
4.4
8.1
3.0 to 5.5
9.7
16.2
3.0 to 3.6
5.3
8.7
2.2 to 5.5
6.6
11.9
2.2 to 3.6
4.0
7.4
1.8 to 5.5
2.9
6.5
1.8 to 3.6
2.2
4.2
2.2 to 5.5
1.1
2.5
2.2 to 3.6
0.6
1.3
1.8 to 5.5
0.6
1.7
1.8 to 3.6
0.3
0.9
2.7 to 5.5
5.0
9.1
2.7 to 3.6
3.6
5.8
1.8 to 5.5
75
370
1.8 to 3.6
46
192
5.0
75
176
3.3
46
115
2.5
35
85
oscillation stopped.
• Frequency variable RC oscillation stopped.
(Note 9-2)
• 1/1 frequency division ratio
IDDOP(2)
• CF1=24MHz external clock
• System clock set to CF1 side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(3)
• FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(4)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
mA
• 1/1 frequency division ratio
IDDOP(5)
• CF oscillation low amplifier size selected.
(CFLAMP=1)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDOP(6)
• FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed RC oscillation stopped.
• System clock set to internal medium speed
RC oscillation.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(7)
• FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed and medium speed RC
oscillation stopped.
• System clock set to 8MHz with
frequency variable RC oscillation
• 1/1 frequency division ratio
IDDOP(8)
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
oscillation.
• Internal medium speed RC oscillation sopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(9)
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
µA
oscillation.
• Internal medium speed RC oscillation sopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• Ta=-10 to +50°C
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A0970-18/27
LC87F2H08A
Continued from preceding page.
Parameter
Normal mode
Symbol
IDDOP(10)
Specification
Pin/
Conditions
Remarks
VDD1
VDD[V]
consumption
• System clock set to 32.768kHz side
current
• Internal low speed and medium speed RC
(Note 9-1)
min
typ
max
unit
• FsX’tal=32.768kHz crystal oscillation mode
1.8 to 5.5
38
139
1.8 to 3.6
15
66
5.0
38
101
3.3
15
46
2.5
9.0
28
2.7 to 5.5
3.1
5.6
2.7 to 3.6
1.6
2.9
3.0 to 5.5
4.9
8.6
3.0 to 3.6
2.3
3.8
2.2 to 5.5
2.7
5.3
2.2 to 3.6
1.4
2.6
1.8 to 5.5
1.4
3.5
1.8 to 3.6
0.7
1.3
2.2 to 5.5
0.7
1.8
2.2 to 3.6
0.3
0.7
1.8 to 5.5
0.4
1.1
1.8 to 3.6
0.2
0.5
oscillation stopped.
• Frequency variable RC oscillation stopped.
(Note 9-2)
• 1/2 frequency division ratio
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(11)
• System clock set to 32.768kHz side
μA
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• Ta=-10 to +50°C
HALT mode
IDDHALT(1)
VDD1
• HALT mode
consumption
• FmCF=12MHz ceramic oscillation mode
current
• System clock set to 12MHz side
(Note 9-1)
• Internal low speed and medium speed RC
(Note 9-2)
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(2)
• HALT mode
• CF1=24MHz external clock
• System clock set to CF1 side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDHALT(3)
• HALT mode
• FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(4)
• HALT mode
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
mA
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(5)
• HALT mode
• CF oscillation low amplifier size selected.
(CFLAMP=1)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDHALT(6)
• HALT mode
• FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed RC oscillation stopped.
• System clock set to internal medium speed
RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A0970-19/27
LC87F2H08A
Continued from preceding page.
Parameter
HALT mode
Symbol
IDDHALT(7)
Specification
Pin/
Conditions
remarks
VDD1
VDD[V]
consumption
• FsX’tal=32.768kHz crystal oscillation mode
current
• Internal low speed and medium speed RC
(Note 9-1)
min
typ
max
unit
• HALT mode
2.7 to 5.5
1.8
3.5
2.7 to 3.6
1.1
2.0
1.8 to 5.5
23
260
oscillation stopped.
• System clock set to 8MHz with
(Note 9-2)
frequency variable RC oscillation
• 1/1 frequency division ratio
• HALT mode
IDDHALT(8)
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
μA
oscillation.
• Internal medium speed RC oscillation sopped.
• Frequency variable RC oscillation stopped.
1.8 to 3.6
13
119
5.0
23
65
3.3
13
35
2.5
9.2
25
1.8 to 5.5
25
112
• 1/1 frequency division ratio
• HALT mode
IDDHALT(9)
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC
oscillation.
• Internal medium speed RC oscillation sopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• Ta=-10 to +50°C
• HALT mode
IDDHALT(10)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low speed and medium speed RC
μA
oscillation stopped.
• Frequency variable RC oscillation stopped.
1.8 to 3.6
8.5
56
5.0
25
69
3.3
8.5
29
2.5
4.2
15
• 1/2 frequency division ratio
• HALT mode
IDDHALT(11)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• Ta=-10 to +50°C
HOLD mode
IDDHOLD(1)
VDD1
consumption
current
IDDHOLD(2)
(Note 9-1)
(Note 9-2)
HOLD mode
1.8 to 5.5
0.04
30
• CF1=VDD or open (External clock mode)
1.8 to 3.6
0.02
21
HOLD mode
5.0
0.04
2.3
• CF1=VDD or open (External clock mode)
3.3
0.02
1.5
2.5
• Ta=-10 to +50°C
IDDHOLD(3)
0.017
1.2
1.8 to 5.5
3.2
35
1.8 to 3.6
2.7
24
HOLD mode
5.0
3.2
6.5
• CF1=VDD or open (External clock mode)
3.3
2.7
4.5
2.5
2.5
4.2
106
HOLD mode
• CF1=VDD or open (External clock mode)
• LVD option selected
IDDHOLD(4)
• Ta=-10 to +50°C
• LVD option selected
Timer HOLD
IDDHOLD(5)
mode
consumption
current
(Note 9-1)
(Note 9-2)
IDDHOLD(6)
VDD1
Timer HOLD mode
1.8 to 5.5
22
• FsX’tal=32.768 kHz crystal oscillation mode
1.8 to 3.6
7.5
45
Timer HOLD mode
5.0
22
62
• FsX’tal=32.768kHz crystal oscillation mode
3.3
7.5
23
2.5
2.9
12
• Ta=-10 to +50°C
μA
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
No.A0970-20/27
LC87F2H08A
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Onboard
IDDFW(1)
VDD1
min
typ
max
unit
• Only current of the Flash block.
programming
2.2 to 5.5
5
10
mA
20
30
ms
40
60
µs
current
Programming
tFW(1)
• Erasing time
time
tFW(2)
• Programming time
2.2 to 5.5
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Transfer rate
UBR
UTX(P20)
1.8 to 5.5
URX(P21)
Data length:
Stop bits :
Parity bits:
min
typ
16/3
max
unit
8192/3
tCYC
7/8/9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start bit
Start of
transmission
Stop bit
End of
transmission
Transmit data (LSB first)
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Start bit
Start of
reception
Stop bit
Receive data (LSB first)
End of
reception
UBR
No.A0970-21/27
LC87F2H08A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
• CF oscillation normal amplifier size selected (CFLAMP=0)
MURATA
Nominal
Frequency
12MHz
Circuit Constant
Type
SMD
SMD
Oscillator Name
CSTCE12M0G52-R0
CSTCE10M0G52-R0
C1
C2
Rf
Operating
Rd
Voltage Range
[V]
Oscillation
Stabilization Time
typ
max
[ms]
[ms]
[pF]
[pF]
[Ω]
[Ω]
(10)
(10)
Open
1.0k
2.7 to 5.5
0.1
0.5
Open
680
2.2 to 3.6
0.1
0.5
Open
1.0k
2.3 to 5.5
0.1
0.5
(10)
Remarks
(10)
10MHz
LEAD
CSTLS10M0G53-B0
(15)
(15)
Open
1.0k
2.5 to 5.5
0.1
0.5
SMD
CSTCE8M00G52-R0
(10)
(10)
Open
1.5k
2.2 to 5.5
0.1
0.5
LEAD
CSTLS8M00G53-B0
(15)
(15)
Open
1.5k
2.2 to 5.5
0.1
0.5
SMD
CSTCR6M00G53-R0
(15)
(15)
Open
2.2k
2.2 to 5.5
0.1
0.5
LEAD
CSTLS6M00G53-B0
(15)
(15)
8MHz
Internal
C1,C2
6MHz
SMD
CSTCR4M00G53-R0
(15)
(15)
LEAD
CSTLS4M00G53-B0
(15)
(15)
4MHz
Open
2.2k
2.2 to 5.5
0.1
0.5
Open
1.5k
1.8 to 2.7
0.2
0.6
Open
3.3k
1.9 to 5.5
0.2
0.6
Open
3.3k
1.9 to 5.5
0.2
0.6
• CF oscillation low amplifier size selected (CFLAMP=1)
MURATA
Nominal
Frequency
Circuit Constant
Type
Oscillator Name
CSTCR4M00G53-R0
C1
C2
[pF]
[pF]
(15)
(15)
Rd
Voltage Range
[V]
Oscillation
Stabilization Time
Typ
Max
[Ω]
[Ω]
[ms]
[ms]
Open
1.0k
2.1 to 2.7
0.2
0.6
Open
2.2k
2.5 to 5.5
0.2
0.6
(15)
Open
1.0k
1.9 to 2.7
0.2
0.7
Internal
Open
1.0k
2.2 to 2.7
0.2
0.6
C1,C2
Open
2.2k
2.5 to 5.5
0.2
0.6
Open
1.0k
2.0 to 2.7
0.2
0.7
4MHz
CSTLS4M00G53-B0
(15)
(15)
LEAD
CSTLS4M00G53095-B0
(15)
Remarks
(15)
SMD
CSTCR4M00G53095-R0
Rf
Operating
(15)
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 3).
No.A0970-22/27
LC87F2H08A
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
EPSON TOYOCOM
Nominal
Frequency
Type
Circuit Constant
Oscillator
Name
Operating
C1
C2
Rf
Rd
[pF]
[pF]
[Ω]
[Ω]
9
9
Open
330k
Voltage Range
[V]
Oscillation
Stabilization Time
typ
max
[s]
[s]
1.4
4.0
Remarks
Applicable
32.768kHz
SMD
MC-306
1.8 to 5.5
CL value =
7.0pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 3):
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF2/XT2
CF1/XT1
Rf
Rd
C1
CF/X’tal
C2
Figure 1 CF and XT Oscillator Circuit
0.5VDD
Figure 2 AC Timing Measurement Point
No.A0970-23/27
LC87F2H08A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Internal medium speed
RC oscillation
tmsCF/tmsX’tal
CF1, CF2
Operating
mode
Reset
Unpredictable
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absent
HOLD reset signal valid
Internal medium speed
RC oscillation or
low speed RC oscillation
tmsCF/tmsX’tal
CF1, CF2
(Note)
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Note: External oscillation circuit is selected.
Figure 3 Oscillation Stabilization Times
No.A0970-24/27
LC87F2H08A
VDD
Note:
External circuits for reset may vary
depending on the usage of POR and LVD.
Please refer to the user’s manual for more
information..
RRES
RES
CRES
Figure 4 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 5 Serial I/O Output Waveforms
tPIL
tPIH
Figure 6 Pulse Input Timing Signal Waveform
No.A0970-25/27
LC87F2H08A
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
100μs or longer
Reset period
Unknown-state
(POUKS)
RES
Figure 7 Waveform observed when only POR is used (LVD not used)
(RESET pin: Pull-up resistor RRES only)
• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an
external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 100μs or longer.
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
VDD
LVD reset voltage
(LVDET)
Reset period
Reset period
Reset period
Unknown-state
(LVUKS)
RES
Figure 8 Waveform observed when both POR and LVD functions are used
(RESET pin: Pull-up resistor RRES only)
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
level.
No.A0970-26/27
LC87F2H08A
VDD
LVD release voltage
LVD reset voltage
LVDET-0.5V
TLVDW
VSS
Figure 9 Low voltage detection minimum width
(Example of momentary power loss/Voltage variation waveform)
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warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
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PS No.A0970-27/27
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