DATA SHEET
www.onsemi.com
CMOS LSI
Iris/Zoom/Focus/Day‐Night
Switching Drive Controller
TQFP64 7x7
CASE 932BC
LC898201
Overview
LC898201 is the appropriate motor control LSI for the surveillance
camera usage, and it can drive iris, focus, zoom and Day/Night
switching simultaneously.
It incorporates feedback control circuits (max 2-systems), stepper
motor control circuits (max 3-system) and VCM control circuit
(1-system).
• Feedback Control Applies Iris
Stepper Motor Controls Apply Focus, Zoom and Day/Night
Switching
• Feedback Control Applies Iris
Stepper Motor Controls Apply Focus and Zoom
VCM Applies Day/Night Switching
MARKING DIAGRAM
LC898201
12K1
XXXXX
LC898201
12K1
XXXXX
= Specific Device Code 1
= Specific Device Code 2
= Lot Number
LC898201 can control a variety of lens units like these examples.
ORDERING INFORMATION
Features
• Built-in Equalizer Circuit by Digital Operation
Iris Control Equalizer Circuit
Focus Control Equalizer Circuit (MR sensor can be connected)
♦ Coefficients can be Set Arbitrarily through the SPI Interface
♦ Computed Values in the Equalizer can be Monitored
Built-in 3ch Stepper Motor Control Circuits
SPI Bus Interface
PI Control Circuit
♦ 30 mA Sink Output Terminal
♦ Built-in PI Detecting Function (A/D method)
A/D Converter
♦ 12bit (6ch): Iris, Focus, PI Detection, General
D/A Converter
♦ 8bit (4ch): Hall Offset, Constant Current Bias, MR Sensor Offset
Operation Amplifier
♦ 3ch (Iris Control ×1, Focus Control ×2)
PWM Pulse Generator
♦ PWM Pulse Generator for Feedback Control
(Up to 12 bit Accuracy)
♦ PWM Pulse Generator for Stepper Motor Control
(Up to 1024 Micro Steps)
♦ PWM Pulse Generator for General-purpose H-Bridge
(128 Voltage Levels)
Motor Driver
♦ ch1 to ch6: Io max = 200 mA
♦ ch7: Io max = 300 mA
♦ Built-in Thermal Protection Circuit
♦ Built-in Low-voltage Malfunction Prevention Circuit
♦
♦
•
•
•
•
•
•
•
•
© Semiconductor Components Industries, LLC, 2014
May, 2022 − Rev. 3
1
Device
Package
Shipping{
LC898201TA−NH
TQFP64 7x7
(Pb−Free /
Halogen Free)
1000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Features (Continued)
• Operation Clock
Selective Usage either Internal OSC
(Typ. 48 MHz) or External Oscillating
Circuit (48 MHz)
Package
♦ TQFP64 (7 × 7) 0.4 mm Pitch
♦ Lead-free, Halogen-free
Power Supply Voltage
♦ Logic Unit: 2.7 V to 3.6 V
(IO, Internal Core)
♦ Driver Unit: 2.7 V to 5.5 V
(Motor Drive)
♦
•
•
Publication Order Number:
LC898201/D
LC898201
BLOCK DIAGRAMS
Application 1
Stepper 3ch-ex.1 & using Crystal oscillator (or Ceramic oscillator) & PI sensor: RL emitter connection.
XTALCK
OSC
Clock
divider
XTAL
CLKO1/MON
Delay
&Inv.
CLKO2/MON
ADIN1
to each
block
OPINM1
Ex.) Internal clock is X’tal clock.
SSB
SCLK
MOSI
MISO
BUSY/MON
Serial I/F
AC
D/A
ZRESET
PWM
Modulation
for STM
STM Control
Logic
H−Bridge
Driver
(200 mA )
OUT1A
H−Bridge
Driver
(200 mA )
OUT2A
K
RL
OPINM3
OPINP6
OPINM6
PWM
Modulation
for STM
STM Control
Logic
ADIN6
H−Bridge
Driver
(200 mA )
OUT3A
H−Bridge
Driver
(200 mA )
OUT4A
OUT3B
AC
PI
OUT4B
K
ADPIIN2
OPINP7A
OPINM7A
PWM
Modulation
for VCM
VCM Control
Logic
STM Control
Logic
PWM
Modulation
for STM
EQ
PWM
Modulation
for VCM
EQ
PWM
Modulation
for VCM
VREF
OPINM7B
From PI Sensor
E
RL
PIS1/MON
VREF
ADIN7A
OPINP7B
E
OUT2B
ADPIIN1
BIASO6
Hall
PI
OUT1B
A/D
ADIN7B
VREF
Gen.
VREF
ADVRH
H−Bridge
Driver
(200 mA )
H−Bridge
Driver
(200 mA )
ADVRL
to each block
for reset
MR Signal
Decode Logic
to driver for
standby
PI
OUT5B
OUT6A
K
OUT6B
PIS2/MON
H−Bridge
Driver
(300 mA )
AC
OUT5A
LVS
TSD
OUT7B
Ch
ch1
ch3
ch4
ch5
ch6
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2
VM
PGND
DAOPVSS
DAOPVDD
DVSS
ADVSS
ADVDD
DVDD
ch7
Figure 1. Application 1
RL
OUT7A
ch2
VSYNC1/MON
VSYNC2/MON/
SHUTTER
MON
E
Connection to
“ADIN7B”
Act/Motor
Item
STM
Zoom
STM
Focus
STM
D/N
HALL−VCM
Iris
LC898201
Application 2
Stepper 3ch-ex.2 & using internal OSC & PI sensor: RL collector connection.
XTALCK
OSC
Clock
divider
XTAL
CLKO1/MON
Delay
&Inv.
CLKO2/MON
ADIN1
to each
block
OPINM1
Ex.) Internal clock is OSC clock. X’tal supplies clock
to ext. components through CLKO1 or CLKO2.
SSB
SCLK
MOSI
MISO
BUSY/MON
Serial I/F
D/A
ZRESET
PWM
Modulation
for STM
STM Control
Logic
H−Bridge
Driver
(200 mA )
OUT1A
H−Bridge
Driver
(200 mA )
OUT2A
A
PI
OUT1B
OUT2B
ADPIIN1
BIASO6
KE
OPINM3
OPINP6
OPINM6
PWM
Modulation
for STM
STM Control
Logic
ADIN6
H−Bridge
Driver
(200 mA )
OUT3A
H−Bridge
Driver
(200 mA )
OUT4A
A
PI
OUT3B
OUT4B
VREF
ADIN7B
VREF
Gen.
H−Bridge
Driver
(200 mA )
OUT5A
H−Bridge
Driver
(200 mA )
OUT6A
PWM
Modulation
for VCM
EQ
A/D
PI
PWM
Modulation
for STM
STM Control
Logic
OPINM7B
A
PWM
Modulation
for VCM
VCM Control
Logic
ADIN7A
From PI Sensor
KE
PIS1/MON
VREF
OPINM7A
OPINP7B
RL
C
ADPIIN2
OPINP7A
RL
C
RL
C
OUT5B
KE
OUT6B
PIS2/MON
Connection to
“ADIN7B”
(for D/N control)
VREF
H−Bridge
Driver
(300 mA )
PWM
Modulation
for VCM
EQ
ADVRH
ADVRL
MR Signal
Decode Logic
to each block
for reset
to driver for
standby
LVS
TSD
OUT7A
OUT7B
Ch
ch1
ch2
VSYNC1/MON
VSYNC2/MON/
SHUTTER
MON
ch3
ch4
ch5
ch6
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3
VM
PGND
DAOPVSS
DAOPVDD
DVSS
Figure 2. Application 2
ADVSS
ADVDD
DVDD
ch7
Act/Motor
Item
STM
Zoom
STM
Focus
STM
Iris
VCM
D/N
LC898201
Application−3
Stepper 2ch & using internal OSC & PI sensor: RL emitter connection.
XTALCK
OSC
Clock
divider
XTAL
CLKO1/MON
Delay
&Inv.
CLKO2/MON
ADIN1
to each
block
OPINM1
Ex.) Internal clock is OSC clock.
SSB
SCLK
MOSI
MISO
BUSY/MON
Serial I/F
AC
D/A
ZRESET
PWM
Modulation
for STM
STM Control
Logic
H−Bridge
Driver
(200 mA )
OUT1A
H−Bridge
Driver
(200 mA )
OUT2A
OUT1B
K
OUT2B
OPINM3
OPINP6
OPINM6
PWM
Modulation
for STM
STM Control
Logic
ADIN6
H−Bridge
Driver
(200 mA )
OUT3A
H−Bridge
Driver
(200 mA )
OUT4A
OUT3B
AC
PI
OUT4B
ADPIIN2
OPINP7A
K
ADIN7A
VCM Control
Logic
PWM
Modulation
for VCM
STM Control
Logic
PWM
Modulation
for STM
EQ
PWM
Modulation
for VCM
EQ
PWM
Modulation
for VCM
VREF
OPINM7B
A/D
ADIN7B
VREF
Gen.
VREF
ADVRH
H−Bridge
Driver
(200 mA )
OUT5A
H−Bridge
Driver
(200 mA )
OUT6A
OUT5B
OUT6B
PIS2/MON
H−Bridge
Driver
(300 mA )
ADVRL
MR Signal
Decode Logic
to each block
for reset
to driver for
standby
LVS
TSD
OUT7A
OUT7B
Ch
ch1
ch2
VSYNC1/MON
VSYNC2/MON/
SHUTTER
MON
ch3
ch4
ch5
ch6
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4
VM
PGND
DAOPVSS
DAOPVDD
DVSS
ADVSS
ADVDD
DVDD
ch7
Figure 3. Application 3
E
RL
PIS1/MON
VREF
OPINM7A
OPINP7B
E
RL
ADPIIN1
BIASO6
Hall
PI
Act/Motor
Item
STM
Zoom
STM
Focus
VCM
D/N
−−−
HALL−VCM
−−−
Iris
LC898201
Application−4
MR−VCM & using internal OSC & PI sensor: RL emitter connection.
XTALCK
OSC
Clock
divider
XTAL
CLKO1/MON
Delay
&Inv.
CLKO2/MON
ADIN1
to each
block
OPINM1
Ex.) Internal clock is OSC clock.
SSB
SCLK
MOSI
MISO
BUSY/MON
Serial I/F
AC
D/A
ZRESET
PWM
Modulation
for STM
STM Control
Logic
H−Bridge
Driver
(200 mA )
OUT1A
H−Bridge
Driver
(200 mA )
OUT2A
OUT1B
K
OUT2B
OPINM3
OPINP6
OPINM6
PWM
Modulation
for STM
STM Control
Logic
ADIN6
H−Bridge
Driver
(200 mA )
OUT3A
H−Bridge
Driver
(200 mA )
OUT4A
OUT3B
AC
PI
OUT4B
ADPIIN2
MR Sensor
OPINP7A
K
ADIN7A
VCM Control
Logic
PWM
Modulation
for VCM
STM Control
Logic
PWM
Modulation
for STM
EQ
PWM
Modulation
for VCM
EQ
PWM
Modulation
for VCM
VREF
A/D
ADIN7B
VREF
Gen.
VREF
ADVRH
H−Bridge
Driver
(200 mA )
OUT5A
H−Bridge
Driver
(200 mA )
OUT6A
H−Bridge
Driver
(300 mA )
to each block
for reset
MR Signal
Decode Logic
to driver for
standby
VM
TSD
PGND
DAOPVSS
DAOPVDD
DVSS
ADVSS
ADVDD
DVDD
Figure 4. Application 4
5
OUT6B
OUT7A
OUT7B
Ch
ch1
ch2
LVS
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OUT5B
PIS2/MON
ADVRL
VSYNC1/MON
VSYNC2/MON/
SHUTTER
MON
E
RL
PIS1/MON
VREF
OPINM7A
OPINP7B
OPINM7B
E
RL
ADPIIN1
BIASO6
Hall
PI
ch3
Act/Motor
Item
STM
Zoom
STM
D/N
ch5
VCM
General
ch6
HALL−VCM
Iris
ch7
MR −VCM
Focus
ch4
LC898201
PIN DESCRIPTION
Table 1. PIN DESCRIPTION
TYPE
I
INPUT
P
O
OUTPUT
Power, GND
B(I)
BIDIRECTION: INPUT at Reset
B(O)
BIDIRECTION: OUTPUT at Reset
NC
NOT CONNECT
SPI INTERFACE (SLAVE)
SSB
I
Chip select
SCLK
I
Clock
MOSI
I
Received data
MISO
B(O)
Transmit data
BUSY/MON
B(O)
Transfer busy / Monitor output
PI SENSOR DRIVE SIGNAL OUTPUT
PIS1/MON
B(O)
PI sensor drive signal output 1 / Monitor output
PIS2/MON
B(O)
PI sensor drive signal output 2 / Monitor output
VIDEO SYNCHRONIZING SIGNAL INPUT
VSYNC1/MON
B(I)
Video synchronizing signal input / Monitor output (with pull-down resistance)
VSYNC2/MON /SHUTTER
B(I)
Video synchronizing signal input / Monitor output / Shutter input
(with pull-down resistance)
B(O)
Monitor output
MONITOR OUTPUT
MON
CLOCK OUTPUT
XTALCK
I
Oscillation amplifier input
XTAL
O
Oscillation amplifier output
CLKO1/MON
B(O)
Clock output 1 / Monitor output
CLKO2/MON
B(O)
Clock output 2 / Monitor output
I
Reset signal input (Low active)
O
CH6 Bias current output
OPINP6
I
CH6 OP Amp input (+)
OPINM6
I
CH6 OP Amp input (−)
RESET
ZRESET
BIAS CURRENT PIN
BIASO6
OP AMP PIN
OPINP7A
I
CH7−A OP Amp input (+)
OPINM7A
I
CH7−A OP Amp input (−)
OPINP7B
I
CH7−B OP Amp input (+)
OPINM7B
I
CH7−B OP Amp input (−)
ADIN1
B
General A/D input
ADIN6
B
CH6 A/D input (CH6 OP Amp output)
ADIN7A
B
CH7−A A/D input (CH7 OP Amp output)
A/D INPUT PIN
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LC898201
A/D INPUT PIN
ADIN7B
B
CH7−B A/D input (CH7 OP Amp output)
ADPIIN1
I
CH1/2 PI sensor signal A/D input
ADPIIN2
I
CH3/4 PI sensor signal A/D input
ADVRH
I
A/D conversion range standard voltage
ADVRL
I
A/D conversion range standard voltage
OUT1A
O
CH1 H−Bridge output
OUT1B
O
CH1 H−Bridge output
OUT2A
O
CH2 H−Bridge output
OUT2B
O
CH2 H−Bridge output
H−BRIDGE
OUT3A
O
CH3 H−Bridge output
OUT3B
O
CH3 H−Bridge output
OUT4A
O
CH4 H−Bridge output
OUT4B
O
CH4 H−Bridge output
OUT5A
O
CH5 H−Bridge output
OUT5B
O
CH5 H−Bridge output
OUT6A
O
CH6 H−Bridge output
OUT6B
O
CH6 H−Bridge output
OUT7A
O
CH7 H−Bridge output
OUT7B
O
CH7 H−Bridge output
OPINM1
I
Connect to GND (DAOPVSS)
OPINM3
I
Connect to GND (DAOPVSS)
DVDD
P
Digital VDD
DVSS
P
Digital GND
DAOPVDD
P
D/A, OP Amp VDD
DAOPVSS
P
D/A, OP Amp GND
ADVDD
P
A/D VDD
ADVSS
P
A/D GND
VM
P
H−Bridge VDD
PGND
P
H−Bridge GND
MISCELLANEOUS
POWER PIN
Process when pins are not used
• PIN TYPE “O” − The pin must be left open
• PIN TYPE “I” − The pin must not be left open. Please make sure to connect the pin to VDD or VSS even when it is not
•
used. (Please check with us whether to connect to VDD or VSS)
PIN TYPE “B” − Please contact us if you are uncertain about a processing method in the pin description in the PIN
layout table
A problem may occur if the processing method is used wrongly for any unused pin.
Please make sure to contact us.
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7
LC898201
PGND
VM
OPINM3
OPINM1
OPINM7A
OPINP7A
BIASO6
DAOPVDD
DAOPVSS
OPINM6
OPINP6
OPINM7B
OPINP7B
ADIN6
ADIN7B
PIN ASSIGNMENT
PIS1
OUT4A
PIS2
OUT5B
VSYNC1
OUT5A
VSYNC2
OUT6B
XTALCK
OUT6A
XTAL
PGND
(TOP VIEW)
Figure 5. TQFP64 (7y7)
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8
PGND
OUT4B
VM
OUT3A
DVSS
VM
DVDD
MON
OUT3B
DVSS
ADVSS
DVDD
OUT1A
BUSY
OUT1B
ADVDD
MISO
ADVRH
MOSI
OUT2A
SCLK
OUT2B
ADVRL
SSB
ADPIIN1
ZRESET
OUT7A
CLKO2
OUT7B
ADPIIN2
CLKO1
ADIN1
DVSS
PGND
DVDD
ADIN7A
LC898201
PIN NUMBER
Table 2. PIN NUMBER
Pin No.
Type
Pin name
1
P
DVDD
2
P
DVSS
3
B(O)
CLKO1
4
B(O)
CLKO2
5
I
ZRESET
6
I
SSB
7
I
SCLK
8
I
MOSI
9
B(O)
MISO
10
B(O)
BUSY
11
P
DVDD
12
P
DVSS
13
B(O)
MON
14
P
VM
15
P
VM
16
P
PGND
17
P
PGND
18
O
OUT6A
19
O
OUT6B
20
O
OUT5A
21
O
OUT5B
22
O
OUT4A
23
O
OUT4B
24
O
OUT3A
25
O
OUT3B
26
O
OUT1A
27
O
OUT1B
28
O
OUT2A
29
O
OUT2B
30
O
OUT7A
31
O
OUT7B
32
P
PGND
33
P
PGND
34
P
VM
35
P
VM
36
I
OPINM3
37
I
OPINM1
38
I
OPINM7A
39
I
OPINP7A
40
O
BIASO6
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LC898201
Table 2. PIN NUMBER (continued)
Pin No.
Type
Pin name
41
P
DAOPVDD
42
P
DAOPVSS
43
I
OPINM6
44
I
OPINP6
45
I
OPINM7B
46
I
OPINP7B
47
B
ADIN6
48
B
ADIN7B
49
B
ADIN7A
50
B
ADIN1
51
I
ADPIIN2
52
I
ADPIIN1
53
I
ADVRL
54
I
ADVRH
55
P
ADVDD
56
P
ADVSS
57
P
DVDD
58
P
DVSS
59
B(O)
PIS1
60
B(O)
PIS2
61
B(I)
VSYNC1
62
B(I)
VSYNC2
63
I
XTALCK
64
O
XTAL
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LC898201
ELECTRICAL CHARACTERISTICS
Logic, Analog
Logic, Analog power: DVDD/DVSS, OPDAVDD/ OPDAVSS, ADVDD/ADVSS, these should be connected at the same
voltage. They are shown DVDD/DVSS as follows.
ABSOLUTE MAXIMUM RATINGS (DVSS = 0 V)
Symbol
Conditions
Ratings
Unit
Supply Voltage
DVDD max
TA ≤ 25°C
−0.3 to 4.6
V
Input/Output Voltage
VIN, VOUT
TA ≤ 25°C
−0.3 to DVDD+0.3
V
Storage Temperature
Tstg
−55 to 125
°C
Operating Temperature
Topr
−20 to 85
°C
Parameter
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
ALLOWABLE OPERATING RANGES (TA = −20 to 85_C, DVSS = 0 V)
Parameter
Power Supply Voltage
Symbol
Min
Typ
Max
Unit
DVDD
2.7
3.3
3.6
V
VIN
0
−
DVDD
V
Except for OPINM1, OPINM3
0
−
VM
V
OPINM1, OPINM3
Input Voltage Range
Applicable Pins
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC CHARACTERISTICS: INPUT/OUTPUT LEVEL (TA = −20 to 85_C, DVSS = 0 V, DVDD = 2.7 to 3.6 V)
Parameter
Symbol
Conditions
Min
CMOS
High-level Input Voltage
VIH
Low-level Input Voltage
VIL
High-level Input Voltage
VIH
Low-level Input Voltage
VIL
High-level Output Voltage
VOH
IOH = −4 mA
Low-level Output Voltage
VOL
IOL = 4 mA
IOL = 30 mA
Typ
Max
0.7 DVDD
0.2 DVDD
CMOS Schmidt
0.75 DVDD
Unit
Applicable
Pins
V
(2)(3)
V
V
0.15 DVDD
DVDD − 0.4
V
V
(2)(3)(4)
0.4
V
(2)(3)
0.4
V
(4)
200
kW
(3)
PullDown Resistance
Rdn
40
Analog Input Voltage
VAI
DVSS
DVDD
V
(5)
PGND
VM
V
(6)
1
kW
(7)
1
mA
(8)
VGA Output Resistance
Rout
Analog Output Current
IAO
CMSDAC
= 001b & WH_DAV4
= 00h
80
(1)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Applicable Pins:
(1) ZRESET, SSB, SCLK, MOSI
(2) MISO, BUSY, MON, CLKO1, CLKO2
(3) VSYNC1, VSYNC2
(4) PIS1, PIS2
(5) OPINP6, OPINM6, OPINP7A, OPINM7A, OPINP7B, OPINM7B, ADPIIN1, ADPIIN2
(6) OPINM1, OPINM3
(7) ADIN1, ADIN6, ADIN7A, ADIN7B
(8) BIASO6
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11
LC898201
VM
ABSOLUTE MAXIMUM RATINGS (TA = 25_C, PGND = 0 V)
Symbol
Parameter
Conditions
Ratings
Unit
−0.3 to 7.0
V
Supply Voltage
VMmax
Output Peak Current
Iopeak1
OUT1A/B to OUT6A/B
t ≤ 10 ms, On-duty ≤ 20%
300
mA
Iopeak2
OUT7A/B
t ≤ 10 ms, On-duty ≤ 20%
450
mA
Iomax1
OUT1A/B to OUT6A/B
200
mA
Iomax2
OUT7A/B
300
mA
Output Continuous Current
Storage Temperature
Tstg
−55 to 125
°C
Operating Temperature
Topr
−20 to 85
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
ALLOWABLE OPERATING RANGES (TA = 25_C, PGND = 0 V)
Parameter
Symbol
Power Supply Voltage
Conditions
VM
Ratings
Unit
2.7 to 5.5
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS (TA = 25_C, PGND = 0 V, VM = 5 V)
Parameter
Output ON Resistance
Output ON Resistance
Diode Forward Voltage
Symbol
Conditions
Min
Typ
Max
Unit
Applicable Pins
(9)
Ronu
IO = 200 mA Pch
0.85
W
Rond
IO = 200 mA Nch
0.45
W
Ronu
IO = 300 mA Pch
0.85
W
Rond
IO = 300 mA Nch
0.45
W
ID = −200 mA
0.9
V
(9)
ID = −300 mA
0.9
V
(10)
VD
(10)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Applicable Pins:
(9) OUT1A, OUT1B, OUT2A, OUT2B, OUT3A, OUT3B, OUT4A, OUT4B, OUT5A, OUT5B, OUT6A, OUT6B
(10) OUT7A, OUT7B
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12
LC898201
EXAMPLE OF EXTERNAL CIRCUIT
Connection example of oscillation circuit.
XTALCK
XTAL
R1
X1
C1
C2
Please contact the manufacturer of the oscillator for an external RC.
* In the case of X’tal, it takes about 50 ms for oscillation to stabilize (please check with the manufacturer for a precise time period).
Figure 6. Example of External Circuit
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13
LC898201
AC CHARACTERISTICS
1−a) Power Supply, Reset Pin
VH_V
VH_V
DVDD
tVtoZR
ZRESET
tZRtoV
tRP
VIL
VIL
VIL
Figure 7.
1−b) Specification
DVDD:
VH_V:
VIL:
DVDD, OPDAVDD, ADVDD
2.7 V
0.15 × DVDD
Symbol
Min
The time from the rise of DVDD to the rise of ZRESET
Parameter
tVtoZR
1
ms
The time from the fall of DVDD to the fall of ZRESET
tZRtoV
500
ms
tRP
100
ms
Low period of ZRESET
Typ
Max
Unit
VM can be turn on/off regardless above power supply AC timing.
2−a) Power Supply, Reset Pin
Upper:
Lower:
“H” active Use setting of 0250h−0253h−bit2 = 0
“L” active Use setting of the above bit = 1
tVSP
VIH
VSYNC1 (or 2)
VIH
VIL
tVSINT
tVSP
VIH
VSYNC1 (or 2)
VIL
VIL
tVSINT
Figure 8.
2−b) Specification
VIH:
VIL:
0.7 × DVDD
0.2 × DVDD
Parameter
Symbol
Conditions
Min
Active period of VSYNC1(or 2)
tVSP
STMCLK = 12 MHz
100
ns
Interval time of VSYNC1(or 2)
tVSINT
2
ms
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14
Typ
Max
Unit
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TQFP64 7x7 / TQFP64
CASE 932BC
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON80202E
TQFP64 7X7 / TQFP64
DATE 31 MAY 2012
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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