LC898301AXA-MH

Ordering number : EN*A2268 LC898301AXA Advance Information CMOS LSI http://onsemi.com Liner Vibrator Driver IC Overview The LC898301AXA is a Linear Vibrator Driver IC dedicated to haptic feedback actuator and vibrator employed in mobile equipment. Due to the product superior technology, the drive frequency is automatically adjusted to the resonance frequency of the linear vibrator without the use of other external parts. As a result of this very effective drive, the vibration is as powerful as possible using very limited amount of energy compared to classical solutions. The start time and brake time are fully configurable through the I2C setting. Moreover, an automatic braking function has been implemented allowing to optimize the braking time. Finally, a self test mode allows to detect various possible functional defaults during assembly. Feature 1) Automatic adjustment to the resonance frequency for LRA (150Hz to 385Hz) 2) Programmable or Automatic braking 3) Initial drive frequency adjustment function 4) Adjustable Drive voltage through I2C IF setting 5) EN IF or PWM IF driving mode available by automatic detection 6) Support various drive pattern through I2C (1.8V IF) 7) Low power consumption thanks to the highly effective drive and the low power driving mode 8) Low driving noise (EMI, Audible band) 9) VBAT compliant 10) Thermal shutdown protection 11) Self test mode for defaults detection (open-circuit, short-circuit and weak back EMF) WLCSP8, 0.78x1.58 Applications 1) 2) 3) 4) Linear Vibrator (Vibration and haptics) Mobile Phone Portable Game Mobile equipment with haptics function 2 * I C Bus is a trademark of Philips Corporation. This document contains information on a new product. Specifications and information herein are subject to change without notice. ORDERING INFORMATION See detailed ordering and shipping information on page 12 of this data sheet. Semiconductor Components Industries, LLC, 2013 December, 2013 Ver. 3.1 D1813HK No.A2268-1/12 LC898301AXA Block Diagram VBAT RSTB EN / PWM LDO TSD OUT1 Driver Drive signal Generator Linear Vibrator OUT2 SCL SDA Register setting POR OSC VSS Fig. 1 Absolute Maximum Ratings at VSS = 0V Parameter Supply voltage range Symbol condition VDDmax Rating Unit 0.3 to 6.0 V VI1 *1 0.3 to VDD+0.3 V VI2 *2 0.3 to 3.3 V VO *3 0.3 to 3.3 V 200 mA 140 mW Ta 30 to 85 C Storage temperature range Tstg 55 to 125 C Input or Output current II,IO 20 mA Input voltage Output voltage H-bridge Drive current IOmax Allowable power dissipation PDmax Operating temperature range *1 *2 *3 *4 *5 Ta=85 C, *4 *5 RSTB pin EN,SDA,SCL pins SDA pin glass epoxy (50mm  40mm ,t=0.9mm, FR-4) Per an I/O buffer Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Recommended Operating Conditions at Ta = 30 to 85 C, VCC = 0V Parameter Supply voltage range Input voltage range Symbol condition VDD Min Typ Max Unit 3.0 - 5.5 V V V VIN1 *1 0 - VDD VIN2 *2 0 - 1.98 *1 RSTB pin *2 EN,SDA,SCL pins No.A2268-2/12 LC898301AXA Electric Characteristics DC Characteristics at VSS = 0V, VDD = 3.0 to 5.5V, Ta = 30 to +85 C Parameter High level Input voltage Low level Input voltage High level Input voltage Low level Input voltage High level Input voltage Low level Input voltage Low level output voltage Input leakage current Symbol Condition VIH VIL CMOS VIH VIL CMOS Schmitt VIH VIL CMOS Schmitt VOL IIL Min Typ Max Unit 1.40 - - V - - 0.32 V Applied pin EN 1.50 - - V - - 0.24 V 1.50 - - V - - 0.36 V IOL=4mA - - 0.4 V SDA VI =VDD,VSS 10 - +10 μA RSTB,EN SDA,SCL SDA,SCL RSTB AC Input Characteristics at VSS = 0V, VDD = 3.0 to 5.5V, Ta = 30 to +85 C Parameter Input PWM frequency Symbol Min Typ Max Unit Condition Ifrq 10.0 - 50.0 kHz 1% Fig.5 No.A2268-4/12 LC898301AXA Pin Description I/O -> I: input, O: output, B: bi-direction, P: power supply, NC: not connected Signal name I/O Function Remarks OUT1 O Motor drive pin H-bridge output OUT2 O Motor drive pin H-bridge output RSTB I Reset and Standby control L : enable, H : disable EN I Motor drive ON/OFF EN control or PWM control input 2 SCL I I C I/F clock pin SDA B I2C I/F data pin VDD P Power supply pin VSS P GND pin Open drain Package Dimensions unit :mm WLCSP8, 0.78x1.58 CASE 567HA ISSUE O E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF THE SOLDER BALLS. A B PIN A1 REFERENCE 2X 2X D 0.05 C 0.05 C DIM A A1 b D E e TOP VIEW A 0.10 C 0.08 C A1 SIDE VIEW NOTE 3 MILLIMETERS MIN MAX −−− 0.65 0.07 0.17 0.15 0.25 0.78 BSC 1.58 BSC 0.40 BSC RECOMMENDED SOLDERING FOOTPRINT* C SEATING PLANE PACKAGE OUTLINE 8X e/2 8X b 0.05 C A B 0.03 C e 0.40 PITCH e/2 e B 0.20 0.40 PITCH DIMENSIONS: MILLIMETERS A 1 2 3 4 BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. No.A2268-5/12 LC898301AXA Timing Chart Motor drive timing The EN or PWM input mode is detected automatically after RSTB pin is set to “H”. IF the input mode detection is completed, the result is maintained until RSTB is set to “L”. EN control mode The Motor is controlled by EN signal, and the driving time is controlled by keeping EN pin “H”. The High speed start UP time, driving power and Brake time can be modified by I2C setting. The initial driving frequency must be set by I2C I/F at the center of resonance frequency of the linear vibrators, when the initial driving frequency is inadequate. The minimum width of EN signal must be larger than the cycle of initial driving frequency setting. EN OUT1 OUT2 High speed Start UP Time Driving Time (Driving power is adjusted by driving voltage.) Brake Time Fig 8.1 Stand-by Control (EN control mode) The Stand-by mode is controlled by RSTB pin. (RSTB=”L”  Stand-by mode is ON.) When the stand-by mode is “ON”, the register value is set to initial value. So, the register must be set again after the stand-by mode is “OFF”. And, the “EN” signal and I2C command must wait over 200s after “RSTB” pin is set to “H”. RSTB 30ms (min) 200s EN Stand-by Driving off 2 IC Driving ON Brake Driving off Stand-by This period isn’t need, if the brake is not used. Set the registers again Fig 8.2 EN control The minimum time of EN=”H” is (1/ the frequency: RESOFRQ). ex) 0x02 RESOFRQ=0x0A (175Hz)  (min) 5.71ms EN=”L” just after EN=”H” means brake works. So the minimum time of EN=”L” depends on the remains of vibration. Then when drive time until just before EN=”L”(time of EN=”H” before EN=”L”) is over 30msec, the minimum time of EN-“L” is 30msec. When drive time until just before EN=”L”(time of EN=”H” before EN=”L”) is less than 30msec, the minimum time of EN=”L” is the same time as drive time until just before EN=”L”. (min)the same time as the last drive time when the last drive = 30msec EN (min) 1/(the frequency: RESOFRQ) Fig 8.3 No.A2268-6/12 LC898301AXA PWM control mode On this mode the motor is controlled by “PWM” signal, and it is automatically detected. The driving or brake mode is judged by the duty of “PWM” signal. Also the driving power is judged by it. The judgment rule is decided by the table as below. On this mode, 005 to 009 registers are available, and the PWM input duty is limited between1% to 99%.When the duty is 0%, the driving is stopped. Note) PWM input frequency must be set 128*(Resonance frequency of LRA) in case 008: RFSEL is set to ”0”. Note) The actual driving frequency of the LRA is calculated by Auto Tune function. Note) The period of input PWM detection is about 170s after a signal input. Duty(%) 99.00 to 50.39 50.39 to 49.62 49.62 to 1.00 Driving mode Forward Stop Reverse resolution 127 steps 127steps Note) Duty:99.0% is maximum driving, on the other hand, Duty:1.0% is maximum braking. PWM freq = 128 * (LRA Freq) in case 0x08:RFSEL=0 EN (PWM) OUT1 OUT2 Forward driving Reverse driving Fig.8.4 Stand-by Control (PWM control mode) The Stand-by mode is controlled by RSTB pin. (RSTB=”L”  Stand-by mode is ON.) When the stand-by mode is “ON”, the register value is set to initial value. So, the register must be set again after the stand-by mode is “OFF”. And, the “EN” signal and I2C command must wait over 200s after “RSTB” pin is set to “H”. RSTB (min) 200s EN PWM input Stand-by Driving off I2 C Driving ON Driving off Stand-by Set the registers again Fig 8.5 No.A2268-7/12 LC898301AXA 2 I C Serial Interface Writing format (Sequential Writing is possible) After the start condition, slave address (7bit) and “L”(Write mode) are received , the flag “ACK=L” is replied. Next, after the 8bit address is received, the flag “ACK=L” is replied. Next, after the 8bit write data is received, the flag “ACK=L” is replied. Next, when the stop condition is received, the write data can be written in the specified address. Moreover, it is possible to write data in the incremental address by the continuous input of the 8bit data confirming the flag “ACK=L” after the every 8bit write data input. START SLAVE ADDRESS L AC ADDR(N) K AC K ADDR(N) WRITE DATA AC ADDR(N+1)WRITE DATA AC K K ADDR(N+2) WRITE AC K STOP SDA SCL Fig 8.6 Reading format (Sequential Reading is possible) After the dummy writing, the start condition, slave address(7bit) and “H”(Read mode) are received, the flag “ACK=L” is replied. Next, the 8bit read data is output. After them, when the stop condition is not received, and the read condition is continued, the read data of incremental address is output one by one. The read condition is end when the end condition is received after the flag “ACK=H”. Dummy writing START SLAVE ADDRESS L AC ADDR(N) K AC K START SLAVE ADDRESS H AC K ADDR(N) READ DATA AC K *1 SDA SCL ADDR(N+1) READ DATA AC ADDR(N+2) READ DATA AC ADDR(N+3) READ DATA AC *1 K K K END SDA SCL Fig 8.7 Slave Address The Slave Address is as follows. Slave Address 1001001 No.A2268-8/12 LC898301AXA 2 AC Characteristics (I C Serial Interface) at VSS=0V, VDD=3.0 to 5.5V, Ta=30 to +85ºC Parameter SCL Clock Frequency START condition Hold time SCL clock Low width SCL clock High width RE-START condition Setup time Symbol Pin Min Typ Max Unit fSCL SCL - - 400 kHz tHD;STA SCL SDA 0.6 - - s tLOW SCL 1.3 - - s tHIGH SCL 0.6 - - s tSU;STA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA 0.6 - - s 0 - - s 0.2 - - s *1 - 0.3 s *1 - 0.3 s *1 0.6 - - s 1.3 - - s SDA Hold time tHD;DAT SDA Setup time tSU;DAT SDA, SCL Rise time SDA, SCL Fall time STOP condition Setup time STOP to START BUS open time tr tf tSU;STP tBUF comment *1) Design Assurance (Shipment test none) 90% 90% SDA 10% 10% tBUF tSU;STA tSU;DAT tLOW 90% 10% 10% 10% tHD;DAT 90% tSU;STP tHD;STA 90% 90% 90% SCL 10% tHD;STA 10% tHIGH tr 90% 90% 10% tf START CONDITION REPEATED CONDITION STOP CONDITION START CONDITION Fig 8.8 AC Characteristic (Power On Reset) at VSS=0V, VDD=3.0 to 5.5V, Ta=30 to +85ºC Parameter Symbol Min Typ Max Unit comment RSTB input timing TRSTB 1.0 - - s - 90% VDD RSTB 10% tRSTB 10% 10% tRSTB Fig 8.9 RSTB input timing chart No.A2268-9/12 LC898301AXA Application Information 1) A vibration is controlled by EN & RSTB pin. VBAT 0.1F Standby control Enable control Application Processor 2 I C IF RSTB VDD EN OUT1 OUT2 SCL SDA LRA GND 2) A vibration is controlled by PWM input RSTB pin. VBAT 0.1F Standby control PWM control Application Processor 2 I C IF RSTB VDD EN OUT1 OUT2 SCL SDA LRA GND No.A2268-10/12 LC898301AXA 3) A vibration is controlled by 0x09 ENON register. VBAT 0.1F Standby control RSTB VDD EN Application Processor Enable control OUT1 OUT2 SCL SDA LRA GND 4) A vibration is controlled by RSTB pin only. VBAT 0.1F Standby control RSTB VDD EN Application Processor 1.8V OUT1 OUT2 SCL SDA LRA GND 5) A vibration is controlled by VDD supply only. Power On Reset VDD(ON/OFF control) 0.1uF 1.8V RSTB VDD EN OUT1 OUT2 SCL SDA LRA GND No.A2268-11/12 LC898301AXA ORDERING INFORMATION Device LC898301AXA-MH Package WLCSP8, 0.78x1.58 (Pb-Free / Halogen Free) Shipping (Qty / Packing) 5000 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A2268-12/12