LE25S161XATAG

DATA SHEET www.onsemi.com Serial Flash Memory 16 Mb (2048K x 8) 8 8 LE25S161 Overview The LE25S161 is a SPI bus flash memory device with a 16 Mbit (2048K x 8−bit) configuration. It uses a single power supply. While making the most of the features inherent to a serial flash memory device, the LE25S161 is housed in an 8−pin ultra−miniature package. All these features make this device ideally suited to storing program in applications such as portable information devices, which are required to have increasingly more compact dimensions. The LE25S161 also has a small sector erase capability which makes the device ideal for storing parameters or data that have fewer rewrite cycles and conventional EEPROMs cannot handle due to insufficient capacity. Features • • • • • • • • • • • • • • • 1 1 VSOIC8 NB CASE 753AA Operations Power Supply: 1.65 to 1.95 V Supply Voltage Range Operating Frequency: 70 MHz (Max) Temperature Range: –40 to +90°C Serial Interface: SPI Mode 0, Mode 3 Supported Electronic Identification: JDEC ID, Device ID, Serial Flash Discoverable Parameter (SFDP) Sector Size: 4 kbytes/Small Sector, 64 kbytes/Sector Erase Functions: Small Sector Erase (SSE), Sector Erase (SE), Chip Erase (CHE) Page Program Function: 256 bytes/Page Status Functions: Ready/Busy Information, Protect Information Low Operation Current: 5.0 mA (Low−power Program Mode, Typ), 3.5 mA (Low−Power Read Mode, Typ) Erase Time: 10 ms (SSE, Typ), 15 ms (SE, Typ), 210 ms (CHE, Typ) Page Program Time (tPP): 0.4 ms/256 bytes (Typ.), 0.7 ms/256 bytes (Max.) Emergency Shutdown of the Current Consumption: Transition to a Standby State in Less than 20 ms from the Active by Write Suspend Transition to a Standby State in Less than 40 ms from the Active by Software Reset High Reliability: 100,000 Erase/Program Cycles 20 Years Data Retention Period Package: LE25S161FDTWG VSOIC8 NB, CASE 753AA LE25S161MDTWG SOIC 8, 150 mils, CASE 751BD LE25S161PCTXG UDFN8 4 x 3, 0.8P, CASE 506DC LE25S161XBTAG WLCSP8, 2.92 x 1.53, CASE 567YR KGD SOIC 8 CASE 751BD ÇÇÇ ÇÇ ÇÇ 1 UDFN8 CASE 506DC WLCSP8 CASE 567YR MARKING DIAGRAM 5S161 00 ALYW 5S16100 A L Y W = Specific Device Code = Assembly Site = Wafer Lot Number = Year of Production = Work Week ORDERING INFORMATION Device Package Shipping† LE25S161FDTWG VSOIC8 NB (Pb−Free / Halide Free) 3000 / Tape & Reel LE25S161MDTWG SOIC8 (Pb−Free / Halide Free) 2000 / Tape & Reel LE25S161PCTXG UDFN8 (Pb−Free / Halide Free) 2000 / Tape & Reel LE25S161XBTAG WLCSP8 (Pb−Free / Halide Free) 4000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *This product is licensed from Silicon Storage Technology, Inc. (USA). © Semiconductor Components Industries, LLC, 2016 February, 2022 − Rev. 2 1 Publication Order Number: LE25S161/D LE25S161 PACKAGE TYPES AND PIN CONFIGURATIONS (Top View) (Top View) CS 1 8 VDD CS 1 8 VDD SO (SIO1) 2 7 HOLD SO (SIO1) 2 7 HOLD WP 3 6 SCK WP 3 6 SCK VSS 4 5 SI (SIO0) VSS 4 5 SI (SIO0) Figure 1. SOIC8 (LE25S161MDTWG) and VSOIC8 NB (LE25S161FDTWG) Figure 2. UDFN8 (LE25S161PCTXG) (Top View) (Ball Side View) A VDD CS B HOLD C D CS VDD A SO/SIO1 SO/ SIO1 HOLD B SCK WP WP SCK C SI/SIO0 VSS VSS SI/ SIO0 D 1 2 2 1 Figure 3. WLCSP8 (LE25S161XBTAG) Table 1. PIN CONFIGURATION Pad No. Name A2 CS B2 SO (SIO1) C2 WP D2 VSS D1 SI (SIO0) C1 SCK B1 HOLD A1 VDD www.onsemi.com 2 LE25S161 4 3 2 1 5 6 7 8 Figure 4. KGD Table 2. PIN CONFIGURATION Pad No. Name 1 CS 2 SO (SIO1) 3 WP 4 VSS 5 SI (SIO0) 6 SCK 7 HOLD 8 VDD PIN DESCRIPTION Table 3. PIN DESCRIPTION ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Symbol Pin Name IIO Description CS Chip Select I The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. SCK Serial Clock I This pin controls the data input/output timing. The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. SI (SIO0) Serial Data Input (Serial Data Input Output) I/O The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the serial clock. (It changes into input/output pin during the Dual operation.) SO (SIO1) Serial Data Output (Serial Data Input Output) I/O The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. (It changes into input/output pin during the Dual operation.) WP Write Protect I The Write Status Register Protect (SRWP) takes effect when the logic level of this pin is low. HOLD Hold I Serial communication is suspended when the logic level of this pin is low. VDD Power Supply VSS Ground ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ This pin supplies the 1.65 to 1.95 V supply voltage. This pin supplies the 0 V supply voltage. www.onsemi.com 3 LE25S161 BLOCK DIAGRAM Energy− consumption Control Unit 16 MBit Flash EEPROM Cell Array Power Circuit Memory Control Logic Decoder Logic & Serial−parallel Conversion Logic Command Logic Serial Interface CS SCK SO (SIO1) SI (SIO0) Figure 5. Block Diagram www.onsemi.com 4 WP HOLD LE25S161 DEVICE OPERATION Standard SPI Modes taken into the device interior in synchronization with the rising edge of SCK, which causes the device to execute operation according to the command that is input. The LE25S161 supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK is high. The read, erase, program and other required functions of the device are executed through the command registers. The serial I/O corrugate is shown in “Figure 6. SPI Modes” and the command list are shown in “Table 5. Command Settings (Standard SPI)”. At the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8 bit units and CS Mode3 SCK Mode0 8CLK SI 1st byte MSB (Bit7) SO Nth byte 2nd byte LSB (Bit0) High Impedance DATA DATA Figure 6. SPI Modes Dual SPI Modes Table 4. PIN CONFIGURATIONS AT DUAL SPI MODE The LE25S161 supports Dual SPI operations when using “Dual Output Read (RDDO: 3Bh)”, “Dual I/O Read (RDIO: BBh)”. The SI and SO pins change into the input/output pin (SIOx) during the Dual SPI modes. The command list is shown in “Table 6. Command Settings (Dual SPI)”. Standard SPI www.onsemi.com 5 Dual SPI SI → SIO0 SO → SIO1 LE25S161 Table 5. COMMAND SETTINGS (STANDARD SPI) − MAX: 70 MHz (EXCEPT RDLP) Command 1st Byte (0−7) WREN Write Enable 06h 2nd Byte (8−15) 3rd Byte (16−23) 4th Byte (24−31) 5th Byte (32−39) 6th Byte (40−47) Nth Byte (8N−8 to 8N−1) WRDI Write Disable 04h RDSR Read Status Register 05h WRSR Write Status Register 01h DATA RDLP Low−Power Read (Max: 33.33 MHz) 03h A23−A16 A15−A8 A7−A0 RD (Note 5) RD (Note 5) RD (Note 5) RDHS High−Speed Read 0Bh A23−A16 A15−A8 A7−A0 X RD (Note 5) RD (Note 5) PD (Note 6) PD (Note 6) PD (Note 6) SSE 20h / D7h A23−A16 A15−A8 A7−A0 SE Sector Erase (64 kB) D8h A23−A16 A15−A8 A7−A0 CHE Chip Erase (16 Mbits) 60h / C7h PP Normal Page Program 02h A23−A16 A15−A8 A7−A0 PPL Low−Power Page Program 0Ah WSUS Write Suspend B0h RESM Small Sector Erase (4 kB) Resume 30h RJID Read JEDEC ID 9Fh Manufacture (62h) Memory Type (16h) Capacity (15h) RID Read Device ID (Exit power down mode) ABh X X X Device ID (88h) Read SFDP 5Ah A23−A16 A15−A8 A7−A0 X RD (Note 5) RD (Note 5) Deep Power Down B9h EDP Exit Deep Power Down ABh RSTEN Reset Enable 66h Reset 99h RSFDP DP RST 1. 2. 3. 4. 5. 6. Description (Clock Number) “X” signifies “don’t care” (that is to say, any value may be input). “Z” signifies “high−impedance”. The “h” following each code indicates that the number given is in hexadecimal notation. Addresses A23 to A21 for all commands are “Don’t care”. “RD” Read data on SO. “PD” Page Program data on SO. Table 6. COMMAND SETTINGS (DUAL SPI) − MAX: 50 MHz Command Description (Clock Number) 1st Byte (0−7) 2nd Byte (8−15) 3rd Byte (16−23) 4th Byte (24−31) 5th Byte (32−39) 6th Byte (40−47) Nth Byte (8N−8 to 8N−1) RDDO Dual Output Read 3Bh A23−A16 A15−A8 A7−A0 Z RDD (Note 11) RDD (Note 11) RDIO Dual I/O Read BBh A23−A8 (Note 12) A7−A0 (Note 12), X, Z RDD (Note 11) RDD (Note 11) RDD (Note 11) RDD (Note 11) 7. “X” signifies “don’t care” (that is to say, any value may be input). 8. “Z” signifies “high−impedance”. 9. The “h” following each code indicates that the number given is in hexadecimal notation. 10. Addresses A23 to A21 for all commands are “Don’t care”. 11. “RDD” Dual Read data: SIO0 = (Bit6, Bit4, Bit2, Bit0) SIO1 = (Bit7, Bit5, Bit3, Bit1) 12. Dual SPI address input from SIO0 and SIO1: SIO0 = (A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0) SIO1 = (A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1) www.onsemi.com 6 LE25S161 MEMORY ORGANIZATION Table 7. MEMORY ORGANIZATION (16 Mbits) Sector (64 kB) Symbol: SE Small Sector (4 kB) Symbol: SSE 31 SSE[511] Address Space (A23 to A0) 1FF000h 1FFFFFh to 30 to 6 SSE[496] 1F0000h 1F0FFFh SSE[495] 1EF000h 1EFFFFh SSE[96] 060000h 060FFFh SSE[95] 05F000h 05FFFFh to 5 to 4 SSE[80] 050000h 050FFFh SSE[79] 04F000h 04FFFFh SSE[64] 040000h 040FFFh SSE[63] 03F000h 03FFFFh SSE[48] 030000h 030FFFh SSE[47] 02F000h 02FFFFh SSE[32] 020000h 020FFFh SSE[31] 01F000h 01FFFFh SSE[16] 010000h 010FFFh SSE[15] 00F000h 00FFFFh SSE[4] 004000h 004FFFh SSE[3] 003800h 003FFFh 003000h 0037FFh 002800h 002FFFh to 3 to 2 to 1 to 0 to SSE[2] SSE[1] SSE[0] www.onsemi.com 7 002000h 0027FFh 001800h 001FFFh 001000h 0017FFh 000800h 000FFFh 000000h 0007FFh LE25S161 STATUS REGISTERS The status registers hold the operating and setting statuses inside the device, and this information can be read by Read Status Register (RDSR) and the protect information can be rewritten by Write Status Register (WRSR). There are 8 bits in total, and “Table 8. Status registers” gives the significance of each bit. Table 8. STATUS REGISTERS Bit Name Logic Function Power−on Time Information Bit0 RDY 0 Ready 3 1 Erase/Program 0 Write disabled 1 Write enabled 0 Block protect information Protected area switch Nonvolatile information Block protect Upper side/Lower side switch Nonvolatile information 0 Erase/Program is not suspended 0 1 Erase/Program suspended 0 Write Status Register enabled 1 Write Status Register disabled Bit1 Bit2 WEN BP0 1 Bit3 BP1 0 0 1 Bit4 BP2 0 1 Bit5 TB 0 1 Bit6 Bit7 SUS SRWP Nonvolatile information 13. All non−volatile bits of the status registers−1 are set “0” in the factory. • Upon completion of Page Program (PP or PPL) • Upon completion of Write Status Register (WRSR) Contents of Each Status Register RDY (Bit 0) The RDY register is for detecting the write (Program, Erase and Write Status Register) end. When it is “1”, the device is in a busy state, and when it is “0”, it means that write is completed. *If a write operation has not been performed inside the LE25S161 because, for instance, the command input for any of the write operations (SSE, SE, CHE, PP, PPL or WRSR) has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation. WEN (Bit 1) The WEN register is for detecting whether the device can perform write operations. If it is set to “0”, the device will not perform the write operation even if the write command is input. If it is set to “1”, the device can perform write operations in any area that is not block−protected. WEN can be controlled using the write enable (WREN) and write disable (WRDI). By inputting the write enable (WREN: 06h), WEN can be set to “1” by inputting the write disable (WRDI: 04h), it can be set to “0.” In the following states, WEN is automatically set to “0” in order to protect against unintentional writing. • At power−on • Upon completion of Erase (SSE, SE, or CHE) BP0, BP1, BP2, TB (Bits 2, 3, 4, 5) Block Protect: BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to “Table 9. Protected Level Setting Conditions”. BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher−order address area or lower−order address area. www.onsemi.com 8 LE25S161 Table 9. PROTECTION LEVEL SETTING CONDITIONS Status Register Bits Protected Level Protected Block TB BP2 BP1 BP0 Protected Area 0 Whole area unprotected X 0 0 0 None T1 Upper side 1/32 protected 0 0 0 1 1F0000h to 1FFFFFh T2 Upper side 1/16 protected 0 0 1 0 1E0000h to 1FFFFFh T3 Upper side 1/8 protected 0 0 1 1 1C0000h to 1FFFFFh T4 Upper side 1/4 protected 0 1 0 0 180000h to 1FFFFFh T5 Upper side 1/2 protected 0 1 0 1 100000h to 1FFFFFh B1 Lower side 1/32 protected 1 0 0 1 000000h to 00FFFFh B2 Lower side 1/16 protected 1 0 1 0 000000h to 01FFFFh B3 Lower side 1/8 protected 1 0 1 1 000000h to 03FFFFh B4 Lower side 1/4 protected 1 1 0 0 000000h to 07FFFFh B5 Lower side 1/2 protected 1 1 0 1 000000h to 0FFFFFh 6 Whole area protected X 1 1 X 000000h to 1FFFFFh 14. Chip Erase is enabled only when the protection level is 0. are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in “Table 10. SRWP Setting Conditions”. SUS (Bit 6) The SUS register indicates when Erase/Program operation has been suspended. The SUS becomes “1” when the Erase/Program operation has been suspended (WSUS: B0h). The SUS is cleared to “0” by Resume (RESM: 30h) or re−erase/program (SSE, SE, CHE, PP, PPL). Table 10. SRWP SETTING CONDITIONS SRWP (Bit 7) Write Status Register protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is “1” and the logic level of the WP pin is low, the Write Status Register (WRSR: 01h) is ignored, and status registers BP0, BP1, BP2, TB and SRWP WP Pin SRWP Status Register Protect State 0 0 Unprotected 1 Protected 0 Unprotected 1 Unprotected 1 www.onsemi.com 9 LE25S161 DESCRIPTION OF COMMANDS AND OPERATIONS → Status Register data (SRWP, SUS, TB, BP2, BP1, BP0,WEN, RDY) out on SO →→ → completed by CS = high *The data output starts from the falling edge of SCK (7th clock) This command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK). If the clock input is continued after bit0 (RDY) has been output, the data is output by returning to bit7 (SRWP) that was first output, after which the output is repeated for as long as the clock input is continued. The data can be read by this command at any time (even during a program, erase cycle). By setting CS to high, the device is deselected, and Read JEDEC ID cycle is completed. While the device is deselected, the output pin SO is in a high−impedance state A detailed description of the functions and operations corresponding to each command is presented below. Read Status Register (RDSR) The contents of the status registers can be read using the Read Status Register (RDSR). This command can be executed even during the following operations. • Erase (SSE, SE or CHE) • Page Program (PP or PPL) • Write Status Register (WRSR) “Figure 7. Read Status Register (RDSR)” shows the timing waveforms. The sequence of RDSR operation: CS goes to low → input RDSR command (05h) CS Mode 3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 Mode 0 8CLK SI 05h MSB SO • High Impedance DATA MSB DATA: Status Resister, “Table 8. Status Register” Figure 7. Read Status Register (RDSR) www.onsemi.com 10 DATA MSB DATA MSB LE25S161 Write Status Register (WRSR) “Figure 8. Write Status Register (WRSR)” shows the timing waveforms. “Figure 37. Write Status Register Flowcharts” shows the flowcharts. The sequence of WRSR operation: CS goes to low → input WRSR command (01h) → Status Register data input on SI → CS goes to high (be executed by the rising CS edge) The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using this command. bit0 (RDY), bit1 (WEN) and bit6 (SUS) are read−only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, TB and SRWP is stored in the non−volatile memory, and when it is written in these bits, the contents are retained even at power−down. Self−timed Write Cycle t WRSR CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 Mode0 8CLK SI 01h DATA MSB High Impedance SO Figure 8. Write Status Register (WRSR) Write Enable (WREN) Write Disable (WRDI) Before performing any of the operations listed below, the device must be placed in the write enable state. • Erase (SSE, SE, CHE or CHE) • Page Program (PP or PPL) • Write Status Register (WRSR) Operation is the same as for setting status register WEN to “1”, and the state is enabled by this command. “Figure 9. Write Enable (WREN)” shows the timing waveforms. The sequence of WREN operation: CS goes to low → input WREN command (06h) → CS goes to high (be executed by the rising CS edge) This command sets status register WEN to “0” to prohibit unintentional writing. The write disable state (WEN “0”) is exited by setting WEN to “1” using the write enable (WREN: 06h). “Figure 10. Write Disable (WRDI)” shows the timing waveforms. The sequence of WRDI operation: CS goes to low → input WRDI command (04h) → CS goes to high (be executed by the rising CS edge) CS Mode3 SCK CS Mode3 SCK 8CLK 0 1 2 3 4 5 6 7 SI Mode0 SI 04h MSB 8CLK 06h SO High Impedance Figure 10. Write Disable (WRDI) MSB SO 0 1 2 3 4 5 6 7 Mode0 High Impedance Figure 9. Write Enable (WREN) www.onsemi.com 11 LE25S161 Standard SPI Read → completed by CS = high *The data output starts from the falling edge of SCK (31th clock) The Address is latched on rising edge of SCK, and the corresponding data is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data is shifted out. If the SCK input is continued after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected, the output pin SO is in a high−impedance state. There are two Read commands, “Low−Power Read (RDLP: 03h)” and “High−Speed Read (RDHS: 0Bh)”. Low−Power Read command (RDLP) − Maximum Clock Frequency: 33.33 MHz This command is for reading data out. “Figure 11. Low−Power Read (RDLP)” shows the timing waveforms. The sequence of RDLP operation: CS goes to low → input RDLP command (03h) → 3 Byte address (A23 − A0) input on SI → the corresponding data out on SO → continuous data out (n−byte) →→ CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 Mode0 8CLK SI Add 03h Add (A7−A0) High Impedance SO • Add (A23−A16) (A15−A8) Byte 1 DATA MSB Address A23 to A21 are “Don’t care”. Figure 11. Low−Power Read (RDLP) www.onsemi.com 12 Byte 2 DATA MSB Byte 3 DATA MSB LE25S161 The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the corresponding data is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data is shifted out. If the SCK input is continued after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected, the output pin SO is in a high−impedance state. High−Speed Read Command (RDHS) − Maximum Clock frequency: 70 MHz This command is for reading data out at the high frequency operation. “Figure 12. High−Speed Read (RDHS)” shows the timing waveforms. The sequence of RDHS operation: CS goes to low → input RDHS command (0Bh) → 3 Byte address (A23 − A0) input on SI → 1 byte dummy cycle → the corresponding data out on SO → continuous data out (n−byte) →→ → completed by CS = high *The data output starts from the falling edge of SCK(39th clock) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 Mode0 8CLK SI Add 0Bh Add (A23−A16) (A15−A8) Add (A7−A0) MSB • Byte 1 High Impedance SO X DATA MSB Address A23 to A21 are “Don’t care”. Byte 2 DATA MSB Byte 3 DATA MSB Figure 12. High−Speed Read (RDHS) → 1 byte dummy cycle → the corresponding data out on SI/SIO0 and SO/SIO1 → continuous data out (n−byte) per 4 clock →→ → completed by CS = high *The data output starts from the falling edge of SCK (39th clock) Output Data SI/SIO0 bit6, 4, 2, 0 SO/SIO1 bit7, 5, 3, 1 The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the corresponding data is shifted out on SI/SIO0 and SO/SIO1 by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data (4 clock cycles) is shifted out. If the SCK input is continued after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected, the output pin SO is in a high−impedance state. Dual Read There are two Dual read commands, the Dual Output Read (RDDO) and the Dual I/O Read (RDIO). They achieve the twice speed−up from ”High−Speed Read (RDHS: 0Bh)”. The command list is shown in “Table 6. Command Settings (Dual SPI)” Table 11. PIN CONFIGURATIONS AT DUAL SPI MODE Standard SPI Dual SPI SI → SIO0 SO → SIO1 Dual Output Read Command (RDDO) − Maximum Clock Frequency: 50 MHz The SI and SO pins change into the input/output pin (SIOx) during this operation. It makes the data output x2 bit and has achieved a high−speed output. bit7, 5, 3 and bit1are output from SIO0. bit6, 4, 2 and bit0 are output from SIO1. “Figure 13. Dual Output Read (RDDO)” shows the timing waveforms. The sequence of RDDO operation: CS goes to low → input RDDO command (3Bh) → 3 Byte address (A23 − A0) input on SI www.onsemi.com 13 LE25S161 CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 43 44 8CLK Add 3Bh SIO0 Add (A23−A16) (A15−A8) Add (A7−A0) Byte 1 dummy bit MSB Byte 2 Byte 3 DATA0 DATA0 DATA0 4CLK High Impedance SIO1 4CLK DATA1 DATA1 DATA1 MSB • 47 Mode0 MSB MSB DATA0: bit6, bit4, bit2, bit0 DATA1: dit7, bit5, bit3, bit1 Address A23 to A21 are “Don’t care”. Figure 13. Dual Output Read (RDDO) → continuous data out (n−byte) per 4 clock →→ → completed by CS = high *The data output starts from the falling edge of SCK (23th clock) Input Address Output Data SI/SIO0 A22, 20, 18 −, A2, A0 bit6, 4, 2, 0 SO/SIO1 A23, 21, 19 −, A3, A1 bit7, 5, 3, 1 The Address is latched on rising edge of SCK. It is necessary to add 4 dummy clocks after address is latched, 2CLK of the latter half of the dummy clock is in the state of high impedance, the controller can switch I/O for this period. The corresponding data is shifted out on SI/SIO0 and SO/SIO1 by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte data (4 clock cycles) is shifted out. If the SCK input is continued after the internal address arrives at the highest address (1FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device is deselected, and the read cycle is completed. While the device is deselected, the output pin SO is in a high−impedance state. Dual I/O Read Command (RDIO) − Maximum Clock Frequency: 50 MHz The SI and SO pins change into the input/output pin (SIOx) during this operation. It makes the address input and data output x2 bit and has achieved a high−speed output. Add1 (A23, A21, −, A3 and A1) is input from SIO1 and Add0 (A22, A20, −, A2 and A0) is input from SIO0. bit7, 5, 3 and bit1 are output from SIO0. bit6, 4, 2 and bit0 are output from SIO1. “Figure 14. Dual I/O Read (RDIO)” shows the timing waveforms. The sequence of RDIO operation: CS goes to low → input RDIO command (BBh) → 3 Byte address (A23 − A0) input on SI/SIO0 and SO/SIO1 by 12 clock cycle → 2 dummy clock (SI/SIO0 and SO/SIO1 are don’t care) + 2 dummy clock (must set SI/SIO0 and SO/SIO1 high impedance) → the corresponding data out on SI/SIO0 and SO/SIO CS Mode3 SCK 0 1 2 3 4 5 6 7 8 19 20 21 22 23 24 BBh SIO0 dummy bit X Add1: A22, A20−A2, A0 MSB 12CLK High Impedance Byte2 Byte3 DATA0 DATA0 DATA0 Byte 1 4CLK 2CLK 2CLK Add2: A23, A21−A3, A1 X DATA1 DATA1 DATA1 MSB • 31 Mode0 8CLK SIO1 27 28 MSB MSB DATA0: bit6, bit4, bit2, bit0 DATA1: dit7, bit5, bit3, bit1 Address A23 to A21 are “Don’t care”. Figure 14. Dual I/O Read (RDIO) www.onsemi.com 14 LE25S161 CS goes to low → input SSE command (20h or D7h) → 3 Byte address (A23 − A0) input on SI → CS goes to high (be executed by the rising CS edge) *A20 to A12 are valid address After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tSSE). The end of erase operation can also be detected by status register (RDY). Small Sector Erase (SSE) Small Sector Erase is an operation that sets the memory cell data in any small sector to “1”. A small sector consists of 4 kbytes. “Figure 15. Small Sector Erase (SSE)” shows the timing waveforms. “Figure 38. Small Sector Erase Flowcharts” shows the flowcharts. The sequence of SSE operation: Self−timed Erase Cycle t SSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 Mode0 8CLK SI 20h / D7h Add Add (A23−A16) (A15−A8) Add (A7−A0) MSB High Impedance SO • Address A23 to A21, A11 to A0 are “Don’t care”. Figure 15. Small Sector Erase (SSE) CS goes to low → input SE command (D8h) → 3 Byte address (A23 − A0) input on SI → CS goes to high (be executed by the rising CS edge) *A20 to A16 are valid address After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tSE). The end of erase operation can also be detected by status register (RDY). Sector Erase (SE) Sector Erase is an operation that sets the memory cell data in any sector to “1”. A sector consists of 64 kbytes. “Figure 16. Sector Erase (SE)” shows the timing waveforms. “Figure 39. Sector Erase Flowcharts” shows the flowcharts. The sequence of SE operation: Self−timed Erase Cycle t SE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 Mode0 8CLK SI D8h Add Add (A23−A16) (A15−A8) Add (A7−A0) MSB SO • High Impedance Address A23 to A21, A15 to A0 are “Don’t care”. Figure 16. Sector Erase (SE) www.onsemi.com 15 LE25S161 CS goes to low → input CHE command (60h or C7h) → CS goes to high (be executed by the rising CS edge) After the correct input sequence the internal erase operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tSE). The end of erase operation can also be detected by status register (RDY). Chip Erase (CHE) Chip Erase is an operation that sets the memory cell data in all sectors to “1”. “Figure 17. Chip Erase (CHE)” shows the timing waveforms. “Figure 40. Chip Erase Flowcharts” shows the flowcharts The sequence of CHE operation: Self−timed Erase Cycle t CHE CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI 60h / C7h MSB SO High Impedance Figure 17. Chip Erase (CHE) Page Program “Figure 41. Page Program Flowcharts” shows the flowcharts. The sequence of PP or PPL operation: CS goes to low → input PP command (02h) or PPL command (0Ah) → 3 Byte address (A23 − A0) input on SI → n−Byte data input on SI →→ → CS goes to high (be executed by the rising CS edge) The program data must be loaded in 1−byte increments. If the data loaded has exceeded 256 bytes, the 256 bytes loaded last are programmed. After the correct input sequence the internal program operation is executed by the rising CS edge, and it is completed automatically by the control exercised by the internal timer (tPP or tPPL). The end of program operation can also be detected by status register (RDY). Normal Page Program (PP) Low−Power Page Program (PPL) There are two Page Program commands, Normal program (PP: 02h ) and Low−Power program (PPL: 0Ah). These two commands are completely functionally the same. By selecting the Low−Power program (PPL), the operating current is reduced, but the program cycle time is extended. (Iccpp > Iccppl, tPPL > tPP) Page Program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page addresses: A20 to A8). Before initiating Page Program, the data on the page concerned must be erased using Small Sector Erase, Sector Erase, or Chip Erase. Page Program (PP, PPL) allows only previous erased data (FFh). “Figure 18. Normal Page Program (PP)”. “Figure 19. Low−power Page Program (PPL)” shows the timing waveforms. www.onsemi.com 16 LE25S161 Self−timed Program Cycle t PP CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 2079 Mode0 8CLK SI 02h Byte 1 Add Add (A23−A16) (A15−A8) Add (A7−A0) PD Byte 2 PD Byte 256 PD MSB High Impedance SO • Address A23 to A21, A15 to A0 are “Don’t care”. Figure 18. Normal Page Program (PP) Self−timed Program Cycle t PPL CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 2079 Mode0 8CLK SI 0Ah Byte 1 Add Add (A23−A16) (A15−A8) Add (A7−A0) PD Byte 2 PD Byte 256 PD MSB SO • High Impedance Address A23 to A21, A15 to A0 are “Don’t care”. Figure 19. Low−Power Page Program (PPL) Write Suspend (WSUS) checked by using status register RDY bit or SUS bit, but the device will not accept another command until it is ready. • The Write Suspend is valid Erase cycle (SSE, SE and CHE) or Program cycle (PP, PPL). • If the Erase (SSE, SE, CHE) or Program (PP, PPL) entry during the suspension, the suspension will be canceled automatically. And a new Erase (SSE, SE, CHE), Program (PP, PPL) will be executed. In this case, it is necessary to erase/program the suspended area again. • During Write Suspend, Read (RDSR, RDLP, RDHS, RDDO, RDIO) and Resume (RESM) can be accepted. • If the Software Reset is executed during the suspension, the suspension will be canceled automatically. The Write Suspend (WSUS) allow the system to interrupt Small Sector Erase (SSE), Sector Erase (SE), Chip Erase (CHE) or Page Program (PP, PPL). “Figure 20. Write Suspend (WSUS)” shows the timing waveforms. The sequence of WSUS operation: CS goes to low → input WSUS command (B0h) → CS goes to high (be executed by the rising CS edge) After the command has been input, the device becomes consumption current equivalent to standby within 20 ms. The recovery time (tRSUS) is needed before next command from suspend. The internal operation status could be www.onsemi.com 17 LE25S161 t RSUS CS Mode3 SCK 20 ms 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Mode0 8CLK SI Next Command (Read or Resume) MSB B0h MSB High Impedance SO Operation Current = Isb Figure 20. Write Suspend (WSUS) Resume (RESM) The internal operation status could be checked by using status register RDY bit or SUS bit. This command will be ignored if the previous Write Suspend operation was interrupted by unexpected power off or re−erase/program (cancel of suspend) or Software Reset (RST). To execute Write Suspend (WSUS) again after Resume, it is necessary to wait for some time (tSUS). This command (RESM) restarts erase cycle (SSE, SE, CHE) or program cycle (PP, PPL) that was suspended. “Figure 21. Resume (RESM)” shows the timing waveforms. The sequence of RESM operation: CS goes to low → input RESM command (30h) → CS goes to high (be executed by the rising CS edge) Self−timed Write Cycle tCHE / tSE / tSSE / tPP / tPPL CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI 30h MSB SO High Impedance Figure 21. Resume (RESM) Read ID “Figure 22. Read JEDEC ID (RJID)” shows the timing waveforms. The sequence of RJID operation: CS goes to low → input RJID command (9Fh) → Manufacture code (62h) out on SO → Memory type code (16h) out on SO → Memory capacity code out on SO (15h) → Reserve code (00h) →→ → completed by CS = high Read ID is an operation that reads the manufacturer code (RJID) and device ID information (RID). These Read ID commands are not accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a device ID. Read JEDEC ID (RJID) This command (RJID) is compatible with the JEDEC standard for SPI compatible serial memories. “Table 12. JEDEC ID codes” lists the silicon ID codes. www.onsemi.com 18 LE25S161 *The 4−byte code is output repeatedly as long as clock inputs are present *The data output starts from the falling edge of SCK (7th clock) By setting CS to high, the device is deselected, and Read JEDEC ID cycle is completed. While the device is deselected, the output pin SO is in a high−impedance state. Table 12. JEDEC ID CODES Output Code Manufacturer code 2 byte device ID 62h Memory type 16h Memory capacity code 15h (16 MBit) Reserve code 00h CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 31 32 23 24 39 Mode0 8CLK SI 9Fh High Impedance SO 62h MSB 16h MSB 00h 15h MSB MSB 62h MSB Figure 22. Read JEDEC ID (RJID) → completed by CS = high *The Device ID (88h) is output repeatedly as long as clock inputs are present *The data output starts from the falling edge of SCK (31th) By setting CS to high, the device is deselected, and Read ID cycle is completed. While the device is deselected, the output pin SO is in a high−impedance state. Read Device ID (RID) This command (RID) is an operation that reads the Device ID. “Table 13. Device ID Code” lists the device ID codes. “Figure 23. Read Device ID (RID)” shows the timing waveforms. The sequence of RID operation: CS goes to low → input RID command (ABh) → 3 byte dummy cycle → Device ID (88h) out on SO →→ Table 13. DEVICE ID CODE Output Code 1 byte device ID 88h (LE25S161) CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 Mode0 8CLK SI SO X ABh X High Impedance X 88h MSB Figure 23. Read Device ID (RID) www.onsemi.com 19 88h MSB LE25S161 CS goes to low → input DP command (B9h) → CS goes to high (be executed by the rising CS edge) The deep power−down command issued during an internal write operation will be ignored. The deep power−down state is exited using the deep power−down exit (EDP). All other commands are ignored. Deep Power−down (DP) The standby current can be further reduced with this command (DP). “Figure 24. Deep Power−down (DP)” shows the timing waveforms. The sequence of DP operation: Standby current (Isb) Deep Power−down Standby Current (Idsb) CS t DP Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK B9h SI MSB High Impedance SO Figure 24. Deep Power−down (DP) Exit Deep Power−down (EDP) / Read Device ID (RDDI) “Figure 25. Exiting from Deep Power−down” shows the timing waveforms. The sequence of EDP operation: CS goes to low → input EDP command (ABh) → CS goes to high (be executed by the rising CS edge) The Exit Deep Power−down (EDP) / Read Device ID (RID) command is a multi−purpose command. It can be used to exit the device from the deep power−down state, or read the device ID information. Exit Deep Power−down (EDP) The exit deep power−down command consists only of the first byte cycle, and it is initiated by inputting (ABh). Deep Power−down Standby current (Idsb) Standby current (Isb) CS t RDP Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI ABh MSB SO High Impedance Figure 25. Exiting from Deep Power−down (EDP) www.onsemi.com 20 LE25S161 → Device ID out on SO →→ → completed by CS = high *The Device ID is output repeatedly as long as clock inputs are present *The data output starts from the falling edge of SCK (31th clock) By setting CS to high, the device is deselected, and Read ID cycle is completed. While the device is deselected, the output pin SO is in a high−impedance state. Read Device ID (RDDI) Also the exit from deep power−down is completed by one byte cycle or more of the Read Device ID (RID: ABh). “Table 13. Device ID Code” lists the device ID codes. “Figure 26. Read Device ID” shows the timing waveforms. The sequence of EDP & RID operation: CS goes to low → input RID command (ABh) → 3 byte dummy cycle Standby current (Isb) Deep Power−down Standby current (Idsb) CS t RDP Mode3 SCK 31 32 0 1 2 3 4 5 6 7 8 39 Mode0 24 Dummy Bits 8CL SI ABh X X High Impedance SO Dev ID Dev ID Dev ID MSB Figure 26. Read Device ID Software Reset When the Software Reset is executed, an internal write (erase/program) operation is cancel, a suspended status is reset, and all volatility status register bits (WEN/RDY/SUS) are reset. After the internal reset time (tRST), the device will become stand−by state. If the Software Reset is executed during a write (erase/program) operation, any dates on the write operation will be broken. The Reset command must input just after input the Reset Enable command. If another command input after the Reset Enable command, the Reset−Enable state will be invalid. The Software Reset reset the device to the state just after power−on. This operation consists of two commands: the Reset Enable (RSTEN) and the Reset command (RST). “Figure 27. Software Reset” shows the timing waveforms. The sequence of Software Reset operation: CS goes to low → input RSTEN command (66h) → CS goes to high → CS goes to low → input RST command (99h) → CS goes to high (be executed by the rising CS edge) Internal reset time (tRST) CS Mode3 SCK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8CLK 8CLK 66h 99h Mode0 SI MSB SO MSB High Impedance Figure 27. Software Reset www.onsemi.com 21 LE25S161 → 1 byte dummy cycle the corresponding parameter out on SO → continuous parameter out (n−byte) →→ → completed by CS = high *A10 to A0 are valid address *The parameter output starts from the falling edge of SCK (39th clock) The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the corresponding parameter is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next higher address after each byte parameter is shifted out. By setting CS to high, the device is deselected, and Read SFDP cycle is completed. While the device is deselected, the output pin SO is in a high−impedance state. Read SFDP (RSFDP) The Read SFDP (Serial Flash Discoverable Parameter) is an operation that reads the parameter about device configurations, available commands and other features. The SFDP parameters are stored in internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. SFDP is a standard of JEDEC. JESD216. Rev 1.0. “Table 14. SFDP Header” shows SFDP Header. “Table 15. SFDP Parameter Table” shows SFDP Parameter Table. “Figure 28. Read SFDP (RSFDP)” shows the timing waveforms. The sequence of RSFDP operation: CS goes to low → input RSFDP command (5Ah) → 3 Byte address (A23 − A0) input on SI CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 Mode0 8CLK SI 5Ah Add Add (A23−A16) (A15−A8) Add (A7−A0) MSB SO High Impedance X Byte 1 MSB Figure 28. Read SFDP (RSFDP) www.onsemi.com 22 Byte 2 Byte 3 Param1 Param2 Param3 MSB MSB LE25S161 Table 14. SFDP HEADER Description Comment Byte Address (Hex) Bits Data (Hex) 00h 7:0 53h 01h 15:8 46h 02h 23:16 44h 03h 31:24 50h SFDP HEADER 1st AND 2nd DWORD SFDP Signature 50444653h (SFDP) SFDP Minor Revision Number Start from 00h 04h 7:0 05h SFDP Major Revision Number Start from 01h 05h 15:8 01h Number of Parameter Headers 02h indicates 3 parameters 06h 23:16 02h 07h 31:24 FFh Unused 1st PARAMETER HEADER (JDEC BASIC FLASH PARAMETERS) ID Number (JEDEC ID) 00h (JEDEC specified header) 08h 7:0 00h Parameter Table Minor Revision Number Start from 00h 09h 15:8 00h Parameter Table Major Revision Number Start from 01h 0Ah 23:16 01h Parameter Table Length (in Double Word) How many DWORDs in the Parameter table 10h indicates 16 DWORDs 0Bh 31:24 10h Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table 0Ch 7:0 40h 0Dh 15:8 00h 0Eh 23:16 00h 0Fh 31:24 FFh 10h 7:0 62h Unused 2nd PARAMETER HEADER (VENDER PARAMETERS 1) ID Number (onsemi Manufacturer ID) 62h (ON Semiconductor manufacturer ID) Parameter Table Minor Revision Number Start from 00h 11h 15:8 00h Parameter Table Major Revision Number Start from 01h 12h 23:16 01h Parameter Table Length (in Double Word) How many DWORDs in the Parameter table 04h indicates 4 DWORDs 13h 31:24 04h Parameter Table Pointer (PTP) First address of On Semiconductor Parameter table 14h 7:0 C0h 15h 15:8 00h 16h 23:16 00h 17h 31:24 FFh Unused www.onsemi.com 23 LE25S161 Table 15. SFDP PARAMETER TABLE Description Comment Byte Address (Hex) Bits Data (Binary) Data (Hex) 40h 1:0 01b E5h JDEC Basic Flash Parameter Tables (from 1st DWORD TO 4th DWORD) Block/Sector Erase Sizes 00b: Reserved 01b: support 4 kB Erase 10b: Reserved 11b: not support 4 kB Erase Write Granularity 0: 1 Byte, 1:64 Byte or larger 2 1b Volatile Status Register Block Protect Bits 0: Non−volatile 1: Volatile 3 0b Write Enable Instruction Select for Writing to Volatile Status Register 0: use 50h opcode, 1: use 06h opcode NOTE: If target flash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 4 0b Unused Contains 111b and can never be changed 7:5 111b 4 kB Erase Instruction 20h 41h 15:8 0010_0000b 20h (1−1−2) Fast Read 0 = not support 1 = support 42h 16 1b 91h Address Bytes 00: 3 Byte only, 01: 3 or 4 Byte, 10: 4 Byte only, 11: Reserved 18:17 00b Double Transfer Rate (DTR) Clocking 0 = not support 1 = support 19 0b (1−2−2) Fast Read 0 = not support 1 = support 20 1b (1−4−4) Fast Read 0 = not support 1 = support 21 0b (1−1−4) Fast Read 0 = not support 1 = support 22 0b 23 1b 43h 31:24 1111_1111b FFh Unused Unused Flash Memory Density 16 M bits 44h 45h 46h 47h 31:0 − 00FFFFFFh (1−4−4) Fast Read Number of Wait States (Dummy Clocks) 0 0000b: Wait states (dummy Clocks) not support 48h 4:0 0_0000b 00h (1−4−4) Fast Read Number of Mode Clocks 000b: Mode Bits not support 7:5 000b 49h 15:8 1111_1111b FFh 4Ah 20:16 0_0000b 00h 23:21 000b 4Bh 31:24 1111_1111b FFh 4Ch 4:0 0_1000b 08h 7:5 000b 4Dh 15:8 0011_1011b 3Bh 4Eh 20:16 0_0100b 04h 23:21 000b 31:24 1011_1011b (1−4−4) Fast Read Instruction (1−1−4) Fast Read Number of Wait States (Dummy Clocks) 0 0000b: Wait states (dummy Clocks) not support (1−1−4) Fast Read Number of Mode Clocks 000b: Mode Bits not support (1−1−4) Fast Read Instruction (1−1−2) Fast Read Number of Wait States (Dummy Clocks) 0 0000b: Wait states (dummy Clocks) not support (1−1−2) Fast Read Number of Mode Clocks 000b: Mode Bits not support (1−1−2) Fast Read Instruction (1−2−2) Fast Read Number of Wait States (Dummy Clocks) 0 0000b: Wait states (dummy Clocks) not support (1−2−2) Fast Read Number of Mode Clocks 000b: Mode Bits not support (1−2−2) Fast Read Instruction 4Fh www.onsemi.com 24 BBh LE25S161 Table 15. SFDP PARAMETER TABLE (continued) Description Comment Byte Address (Hex) Bits Data (Binary) Data (Hex) 50h 0 0b EEh 3:1 111b 4 0b 7:5 111b JDEC BASIC FLASH PARAMETER TABLES (FROM 5th DWORD TO 8th DWORD) (2−2−2) Fast Read 0 = not support 1 = support Reserved Default all 1’s (4−4−4) Fast Read 0 = not support 1 = support Reserved Default all 1’s Reserved Default all 1’s 51h 52h 53h 31:8 − FFh FFh FFh Reserved Default all 1’s 54h 55h 15:0 − FFh FFh (2−2−2) Fast Read Number of Wait states (Dummy Clocks) 0 0000b: Wait states (dummy Clocks) not support 56h 20:16 0_0000b 00h (2−2−2) Fast Read Number of Mode Clocks 000b: Mode Bits not support 23:21 000b 57h 31:24 1111_1111b FFh (2−2−2) Fast Read Instruction Reserved Default all 1’s 58h 59h 15:0 − FFh FFh (4−4−4) Fast Read Number of Wait States (Dummy Clocks) 0 0000b: Wait states (dummy Clocks) not support 5Ah 20:16 0_0000b 00h (4−4−4) Fast Read Number of Mode Clocks 000b: Mode Bits not support 23:21 000b 5Bh 31:24 1111_1111b FFh 5Ch 7:0 0000_1100b 0Ch 5Dh 15:8 0010_0000b 20h 5Eh 23:16 0001_0000b 10h 5Fh 31:24 1101_1000b D8h 60h 7:0 0000_0000b 00h 61h 15:8 1111_1111b FFh 62h 23:16 0000_0000b 00h 63h 31:24 1111_1111b FFh 64h 3:0 0100b 94h 10:4 00_01001b (4−4−4) Fast Read Instruction Sector Type 1 Size Sector/block size = 2^N bytes 0Ch indicates 4 kbytes Sector Type 1 Erase Instruction Sector Type 2 Size Sector/block size = 2^N bytes 10h indicates 64 kbytes Sector Type 2 Erase Instruction JDEC BASIC FLASH PARAMETER TABLES (FROM 9th DWORD TO 12th DWORD) Sector Type 3 Size Sector/block size = 2^N bytes 00h indicates not exist Sector Type 3 Erase Instruction Sector Type 4 Size Sector/block size = 2^N bytes 00h indicates not exist Sector Type 4 Erase Instruction Multiplier from Typical Erase Time to Maximum Erase Time SE (64 k−Byte erase): 150 ms = 2 x (n + 1) x 15 ms n=4 Sector Type 1 Erase, Typical Time SSE (4 k−Byte erase) 10 ms: ((n + 1) x 1 ms = 10 ms) n=9 Sector Type 2 Erase, Typical Time SE (64 k−Byte erase) 15 ms: ((n + 1) x 1 ms = 15 ms) n = 14 Sector Type 3 Erase, Typical Time − Sector Type 4 Erase, Typical Time − 65h 17:11 25 00_01110b 66h 67h www.onsemi.com 70h 00h 24:18 00_00000b 31:25 00_00000b 00h LE25S161 Table 15. SFDP PARAMETER TABLE (continued) Description Comment Byte Address (Hex) Bits Data (Binary) Data (Hex) 68h 3:0 0010b 82h 7:4 1000b 13:8 1_00110b 15:14 1_1111b JDEC BASIC FLASH PARAMETER TABLES (FROM 9th DWORD TO 12th DWORD) Multiplier from Typical Time to Max Time for Page or Byte Program (n + 1) x 0.3 ms = 0.9 ms: n = 2, 0.9 ms > 0.7 ms (spec) Page Size 256 Bytes =2^8 Page Program Typical Time (n + 1) x 64 ms = 448 ms: n = 6, 448 ms > 400 ms (spec) Byte Program Typical Time, First Byte (n + 1) x 8 ms = 128 ms: n = 15 69h 6Ah 07h 18:16 Byte Program Typical Time, Additional Byte (count + 1) x 1 ms/byte = 1 ms/byte: Count = 0 Chip Erase, Typical Time (n + 1) x 16 ms = 208 ms: n = 12, 208 ms = 210 ms (spec) Reserved − Prohibited Operations During Program Suspend xxx0b: May not initiate a new erase anywhere xxx1b: May not initiate a new erase in the program suspended page size xx0xb: May not initiate a new page program anywhere xx1xb: May not initiate a new page program in the program suspended page size x0xxb: Refer to vendor datasheet for read restrictions x1xxb: May not initiate a read in the program suspended page size 0xxxb: Additional erase or program restrictions apply 1xxxb: The erase and program restrictions in bits 1:0 are sufficient Prohibited Operations During Erase Suspend xxx0b: May not initiate a new erase anywhere xxx1b: May not initiate a new erase in the erase suspended sector size xx0xb: May not initiate a page program anywhere xx1xb: May not initiate a page program in the erase suspended sector size x0xxb: Refer to vendor datasheet for read restrictions x1xxb: May not initiate a read in the erase suspended sector size 0xxxb: Additional erase or program restrictions apply 1xxxb: The erase and program restrictions in bits 5:4 are sufficient Reserved − Program Resume to Suspend Interval