LM301ADR2G

LM301A, LM201A, LM201AV Operational Amplifiers, NonCompensated, Single A general purpose operational amplifier that allows the user to choose the compensation capacitor best suited to his needs. With proper compensation, summing amplifier slew rates to 10 V/ms can be obtained. http://onsemi.com Features MARKING DIAGRAMS • Low Input Offset Current: 20 nA Maximum Over Temperature • • • • • Range External Frequency Compensation for Flexibility Class AB Output Provides Excellent Linearity Output Short Circuit Protection Guaranteed Drift Characteristics Pb−Free Packages are Available 8 LMx01AN AWL YYWWG PDIP−8 N SUFFIX CASE 626 8 1 1 VEE Inverting Input 8 VCC NonInverting Input Output 1 + 1 5.1 MW 30 pF 10 MW 8 Balance Freq Compen Balance 20 k LM201AVDR2G 8 VEE 1 Figure 1. Standard Compensation and Offset Balancing Circuit VUT SOIC−8 D SUFFIX CASE 751 x A WL, L YY, Y WW, W G G VCC LMx01 ALYWA G 201AV ALYW G = 2 or 3 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package = Pb−Free Package + VO VI PIN CONNECTIONS MZ4622 or Equiv. VEE VCC 3.9 V Balance Inputs VO VLT VEE VEE VO = 4.8 V for VLT ≤ VI ≤ VUT VO = -0.4 V VI < VLT or VI > VUT 1 8 Compensation 2 7 VCC 3 6 Output 4 5 Balance (Top View) (Pins Not Shown Are Not Connected) Figure 2. Double−Ended Limit Detector ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2011 December, 2011 − Rev. 11 1 Publication Order Number: LM301A/D LM301A, LM201A, LM201AV Balance Compensation VCC Inputs + 500 25 Output 50 450 40k 5k 20 k 250 40k 10 k 80 k 1.0 k VEE Balance Figure 3. Representative Circuit Schematic ORDERING INFORMATION Package Shipping† LM301ADG SOIC−8 (Pb−Free) 98 Units/Rail LM301ADR2G SOIC−8 (Pb−Free) 2500 Tape & Reel PDIP−8 50 Units/Rail LM301ANG PDIP−8 (Pb−Free) 50 Units/Rail LM201ADG SOIC−8 (Pb−Free) 98 Units/Rail LM201ADR2G SOIC−8 (Pb−Free) 2500 Tape & Reel Device LM301AN LM201AN PDIP−8 50 Units/Rail LM201ANG PDIP−8 (Pb−Free) 50 Units/Rail LM201AVDR2G SOIC−8 (Pb−Free) 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 LM301A, LM201A, LM201AV MAXIMUM RATINGS Value Rating Power Supply Voltage Symbol LM201A LM201AV LM301A Unit VCC, VEE ±22 ±22 ±18 Vdc Input Differential Voltage VID ±30 V Input Common Mode Range (Note 1) VICR ±15 V Output Short Circuit Duration tSC Continuous Power Dissipation (Package Limitation) PD Plastic Dual−In−Line Package 625 625 625 mW Derate above TA = +25°C 5.0 5.0 5.0 mW/°C −40 to +105 0 to +70 °C Operating Ambient Temperature Range TA Storage Temperature Range Tstg −25 to +85 −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = +25°C, unless otherwise noted.) Unless otherwise specified, these specifications apply for supply voltages from ± 5.0 V to ± 20 V for the LM201A and LM201AV, and from ± 5.0 V to ±15 V for the LM301A. LM201A / LM201AV LM301A Symbol Min Typ Max Min Typ Max Unit Input Offset Voltage (RS ≤ 50 kW) VIO − 0.7 2.0 − 2.0 7.5 mV Input Offset Current IIO − 1.5 10 − 3.0 50 nA Input Bias Current IIB − 30 75 − 70 250 nA Input Resistance ri 1.5 4.0 − 0.5 2.0 − MW − − 1.8 − 3.0 − − − − 1.8 − 3.0 50 160 − 25 160 − V/mV − 3.0 − − 10 mV Characteristic Supply Current VCC/VEE = ± 20 V VCC/VEE = ±15 V Large Signal Voltage Gain (VCC/VEE = ±15 V, VO = ±10 V, RL > 2.0 kW) ICC,IEE AV mA The following specifications apply over the operating temperature range. Input Offset Voltage (RS ≤ 50 kW) Input Offset Current VIO − IIO − − 20 − − 70 nA Avg Temperature Coefficient of Input Offset Voltage (Note 2) TA(min) ≤ TA ≤ TA (max) DVIO/DT − 3.0 15 − 6.0 30 mV/°C Avg Temperature Coefficient of Input Offset Current (Note 2) +25°C ≤ TA ≤ TA (max) TA(min) ≤ TA ≤ 25°C DIIO/DT nA/°C − − 0.01 0.02 0.1 0.2 − − 0.01 0.02 0.3 0.6 IIB − − 100 − − 300 nA Large Signal Voltage Gain (VCC/VEE = ±15 V, VO = ±10V, RL > 2.0 kW) AVOL 25 − − 15 − − V/mV Input Voltage Range VCC/VEE = ± 20 V VCC/VEE = ±15 V VICR −15 − − − +15 − − −12 − − − +12 Common Mode Rejection (RS ≤ 50 kW) CMR 80 96 − 70 90 − dB Supply Voltage Rejection (RS ≤ 50 kW) PSR 80 96 − 70 96 − dB VO ±12 ±10 ±14 ±13 − − ±12 ±10 ±14 ±13 − − V ICC,IEE − 1.2 2.5 − − − mA Input Bias Current Output Voltage Swing (VCC/VEE = ±15 V, RL = ±10 kW, RL > 2.0 kW) Supply Currents (TA = TA(max), VCC/VEE = ± 20 V) V 1. For supply voltages less than ±15 V, the absolute maximum input voltage is equal to the supply voltage. 2. Guaranteed by design. http://onsemi.com 3 LM301A, LM201A, LM201AV Applicable to the Specified Operating Temperature Ranges 16 VOR, OUTPUT VOLTAGE RANGE ( ±V) VIR , INPUT VOLTAGE RANGE (V) 20 12 LM201A only Positive 8.0 Negative 4.0 0 0 5.0 10 15 VCC, ( -VEE), SUPPLY VOLTAGE (V) 20 Applicable to the Specified Operating Temperature Ranges 16 12 Minimum RL = 10 k 8.0 Minimum RL = 2.0 k 4.0 0 20 0 Figure 4. Minimum Input Voltage Range 5.0 10 15 VCC, ( -VEE), SUPPLY VOLTAGE (V) 20 Figure 5. Minimum Output Voltage Swing 100 2.5 I CC , I EE , SUPPLY CURRENTS (mA) Applicable to the Specified Operating Temperature Ranges 94 A V , VOLTAGE GAIN (dB) LM201A only 88 LM201A only 82 76 2.0 1.5 5.0 10 15 TA = +25°C 0.5 70 0 LM201A only 1.0 0 20 0 5.0 10 15 VCC, ( -VEE), SUPPLY VOLTAGE (V) VCC, ( -VEE), SUPPLY VOLTAGE (V) Figure 6. Minimum Voltage Gain Figure 7. Typical Supply Currents 20 Single-Pole Compensation A V , VOLTAGE GAIN (dB) 160 140 315 120 270 100 80 C1 = 3.0 pF 225 Phase 180 60 135 C1 = 30 pF 40 20 0 -20 1.0 90 0 10 100 1.0 k 10 k 100 k 1.0 M Single-Pole Compensation 15 10 C1 = 3.0 pF 5.0 45 Gain VOR, OUTPUT VOLTAGE RANGE ( ±V) 180 C1 = 30 pF 0 1.0 k 10 M 10 k 100 k 1.0 M 10 M f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 8. Open Loop Frequency Response Figure 9. Large Signal Frequency Response http://onsemi.com 4 LM301A, LM201A, LM201AV 140 8.0 6.0 4.0 2.0 Input 0 -2.0 Output -4.0 -6.0 100 225 80 180 Phase 60 135 40 90 20 45 Gain 0 0 0 -8.0 -10 0 10 20 30 40 50 60 70 80 -20 10 90 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M t, TIME (ms) f, FREQUENCY (Hz) Figure 10. Voltage Follower Pulse Response Figure 11. Open Loop Frequency Response 10 VOR, OUTPUT VOLTAGE RANGE ( ±V) 18 VOR, OUTPUT VOLTAGE RANGE ( ±V) Feedforward Compensation 120 PHASE LAG (DEGREES) Single-Pole Compensation A V, VOLTAGE GAIN (dB) VIR , VOR, VOLTAGE RANGE ( ±V) 10 Feedforward Compensation 16 12 8.0 4.0 0 100 k Feedforward Compensation 8.0 Output 6.0 4.0 2.0 Input 0 -2.0 -4.0 -6.0 -8.0 -10 1.0 M f, FREQUENCY (Hz) 10 M 0 Figure 12. Large Signal Frequency Response 1.0 2.0 3.0 4.0 5.0 t, TIME (ms) 6.0 7.0 8.0 Figure 13. Inverter Pulse Response C2 R2 R1 -VI R2 VCC 2 R1 6 R3 +VI 7 3 VI VO C1 C1 ≥ 4 + 8 Frequency Compensation 1 R3 R1 Cs R1 +R2 C1 150 pF Cs = 30 pF VCC 6 3 + 4 1 VEE Balance 7 2 VO VEE Balance C2 = 1 2πfoR2 fo = 3.0 MHz Figure 14. Single−Pole Compensation Figure 15. Feedforward Compensation http://onsemi.com 5 9.0 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−8 CASE 626−05 ISSUE P DATE 22 APR 2015 SCALE 1:1 D A E H 8 5 E1 1 4 NOTE 8 b2 c B END VIEW TOP VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L SEATING PLANE A1 C D1 M e 8X SIDE VIEW b 0.010 eB END VIEW M C A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.355 0.400 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 9.02 10.16 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° NOTE 6 GENERIC MARKING DIAGRAM* STYLE 1: PIN 1. AC IN 2. DC + IN 3. DC − IN 4. AC IN 5. GROUND 6. OUTPUT 7. AUXILIARY 8. VCC XXXXXXXXX AWL YYWWG XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98ASB42420B PDIP−8 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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