LM317M, NCV317MA,
NCV317M
Voltage Regulator Adjustable Output, Positive
500 mA
The LM317M is an adjustable three−terminal positive voltage
regulator capable of supplying in excess of 500 mA over an output
voltage range of 1.2 V to 37 V. This voltage regulator is exceptionally
easy to use and requires only two external resistors to set the output
voltage. Further, it employs internal current limiting, thermal
shutdown and safe area compensation, making it essentially blow−out
proof.
The LM317M serves a wide variety of applications including local,
on−card regulation. This device also makes an especially simple
adjustable switching regulator, a programmable output regulator, or by
connecting a fixed resistor between the adjustment and output, the
LM317M can be used as a precision current regulator.
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Heatsink surface
connected to Pin 2
TO−220AB
T SUFFIX
CASE 221AB
1
Features
•
•
•
•
•
•
•
•
•
Output Current in Excess of 500 mA
Output Adjustable between 1.2 V and 37 V
Internal Thermal Overload Protection
Internal Short Circuit Current Limiting
Output Transistor Safe−Area Compensation
Floating Operation for High Voltage Applications
Eliminates Stocking Many Fixed Voltages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
Vin
Vin
Vout
2
SOT−223
ST SUFFIX
CASE 318E
1
3
2
3
4
DPAK
DT SUFFIX
CASE 369C
1 2
3
Heatsink Surface (shown as terminal 4 in
case outline drawing) is connected to Pin 2.
Vout
LM317M
PIN ASSIGNMENT
R1
240
*
Cin
0.1mF
IAdj
Adjust
**
+C
O
1.0mF
1
Adjust
2
Vout
3
Vin
R2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
* = Cin is required if regulator is located an appreciable distance from power supply filter.
** = CO is not needed for stability, however, it does improve transient response.
R
Vout + 1.25Vǒ1 ) 2Ǔ ) IAdjR2
R1
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 11 of this data sheet.
Since IAdj is controlled to less than 100 mA, the error associated with this
term is negligible in most applications.
Figure 1. Simplified Application
© Semiconductor Components Industries, LLC, 2014
October, 2019 − Rev. 26
1
Publication Order Number:
LM317M/D
LM317M, NCV317MA, NCV317M
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Input−Output Voltage Differential
Power Dissipation (Package Limitation) (Note 1)
Plastic Package, T Suffix, Case 221A
TA = 25°C
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
Plastic Package, DT Suffix, Case 369C
TA = 25°C
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
Plastic Package, ST Suffix, Case 318E
TA = 25°C
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
Maximum Junction Temperature
Storage Temperature Range
Symbol
Value
Unit
VI−VO
40
Vdc
PD
qJA
qJC
Internally Limited
70
5.0
°C/W
°C/W
PD
qJA
qJC
Internally Limited
92
5.0
°C/W
°C/W
PD
qJA
qJC
Internally Limited
245
15
°C/W
°C/W
TJMAX
+150
°C
Tstg
−65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Figure 25 provides thermal resistance versus PC board pad size.
ELECTRICAL CHARACTERISTICS (VI − VO = 5.0 V; IO = 0.1 A, TJ = Tlow to Thigh (Note 2), unless otherwise noted.)
LM317M/LM317MB/NCV317MB
Figure
Symbol
Min
Typ
Max
Unit
Line Regulation (Note 3) (TA = 25°C, 3.0 V ≤ VI − VO ≤ 40 V)
3
Regline
−
0.01
0.04
%/V
Load Regulation (Note 3)
TA = 25°C, 10 mA ≤ IO ≤ 0.5 A
VO ≤ 5.0 V
VO ≥ 5.0 V
4
Regload
−
−
5.0
0.1
25
0.5
mV
% VO
Adjustment Pin Current
5
IAdj
−
50
100
mA
Adjustment Pin Current Change
2.5 V ≤ VI − VO ≤ 40 V, 10 mA ≤ IL ≤ 0.5 A, PD ≤ Pmax
3, 4
DIAdj
−
0.2
5.0
mA
Reference Voltage
3.0 V ≤ VI − VO ≤ 40 V, 10 mA ≤ IL ≤ 0.5 A, PD ≤ Pmax
5
Vref
1.20
1.25
1.30
V
Line Regulation 3.0 V ≤ VI−VO ≤ 40 V (Note 3)
3
Regline
−
0.02
0.07
%/V
Load Regulation 10 mA ≤ IO ≤ 0.5 A (Note 3)
VO ≤ 5.0 V
VO ≥ 5.0 V
4
Regload
−
−
20
0.3
70
1.5
mV
% VO
Temperature Stability (Tlow ≤ TJ ≤ Thigh)
5
TS
−
0.7
−
% VO
Minimum Load Current to Maintain Regulation (VI − VO = 40 V)
5
ILmin
−
3.5
10
mA
Maximum Output Current
VI − VO ≤ 15 V, PD ≤ Pmax
VI − VO = 40 V, PD ≤ Pmax, TA = 25°C
5
Imax
0.5
0.15
0.9
0.25
−
−
RMS Noise, % of VO (TA = 25°C, 10 Hz ≤ f ≤ 10 kHz)
−
N
−
0.003
−
Ripple Rejection, VO = 10 V, f = 120 Hz (Note 4)
Without CAdj
CAdj = 10 mF
6
RR
−
66
65
80
−
−
Thermal Shutdown (Note 5)
−
−
−
180
−
°C
Long−Term Stability, TJ = Thigh (Note 6)
TA= 25°C for End−point Measurements
5
S
−
0.3
1.0
%/1.0
kHrs.
Characteristics
A
% VO
dB
2. Tlow to Thigh = 0° to +125°C for LM317M
Tlow to Thigh = −40° to +125°C for LM317MB, NCV317MB.
3. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account
separately. Pulse testing with low duty cycle is used.
4. CAdj, when used, is connected between the adjustment pin and ground.
5. Thermal characteristics are not subject to production test.
6. Since Long−Term Stability cannot be measured on each device before shipment, this specification is an engineering estimate of average
stability from lot−to−lot.
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2
LM317M, NCV317MA, NCV317M
ELECTRICAL CHARACTERISTICS (VI − VO = 5.0 V; IO = 0.1 A, TJ = Tlow to Thigh (Note 7), unless otherwise noted.)
Characteristics
Figure
Symbol
Line Regulation (Note 8) (TA = 25°C, 3.0 V ≤ VI − VO ≤ 40 V)
3
Regline
Load Regulation (Note 8)
TA = 25°C, 10 mA ≤ IO ≤ 0.5 A
VO ≤ 5.0 V
VO ≥ 5.0 V
4
Regload
Adjustment Pin Current
5
Adjustment Pin Current Change
2.5 V ≤ VI − VO ≤ 40 V, 10 mA ≤ IL ≤ 0.5 A, PD ≤ Pmax
LM317MA/LM317MAB/NCV317MAB
Min
Typ
Max
Unit
−
0.01
0.04
%/V
−
−
5.0
0.1
25
0.5
mV
% VO
IAdj
−
50
100
mA
3, 4
DIAdj
−
0.2
5.0
mA
Reference Voltage
3.0 V ≤ VI − VO ≤ 40 V, 10 mA ≤ IL ≤ 0.5 A, PD ≤ Pmax
5
Vref
1.225
1.250
1.275
V
Line Regulation (Note 8)
3.0 V ≤ VI−VO ≤ 40 V
3
Regline
−
0.02
0.07
%/V
Load Regulation (Note 8)
10 mA ≤ IO ≤ 0.5 A
VO ≤ 5.0 V
VO ≥ 5.0 V
4
Regload
−
−
20
0.3
70
1.5
mV
% VO
Temperature Stability (Tlow ≤ TJ ≤ Thigh)
5
TS
−
0.7
−
% VO
Minimum Load Current to Maintain Regulation (VI − VO = 40 V)
5
ILmin
−
3.5
10
mA
Maximum Output Current
VI − VO ≤ 15 V, PD ≤ Pmax
VI − VO = 40 V, PD ≤ Pmax, TA = 25°C
5
Imax
0.5
0.15
0.9
0.25
−
−
RMS Noise, % of VO (TA = 25°C, 10 Hz ≤ f ≤ 10 kHz)
−
N
−
−
−
Ripple Rejection, VO = 10 V, f = 120 Hz (Note 9)
Without CAdj
CAdj = 10 mF
6
RR
−
66
65
80
−
−
Thermal Shutdown (Note 10)
−
−
−
180
−
°C
Long−Term Stability, TJ = Thigh (Note 11)
TA= 25°C for End−point Measurements
5
S
−
0.3
1.0
%/1.0
kHrs.
A
% VO
dB
7. Tlow to Thigh = 0° to +125°C for LM317MA
Tlow to Thigh = −40° to +125°C for LM317MAB, NCV317MAB.
8. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account
separately. Pulse testing with low duty cycle is used.
9. CAdj, when used, is connected between the adjustment pin and ground.
10. Thermal characteristics are not subject to production test.
11. Since Long−Term Stability cannot be measured on each device before shipment, this specification is an engineering estimate of average
stability from lot−to−lot.
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3
LM317M, NCV317MA, NCV317M
Vin
300
300
300
3.0k
300
70
6.8V
6.8V
350
18k
8.67k
500
130
400
5.1k
200k
6.3V
180
180
2.0k
6.0k
60
10
pF 10
pF
1.25
Vout
2.4k
12.8k
50
Adjust
Figure 2. Representative Schematic Diagram
VCC
VOH - VOL
VOL
Line Regulation (%/V) =
*
VIH
VIL
VOH
VOL
Vout
Vin
x 100
LM317M
Adjust
Cin
*Pulse Testing Required:
1% Duty Cycle is suggested.
0.1mF
R1
240
1%
RL
+
CO
IAdj
1.0mF
R2
1%
Figure 3. Line Regulation and DIAdj/Line Test Circuit
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4
LM317M, NCV317MA, NCV317M
Load Regulation (mV) = VO (min Load) -VO (max Load)
VO (min Load) - VO (max Load)
Load Regulation (% VO) =
VO (min Load)
Vin
Vin
Vout
LM317M
Adjust
X 100
VO (min Load)
VO (max Load)
IL
R1
RL
(max Load)
240
1%
RL
(min Load)
*
+
Cin
0.1mF
CO
IAdj
1.0mF
R2
1%
*Pulse Testing Required:
1% Duty Cycle is suggested.
Figure 4. Load Regulation and DIAdj/Load Test Circuit
Vin
Vout
LM317M
IL
Adjust
240
1%
R1
VI
IAdj
Cin
Vref
RL
+
CO
0.1mF
1mF
VO
ISET
R2
1%
To Calculate R2:
Vout = ISET R2 + 1.250 V
Assume ISET = 5.25 mA
*Pulse Testing Required:
1% Duty Cycle is suggested.
Figure 5. Standard Test Circuit
24V
Vout
Vin
14V
f = 120 Hz
Vout = 10 V
LM317M
Adjust
Cin
240
1%
R1
D1 *
1N4002
CO
0.1mF
R2
1.65K
1%
**
CAdj
RL
+
1.0mF
+
10mF
*D1 Discharges CAdj if Output is Shorted to Ground.
**CAdj provides an AC ground to the adjust pin.
Figure 6. Ripple Rejection Test Circuit
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5
VO
LM317M, NCV317MA, NCV317M
0.4
Vin = 45 V
Vout = 5.0 V
IL = 5.0 mA to 40 mA
0.2
RR, RIPPLE REJECTION (dB)
Δ V out , OUTPUT VOLTAGE CHANGE (%)
90
0
-0.2
Vin = 10 V
Vout = 5.0 V
IL = 5.0 mA to 100 mA
-0.4
-0.6
-0.8
80
Without CAdj = 10 mF
70
50
-1.0
-50
-25
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
-50
150
-25
Figure 7. Load Regulation
V in -Vout , INPUT-OUTPUT VOLTAGE
DIFFERENTIAL (V)
Iout , OUTPUT CURRENT (A)
0.80
0.60
TJ = 25°C
0.40
TJ = 125°C
150
2.5
IL = 500 mA
2.0
IL = 100 mA
1.5
1.0
0.5
0
0
10
20
30
40
Vin-Vout, INPUT-OUTPUT VOLTAGE DIFFERENTIAL (V)
50
-50
Figure 9. Current Limit
5.0
100
4.5
90
4.0
3.5
3.0
TJ = 25°C
2.5
TJ = 125°C
2.0
-25
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
150
Figure 10. Dropout Voltage
RR, RIPPLE REJECTION (dB)
IB , QUIESCENT CURRENT (mA)
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Ripple Rejection
1.0
0.20
Without CAdj
IL = 100 mA
f = 120 Hz
Vout = 10 V
Vin = 14 V to 24 V
60
1.5
1.0
IL = 40 mA
Vin = 5.0 V ± 1.0 VPP
Vout = 1.25 V
80
70
60
50
40
30
20
10
0.5
0
10
20
30
40
Vin-Vout, INPUT-OUTPUT VOLTAGE DIFFERENTIAL (Vdc)
10
Figure 11. Minimum Operating Current
100
1.0 k
10 k
100 k 1.0 M
f, FREQUENCY (Hz)
Figure 12. Ripple Rejection versus Frequency
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LM317M, NCV317MA, NCV317M
1.250
1.240
Vin = 4.2 V
Vout = Vref
IL = 5.0 mA
1.230
80
IAdj, ADJUSTMENT PIN CURRENT ( μA)
Vref, REFERENCE VOLTAGE (V)
1.260
Vin = 6.25 V
Vout = Vref
IL = 10 mA
IL = 100 mA
70
65
60
55
50
45
40
35
1.220
-50
-25
0
25
50
75 100 125
TJ, JUNCTION TEMPERATURE (°C)
-50
150
NOISE VOLTAGE ( μV)
Δ Vout , OUTPUT VOLTAGE CHANGE (%)
75
100
125
150
Bandwidth 100 Hz to 10 kHz
0
-0.2
-0.4
-0.6
8.0
6.0
-0.8
4.0
-50
-25
0
25
50
75 100 125
TJ, JUNCTION TEMPERATURE (°C)
150
-50
Δ Vout , OUTPUT VOLTAGE
DEVIATION (V)
CL = 1.0 mF
3.0
I L , LOAD
CURRENT (A)
1.0
25
50
75
100
1.5
1.0
Vout = 10 V
IL = 50 mA
TJ = 25°C
-1.5
CL = 1.0 mF; CAdj = 10 mF
Vin = 15 V
Vout = 10 V
INL = 50 mA
TJ = 25°C
CL = 0
1.0
Vin
0
10
CL = 0.3 mF; CAdj = 10 mF
-3.0
0.5
20
t, TIME (ms)
150
0
-2.0
-0.5
-1.0
125
2.0
-1.0
0
0
0
Figure 16. Output Noise
1.5
0.5
-25
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Line Regulation
Δ Vout , OUTPUT VOLTAGE
DEVIATION (V)
50
10
-1.0
Δ Vin , INPUT VOLTAGE
CHANGE (V)
25
Figure 14. Adjustment Pin Current
Vin = 4.25 V to 41.25 V
Vout = Vref
IL = 5.0 mA
0.2
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Temperature Stability
0.4
-25
30
40
1.0
IL
0.5
0
0
10
20
t, TIME (ms)
30
Figure 18. Load Transient Response
Figure 17. Line Transient Response
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7
40
LM317M, NCV317MA, NCV317M
APPLICATIONS INFORMATION
Basic Circuit Operation
External Capacitors
The LM317M is a three−terminal floating regulator. In
operation, the LM317M develops and maintains a nominal
1.25 V reference (Vref) between its output and adjustment
terminals. This reference voltage is converted to a
programming current (IPROG) by R1 (see Figure 19), and this
constant current flows through R2 to ground. The regulated
output voltage is given by:
A 0.1 mF disc or 1.0 mF tantalum input bypass capacitor
(Cin) is recommended to reduce the sensitivity to input line
impedance.
The adjustment terminal may be bypassed to ground to
improve ripple rejection. This capacitor (CAdj) prevents
ripple from being amplified as the output voltage is
increased. A 10 mF capacitor should improve ripple
rejection about 15 dB at 120 Hz in a 10 V application.
Although the LM317M is stable with no output
capacitance, like any feedback circuit, certain values of
external capacitance can cause excessive ringing. An output
capacitance (CO) in the form of a 1.0 mF tantalum or 25 mF
aluminum electrolytic capacitor on the output swamps this
effect and insures stability.
ǒ
Ǔ
R
Vout + Vref 1 ) 2 ) IAdj R2
R1
Since the current from the terminal (IAdj) represents an
error term in the equation, the LM317M was designed to
control IAdj to less than 100 mA and keep it constant. To do
this, all quiescent operating current is returned to the output
terminal. This imposes the requirement for a minimum load
current. If the load current is less than this minimum, the
output voltage will rise.
Since the LM317M is a floating regulator, it is only the
voltage differential across the circuit which is important to
performance, and operation at high voltages with respect to
ground is possible.
Protection Diodes
When external capacitors are used with any IC regulator
it is sometimes necessary to add protection diodes to prevent
the capacitors from discharging through low current points
into the regulator.
Figure 20 shows the LM317M with the recommended
protection diodes for output voltages in excess of 25 V or
high capacitance values (CO > 25 mF, CAdj > 5.0 mF). Diode
D1 prevents CO from discharging thru the IC during an input
short circuit. Diode D2 protects against capacitor CAdj
discharging through the IC during an output short circuit.
The combination of diodes D1 and D2 prevents CAdj from
discharging through the IC during an input short circuit.
Vout
Vin
LM317M
+
R1
Vref
Adjust
IPROG
Vout
IAdj
D1
R2
1N4002
Vin
Vref = 1.25 V Typical
Vout
Vout
LM317M
+
Figure 19. Basic Circuit Configuration
Cin
R1
D2
Adjust
Load Regulation
The LM317M is capable of providing extremely good
load regulation, but a few precautions are needed to obtain
maximum performance. For best performance, the
programming resistor (R1) should be connected as close to
the regulator as possible to minimize line drops which
effectively appear in series with the reference, thereby
degrading regulation. The ground end of R2 can be returned
near the load ground to provide remote ground sensing and
improve load regulation.
1N4002
R2
CAdj
Figure 20. Voltage Regulator with
Protection Diodes
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8
CO
LM317M, NCV317MA, NCV317M
+25V
Vout
1.25k
Vin
Adjust
D1
D1
1N914
R2
500
* To provide current limiting of IO
to the system ground, the source of
the current limiting diode must be tied to
a negative voltage below -7.25 V.
1N4002
Vin
Vout
LM317M
+
1.0mF
120
Adjust
1N5314
MPS2222
TTL
Control
720
1.0k
VSS*
Vref
IOmax + IDSS
Minimum Vout = 1.25 V
VO < POV + 1.25 V + VSS
ILmin - IP < IO < 500 mA - IP
As shown O < IO < 495 mA
D1 protects the device during an input short circuit.
Figure 21. Adjustable Current Limiter
Vin
Vout
Vin
D2
1N914
Vref
R2 ≥
IDSS
R1 =
IO
VO
R1
LM317M
Figure 22. 5 V Electronic Shutdown Regulator
Vout
Vin
Vout
LM317M
240
R1
Iout
R2
LM317M
Vout
1N4001
Adjust
IAdj
50k
Adjust
R2
MPS2907
+
Ioutmax =
10mF
Vref
R1 + R2
1.25 V
+ IAdj ^ R + R
1
2
5.0 mA < Iout < 500 mA
R θ JA, THERMAL RESISTANCE, JUNCTION-TO-AIR (° C/W)
Figure 23. Slow Turn−On Regulator
Figure 24. Current Regulator
100
2.4
90
80
Minimum
Size Pad
70
280
2.50
PD(max) for TA = 50°C
Free Air
Mounted
Vertically
60
2.0
240
2.0 oz. Copper
L
1.6
200
L
1.2
160
0.8
120
0.4
80
ÎÎÎ
ÎÎÎ
ÎÎÎ
50
PD(max) for TA = 50°C
Free Air
Mounted
Vertically
1.25
0
10
15
L
0.63
0.42
RqJA
40
5.0
0.83
0.50
RqJA
0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Minimum
Size Pad
2.0 oz. Copper
L
20
25
40
30
0
5.0
10
15
20
25
30
0.35
L, LENGTH OF COPPER (mm)
L, LENGTH OF COPPER (mm)
Figure 25. DPAK Thermal Resistance and Maximum
Power Dissipation versus PCB Copper Length
Figure 26. SOT−223 Thermal Resistance and Maximum
Power Dissipation versus PCB Copper Length
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9
LM317M, NCV317MA, NCV317M
ORDERING INFORMATION
Output Voltage
Operating Temperature
Range
Package
Shipping†
LM317MABDTG
DPAK
(Pb−Free)
75 Units / Rail
LM317MABDTRKG
DPAK
(Pb−Free)
2500 / Tape & Reel
SOT−223
(Pb−Free)
4000 / Tape & Reel
TO−220
(Pb−Free)
50 Units / Rail
DPAK
(Pb−Free)
2500 / Tape & Reel
DPAK
(Pb−Free)
75 Units / Rail
DPAK
(Pb−Free)
2500 / Tape & Reel
SOT−223
(Pb−Free)
4000 / Tape & Reel
TO−220
(Pb−Free)
50 Units / Rail
LM317MDTG
DPAK
(Pb−Free)
75 Units / Rail
LM317MDTRKG
DPAK
(Pb−Free)
2500 / Tape & Reel
SOT−223
(Pb−Free)
4000 / Tape & Reel
TO−220
(Pb−Free)
50 Units / Rail
Device
Tolerance
NCV317MABDTRKG*
NCV317MABSTT3G*
TJ = −40°C to 125°C
2%
LM317MABTG
LM317MADTRKG
TJ = 0°C to 125°C
LM317MBDTG
NCV317MBDTG*
LM317MBDTRKG
NCV317MBDTRKG*
TJ = −40°C to 125°C
LM317MBSTT3G
NCV317MBSTT3G*
LM317MBTG
NCV317MBTG*
LM317MSTT3G
4%
TJ = 0°C to 125°C
LM317MTG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*NCV devices: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV Prefix for Automotive and Other Applications Requiring Unique Site
and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.
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10
LM317M, NCV317MA, NCV317M
MARKING DIAGRAMS
DPAK
DT SUFFIX
CASE 369C
317ABG
ALYWW
317MAG
ALYWW
317MBG
ALYWW
TO−220
T SUFFIX
CASE 221A
LM
317MABT
AWLYWWG
LM
317MBT
AWLYWWG
317MG
ALYWW
SOT−223
ST SUFFIX
CASE 318E
AYW
317MA G
G
LM
317MT
AWLYWWG
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
www.onsemi.com
11
AYW
317MB G
G
AYW
317M G
G
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220, SINGLE GAUGE
CASE 221AB−01
ISSUE A
−T−
B
F
T
SCALE 1:1
SEATING
PLANE
C
S
DATE 16 NOV 2010
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND
LEAD IRREGULARITIES ARE ALLOWED.
4. PRODUCT SHIPPED PRIOR TO 2008 HAD DIMENSIONS
S = 0.045 - 0.055 INCHES (1.143 - 1.397 MM)
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
U
1 2 3
H
K
Z
L
R
V
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.020
0.024
0.235
0.255
0.000
0.050
0.045
----0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
0.508
0.61
5.97
6.47
0.00
1.27
1.15
----2.04
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
BASE
EMITTER
COLLECTOR
EMITTER
STYLE 3:
PIN 1.
2.
3.
4.
CATHODE
ANODE
GATE
ANODE
STYLE 4:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
STYLE 5:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 6:
PIN 1.
2.
3.
4.
ANODE
CATHODE
ANODE
CATHODE
STYLE 7:
PIN 1.
2.
3.
4.
CATHODE
ANODE
CATHODE
ANODE
STYLE 8:
PIN 1.
2.
3.
4.
CATHODE
ANODE
EXTERNAL TRIP/DELAY
ANODE
STYLE 9:
PIN 1.
2.
3.
4.
GATE
COLLECTOR
EMITTER
COLLECTOR
STYLE 10:
PIN 1.
2.
3.
4.
GATE
SOURCE
DRAIN
SOURCE
STYLE 11:
PIN 1.
2.
3.
4.
DRAIN
SOURCE
GATE
SOURCE
DOCUMENT NUMBER:
DESCRIPTION:
98AON23085D
TO−220, SINGLE GAUGE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
4
1 2
DATE 21 JUL 2015
3
SCALE 1:1
A
E
b3
C
A
B
c2
4
L3
Z
D
1
L4
2
3
NOTE 7
b2
e
c
SIDE VIEW
b
0.005 (0.13)
TOP VIEW
H
DETAIL A
M
BOTTOM VIEW
C
Z
H
L2
GAUGE
PLANE
C
L
L1
DETAIL A
Z
SEATING
PLANE
BOTTOM VIEW
A1
ALTERNATE
CONSTRUCTIONS
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
6.17
0.243
SCALE 3:1
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
XXXXXX
A
L
Y
WW
G
3.00
0.118
1.60
0.063
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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