DATA SHEET
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Voltage Regulator - Low
Power Low, Dropout
TO−92
CASE 29−10
100 mA
LP2950, LP2951, NCV2951
The LP2950 and LP2951 are micropower voltage regulators that are
specifically designed to maintain proper regulation with an extremely
low input−to−output voltage differential. These devices feature a very
low quiescent bias current of 75 mA and are capable of supplying
output currents in excess of 100 mA. Internal current and thermal
limiting protection is provided.
The LP2951 has three additional features. The first is the Error
Output that can be used to signal external circuitry of an out of
regulation condition, or as a microprocessor power−on reset. The
second feature allows the output voltage to be preset to 5.0 V, 3.3 V or
3.0 V output (depending on the version) or programmed from 1.25 V
to 29 V. It consists of a pinned out resistor divider along with direct
access to the Error Amplifier feedback input. The third feature is
a Shutdown input that allows a logic level signal to turn−off or turn−on
the regulator output.
Due to the low input−to−output voltage differential and bias current
specifications, these devices are ideally suited for battery powered
computer, consumer, and industrial equipment where an extension of
useful battery life is desirable. The LP2950 is available in the three
pin case 29 and DPAK packages, and the LP2951 is available in the
eight pin dual−in−line, SOIC−8 and Micro8 surface mount packages.
The ‘A’ suffix devices feature an initial output voltage tolerance
± 0.5%.
Features
• Low Quiescent Bias Current of 75 mA
• Low Input−to−Output Voltage Differential of 50 mV at 100 mA and
•
•
•
•
•
•
380 mV at 100 mA
5.0 V, 3.3 V or 3.0 V ± 0.5% Allows Use as a Regulator or Reference
Extremely Tight Line and Load Regulation
Requires Only a 1.0 mF Output Capacitor for Stability
Internal Current and Thermal Limiting
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and RoHS Compliant
1
12
3
STRAIGHT LEAD
2
3
BENT LEAD
PIN CONNECTIONS
4
1 2
Pin: 1. Output
2. Ground
3. Input
Pin: 1. Input
2. Ground
3. Output
3
1
DPAK
CASE 369C
2
3
(Top View)
Heatsink surface (shown as terminal 4 in
case outline drawing) is connected to Pin 2.
8
1
SOIC−8
CASE 751
PDIP−8
CASE 626
8
1
8
1
Micro8
CASE 846A
PIN CONNECTIONS
Output 1
8
Input
Sense 2
7
Feedback
Shutdown 3
6
VO Tap
GND 4
5
Error Output
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on pages 14 and 15 of this data sheet.
DEVICE MARKING INFORMATION
LP2951 Additional Features
See general marking information in the device marking
section on page 16 of this data sheet.
• Error Output Signals an Out of Regulation Condition
• Output Programmable from 1.25 V to 29 V
• Logic Level Shutdown Input
(See Following Page for Device Information.)
© Semiconductor Components Industries, LLC, 1995
October, 2021 − Rev. 34
1
Publication Order Number:
LP2950/D
LP2950, LP2951, NCV2951
DEVICE INFORMATION
Output Voltage
Package
3.0 V
3.3 V
5.0 V
Adjustable
Operating Ambient
Temperature Range
TO−92
Suffix Z
LP2950CZ−3.0
LP2950ACZ−3.0
LP2950CZ−3.3
LP2950ACZ−3.3
LP2950CZ−5.0
LP2950ACZ−5.0
Not
Available
TA = −40° to +125°C
DPAK
Suffix DT
LP2950CDT−3.0
LP2950ACDT−3.0
LP2950CDT−3.3
LP2950ACDT−3.3
LP2950CDT−5.0
LP2950ACDT−5.0
Not
Available
TA = −40° to +125°C
NCV2951ACD−3.3R2
NCV2951ACDR2
NCV2951CDR2
TA = −40° to +125°C
−
SOIC−8
SOIC−8
Suffix D
LP2951CD−3.0
LP2951ACD−3.0
LP2951CD−3.3
LP2951ACD−3.3
LP2951CD
LP2951ACD
LP2951CD
LP2951ACD
TA = −40° to +125°C
Micro8
Suffix DM
LP2951CDM−3.0
LP2951ACDM−3.0
LP2951CDM−3.3
LP2951ACDM−3.3
LP2951CDM
LP2951ACDM
LP2951CDM
LP2951ACDM
TA = −40° to +125°C
DIP−8
Suffix N
LP2951CN−3.0
LP2951ACN−3.0
LP2951CN−3.3
LP2951ACN−3.3
LP2951CN
LP2951ACN
LP2951CN
LP2951ACN
TA = −40° to +125°C
LP2950Cx−xx / LP2951Cxx−xx
LP2950ACx−xx / LP2951ACxx−xx
1% Output Voltage Precision at TA = 25°C
0.5% Output Voltage Precision at TA = 25°C
Input
Battery or
Unregulated DC
Output
182 k
Error Amplifier
60 k
1.23 V
Reference
GND
Input
Battery or
Unregulated DC
5.0 V/100 mA
1.0 mF
1
3
LP2950CZ−5.0
2
8
Output
1
Sense
5.0 V/100 mA
2
182 k
1.0 mF
VO Tap
6
60 k
7
From
3
CMOS/TTL
Feedback
Error
Amplifier
Shutdown
330 k
60 k
50 k
75 mV/
60 mV
Error
Output
To CMOS/TTL
5
Error Detection
Comparator
1.23 V
Reference
GND
4
LP2951CD or CN
This device contains 34 active transistors.
Figure 1. Representative Block Diagrams
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2
LP2950, LP2951, NCV2951
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Input Voltage
Symbol
Value
Unit
VCC
30
Vdc
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Peak Transient Input Voltage (t < 300 ms)
VCC
32
Vdc
PD
Internally Limited
W
Thermal Resistance, Junction−to−Ambient
RqJA
180
°C/W
Thermal Resistance, Junction−to−Case
RqJC
45
°C/W
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation
Case 751(SOIC−8) D Suffix
Case 369A (DPAK) DT Suffix (Note 1)
Thermal Resistance, Junction−to−Ambient
RqJA
92
°C/W
Thermal Resistance, Junction−to−Case
RqJC
6.0
°C/W
Thermal Resistance, Junction−to−Ambient
RqJA
160
°C/W
Thermal Resistance, Junction−to−Case
RqJC
83
°C/W
RqJA
105
°C/W
RqJA
240
°C/W
Feedback Input Voltage
Vfb
−1.5 to +30
Vdc
Shutdown Input Voltage
Vsd
−0.3 to +30
Vdc
Error Comparator Output Voltage
Verr
−0.3 to +30
Vdc
Operating Ambient Temperature Range
TA
−40 to +125
°C
Maximum Die Junction Temperature Range
TJ
+150
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Case 29 (TO−226AA/TO−92) Z Suffix
Case 626 N Suffix
Thermal Resistance, Junction−to−Ambient
Case 846A (Micro8) DM Suffix
Thermal Resistance, Junction−to−Ambient
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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LP2950, LP2951, NCV2951
ELECTRICAL CHARACTERISTICS
(Vin = VO + 1.0 V, IO = 100 mA, CO = 1.0 mF, TA = 25°C [Note 3], unless otherwise noted.)
Characteristic
Symbol
Output Voltage, 5.0 V Versions
Min
Typ
Max
VO
Unit
V
Vin = 6.0 V, IO = 100 mA, TA = 25°C
LP2950C−5.0/LP2951C/NCV2951C*
4.950
5.000
5.050
LP2950AC−5.0/LP2951AC/NCV2951AC*
4.975
5.000
5.025
LP2950C−5.0/LP2951C/NCV2951C*
4.900
−
5.100
LP2950AC−5.0/LP2951AC/NCV2951AC*
4.940
−
5.060
LP2950C−5.0/LP2951C/NCV2951C*
4.880
−
5.120
LP2950AC−5.0/LP2951AC/NCV2951AC*
4.925
−
5.075
TA = − 40 to +125°C
Vin = 6.0 to 30 V, IO = 100 mA to 100 mA, TA = − 40 to +125°C
Output Voltage, 3.3 V Versions
VO
V
Vin = 4.3 V, IO = 100 mA, TA = 25°C
LP2950C−3.3/LP2951C−3.3
3.267
3.300
3.333
LP2950AC−3.3/LP2951AC−3.3/NCV2951AC−3.3*
3.284
3.300
3.317
LP2950C−3.3/LP2951C−3.3
3.234
−
3.366
LP2950AC−3.3/LP2951AC−3.3/NCV2951AC−3.3*
3.260
−
3.340
LP2950C−3.3/LP2951C−3.3
3.221
−
3.379
LP2950AC−3.3/LP2951AC−3.3/NCV2951AC−3.3*
3.254
−
3.346
TA = − 40 to +125°C
Vin = 4.3 to 30 V, IO = 100 mA to 100 mA, TA = − 40 to +125°C
Output Voltage, 3.0 V Versions
VO
V
Vin = 4.0 V, IO = 100 mA, TA = 25°C
LP2950C−3.0/LP2951C−3.0
2.970
3.000
3.030
LP2950AC−3.0/LP2951AC−3.0
2.985
3.000
3.015
LP2950C−3.0/LP2951C−3.0
2.940
−
3.060
LP2950AC−3.0/LP2951AC−3.0
2.964
−
3.036
LP2950C−3.0/LP2951C−3.0
2.928
−
3.072
LP2950AC−3.0/LP2951AC−3.0
2.958
−
3.042
TA = − 40 to +125°C
Vin = 4.0 to 30 V, IO = 100 mA to 100 mA, TA = − 40 to +125°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. The Junction−to−Ambient Thermal Resistance is determined by PCB copper area per Figure 29.
2. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM), 2000 V, Class 2, JESD22 A114−C
Machine Model (MM), 200 V, Class B, JESD22 A115−A
Charged Device Model (CDM), 2000 V, Class IV, JESD22 C101−C
3. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
4. VO(nom) is the part number voltage option.
5. Noise tests on the LP2951 are made with a 0.01 mF capacitor connected across Pins 7 and 1.
6. Latch−up Current Maximum Rating tested per JEDEC standard: JESD78
− Inputs Low: passing positive current 100 mA and negative current −100 mA
− Inputs High: passing positive current 100 mA and negative current −10 mA.
*NCV prefix is for automotive and other applications requiring site and change control.
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LP2950, LP2951, NCV2951
ELECTRICAL CHARACTERISTICS (continued)
(Vin = VO + 1.0 V, IO = 100 mA, CO = 1.0 mF, TA = 25°C [Note 9], unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
−
−
0.08
0.04
0.20
0.10
−
−
0.13
0.05
0.20
0.10
−
−
30
350
80
450
−
−
93
4.0
120
12
mA
mA
ICCdropout
−
110
170
mA
ILimit
−
220
300
mA
Regthermal
−
0.05
0.20
%/W
−
−
126
56
−
−
1.210
1.220
1.235
1.235
1.260
1.250
1.200
1.200
−
−
1.270
1.260
Line Regulation (Vin = VO(nom) +1.0 V to 30 V) (Note 10)
LP2950C−XX/LP2951C/LP2951C−XX/NCV2951C*
LP2950AC−XX/LP2951AC/LP2951AC−XX/NCV2951AC*
Regline
Load Regulation (IO = 100 mA to 100 mA)
LP2950C−XX/LP2951C/LP2951C−XX/NCV2951C*
LP2950AC−XX/LP2951AC/LP2951AC−XX/NCV2951AC*
Regload
Dropout Voltage
IO = 100 mA
IO = 100 mA
VI − VO
Supply Bias Current
IO = 100 mA
IO = 100 mA
ICC
Dropout Supply Bias Current (Vin = VO(nom) − 0.5 V,
IO = 100 mA) (Note 10)
Current Limit (VO Shorted to Ground)
Thermal Regulation
Output Noise Voltage (10 Hz to 100 kHz) (Note 11)
CL = 1.0 mF
CL = 100 mF
Vn
Unit
%
%
mV
mVrms
LP2951A/LP2951AC Only
Reference Voltage (TA = 25°C)
LP2951C/LP2951C−XX/NCV2951C*
LP2951AC/LP2951AC−XX/NCV2951AC*
Vref
Reference Voltage (TA = − 40 to +125°C)
LP2951C/LP2951C−XX/NCV2951C*
LP2951AC/LP2951AC−XX/NCV2951AC*
Vref
Reference Voltage (TA = − 40 to +125°C)
IO = 100 mA to 100 mA, Vin = 23 to 30 V
LP2951C/LP2951C−XX/NCV2951C*
LP2951AC/LP2951AC−XX/NCV2951AC*
Vref
Feedback Pin Bias Current
V
V
V
1.185
1.190
−
−
1.285
1.270
IFB
−
15
40
nA
Output Leakage Current (VOH = 30 V)
Ilkg
−
0.01
1.0
mA
Output Low Voltage (Vin = 4.5 V, IOL = 400 mA)
VOL
−
150
250
mV
Upper Threshold Voltage (Vin = 6.0 V)
Vthu
40
45
−
mV
Lower Threshold Voltage (Vin = 6.0 V)
Vthl
−
60
95
mV
Hysteresis (Vin = 6.0 V)
Vhy
−
15
−
mV
0
2.0
−
−
0.7
30
−
−
35
450
50
600
−
3.0
10
Error Comparator
Shutdown Input
Input Logic Voltage
Logic “0” (Regulator “On”)
Logic “1” (Regulator “Off”)
Vshtdn
Shutdown Pin Input Current
Vshtdn = 2.4 V
Vshtdn = 30 V
Ishtdn
Regulator Output Current in Shutdown Mode
(Vin = 30 V, Vshtdn = 2.0 V, VO = 0, Pin 6 Connected to Pin 7)
Ioff
V
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. The Junction−to−Ambient Thermal Resistance is determined by PCB copper area per Figure 29.
8. ESD data available upon request.
9. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
10. VO(nom) is the part number voltage option.
11. Noise tests on the LP2951 are made with a 0.01 mF capacitor connected across Pins 7 and 1.
*NCV prefix is for automotive and other applications requiring site and change control.
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5
LP2950, LP2951, NCV2951
DEFINITIONS
Output Noise Voltage − The RMS ac voltage at the
output, with constant load and no input ripple, measured
over a specified frequency range.
Leakage Current − Current drawn through a bipolar
transistor collector−base junction, under a specified
collector voltage, when the transistor is “off”.
Upper Threshold Voltage − Voltage applied to the
comparator input terminal, below the reference voltage
which is applied to the other comparator input terminal,
which causes the comparator output to change state from a
logic “0” to “1”.
Lower Threshold Voltage − Voltage applied to the
comparator input terminal, below the reference voltage
which is applied to the other comparator input terminal,
which causes the comparator output to change state from a
logic “1” to “0”.
Hysteresis − The difference between Lower Threshold
voltage and Upper Threshold voltage.
Dropout Voltage − The input/output voltage differential
at which the regulator output no longer maintains regulation
against further reductions in input voltage. Measured when
the output drops 100 mV below its nominal value (which is
measured at 1.0 V differential), dropout voltage is affected
by junction temperature, load current and minimum input
supply requirements.
Line Regulation − The change in output voltage for a
change in input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that average chip temperature is not significantly
affected.
Load Regulation − The change in output voltage for a
change in load current at constant chip temperature.
Maximum Power Dissipation − The maximum total
device dissipation for which the regulator will operate
within specifications.
Bias Current − Current which is used to operate the
regulator chip and is not delivered to the load.
6.0
LP2951C
TA = 25°C
5.0
Vout , OUTPUT VOLTAGE (V)
LP2950/LP2951 BIAS CURRENT (mA)
10
1.0
0.1
0.01
0.1
1.0
10
4.0
RL = 50 W
3.0
2.0
1.0
0
100
RL = 50 kW
0
1.0
2.0
3.0
4.0
5.0
IL, LOAD CURRENT (mA)
Vin, INPUT VOLTAGE (V)
Figure 2. Quiescent Current
Figure 3. 5.0 V Dropout Characteristics over
Load
6.0
6.0
5.00
4.99
Vout , OUTPUT VOLTAGE (V)
Vout , OUTPUT VOLTAGE (V)
LP2951C
5.0
4.98
4.97
4.96
4.0
3.0
2.0
25°C
1.0
LP2951C
4.95
-50
125°C
−40°C
0
0
50
100
200
150
0
1.0
2.0
3.0
4.0
5.0
TA, AMBIENT TEMPERATURE (°C)
Vin, INPUT VOLTAGE (V)
Figure 4. Output Voltage versus Temperature
Figure 5. 5.0 V Dropout Characteristics with
RL = 50 W
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6
6.0
LP2950, LP2951, NCV2951
400
250
350
DROPOUT VOLTAGE (mV)
BIAS CURRENT (μ A)
200
0.1 mA Load Current
150
100
No Load
50
TA = 25°C
300
250
200
150
100
50
0
0.1
0
0
5.0
10
15
20
25
1.0
Figure 6. Input Current
45
RL = 50
40
400
35
RL = 50 k
300
-50
0
50
Vout , OUTPUT VOLTAGE (V)
50
500
DROPOUT VOLTAGE (mV) R L= 50 k
DROPOUT VOLTAGE (mV) R L= 50
5.0
55
350
30
150
100
4.0
LP2951C
RL = 330 k
TA = 25°C
Vin Decreasing
3.0
Vin Increasing
2.0
1.0
0
4.70
4.74
T, TEMPERATURE (°C)
-2.0
6.5
TA = 25°C
CL = 1.0 mF
IL = 1.0 mA
VO = 5.0 V
5.5
0
100
200
300
400
-4.0
500
600
700
-6.0
800
SHUTDOWN AND OUTPUT VOLTAGE (V)
0
Vout
OUTPUT VOLTAGE CHANGE (mV)
Vin , INPUT VOLTAGE (V)
2.0
7.5
6.0
4.82
4.86
4.90
Figure 9. Error Comparator Output
4.0
Vin
7.0
4.78
Vin, INPUT VOLTAGE (V)
Figure 8. Dropout Voltage versus Temperature
8.0
100
Figure 7. Dropout Voltage versus Output Current
550
450
10
IO, OUTPUT CURRENT (mA)
Vin, INPUT VOLTAGE (V)
6.0
5.0
CL = 1.0 mF
4.0
CL = 10 mF
3.0
2.0
1.0
Shutdown Input
TA = 25°C
IL = 10 mA
Vin = 8.0 V
Vout = 5.0 V
0
-1.0
-100
0
100
200
300
t, TIME (ms)
t, TIME (ms)
Figure 10. Line Transient Response
Figure 11. LP2951 Enable Transient
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7
400
LP2950, LP2951, NCV2951
200
200
Vout
100
0
50
-200
ILoad
0
RIPPLE REJECTION (dB)
LOAD CURRENT (mA)
150
400
OUTPUT VOLTAGE CHANGE (mV)
80
CL = 1.0 mF
Vout = 5.0 V
IL = 400 mA to 75 mA
TA = 25°C
60
IL= 0.1 mA
40
TA = 25°C
CL = 1.0 mF
Vin = 6.0 V
Vout = 5.0 V
20
-400
-50
0
0.5
1
1.5
2
2.5
3
3.5
0
1.0
4
10
CL = 1.0 mF
2.0
CL = 100 mF
10 k
Vout , OUTPUT CURRENT (mA)
Output “Off"
1.2
Output “On"
1.0
0
20
40
60
80
100
120
140
f, FREQUENCY (Hz)
t, TEMPERATURE (°C)
Figure 14. Output Noise
Figure 15. Shutdown Threshold Voltage
versus Temperature
TA = 25°C
80
2.0
TA = 75°C
60
0
40
-2.0
20
-4.0
LP2951CN
5.0
1.4
0.8
-40 -20
10
15
20
25
30
35
160
10000
4.0
0
1.6
100 k
100
0
1.8
SHUTDOWN THRESHOLD VOLTAGE (V)
IL= 100 mA
TA = 25°C
VO = 5.0 V
LP2951C
3.0
1.0 k
100 k
Figure 13. Ripple Rejection
Vout = 5 V
OUTPUT VOLTAGE CHANGE (mV)
ESR (ohms)
VOLTAGE NOISE (μ V/√ Hz)
4.0
0
100
10 k
f, FREQUENCY (Hz)
Figure 12. Load Transient Response
1.0
1.0 k
100
t, TIME (ms)
1000
-6.0
40
Unstable Region
100
Stable Region
10
1
0.1 mF
Unstable Region for 0.1 mF capacitor only
0.1
0.01
100 mF
Lower unstable region is for 0.1 mF only.
1 mF and 100 mF show no instability with low ESR values.
0
Vin, INPUT VOLTAGE (V)
10
20
30
40
50
60
70
80
90
100
Output Current (mA)
Figure 16. Maximum Rated
Output Current
Figure 17. Output Stability versus Output Capacitor
Change
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8
LP2950, LP2951, NCV2951
APPLICATIONS INFORMATION
Introduction
to the LP2951 is ramped up and down. The ERROR signal
becomes valid (low) at about 1.3 V input. It goes high when
the input reaches about 5.0 V (Vout exceeds about 4.75 V).
Since the LP2951’s dropout voltage is dependent upon the
load current (refer to the curve in the Typical Performance
Characteristics), the input voltage trip point will vary with
load current. The output voltage trip point does not vary
with load.
The error comparator output is an open collector which
requires an external pullup resistor. This resistor may be
returned to the output or some other voltage within the
system. The resistance value should be chosen to be
consistent with the 400 mA sink capability of the error
comparator. A value between 100 kW and 1.0 MW is
suggested. No pullup resistance is required if this output is
unused.
When operated in the power down mode (Vin = 0 V),
the error comparator output will go high if it has been pulled
up to an external supply (the output transistor is in high
impedance state). To avoid this invalid response, the error
comparator output should be pulled up to Vout (see
Figure 18).
The LP2950/LP2951 regulators are designed with
internal current limiting and thermal shutdown making them
user−friendly. Typical application circuits for the LP2950
and LP2951 are shown in Figures 20 through 28.
These regulators are not internally compensated and thus
require a 1.0 mF (or greater) capacitance between the
LP2950/LP2951 output terminal and ground for stability.
Most types of aluminum, tantalum or multilayer ceramic
will perform adequately. Solid tantalums or appropriate
multilayer ceramic capacitors are recommended for
operation below 25°C.
At lower values of output current, less output capacitance
is required for output stability. The capacitor can be reduced
to 0.33 mF for currents less than 10 mA, or 0.1 mF for currents
below 1.0 mA. Using the 8 pin versions at voltages less than
5.0 V operates the error amplifier at lower values of gain, so
that more output capacitance is needed for stability. For the
worst case operating condition of a 100 mA load at 1.23 V
output (output Pin 1 connected to the feedback Pin 7)
a minimum capacitance of 3.3 mF is recommended.
The LP2950 will remain stable and in regulation when
operated with no output load. When setting the output
voltage of the LP2951 with external resistors, the resistance
values should be chosen to draw a minimum of 1.0 mA.
A bypass capacitor is recommended across the
LP2950/LP2951 input to ground if more than 4 inches of
wire connects the input to either a battery or power supply
filter capacitor.
Input capacitance at the LP2951 Feedback Pin 7 can
create a pole, causing instability if high value external
resistors are used to set the output voltage. Adding a 100 pF
capacitor between the Output Pin 1 and the Feedback Pin 7
and increasing the output filter capacitor to at least 3.3 mF
will stabilize the feedback loop.
5.0 V
4.75 V
Output
Voltage
ERROR
Not
Valid
Not
Valid
4.75 V + Vdropout
Input
Voltage
Error Detection Comparator
The comparator switches to a positive logic low whenever
the LP2951 output voltage falls more than approximately
5.0% out of regulation. This value is the comparator’s
designed−in offset voltage of 60 mV divided by the 1.235 V
internal reference. As shown in the representative block
diagram. This trip level remains 5.0% below normal
regardless of the value of regulated output voltage. For
example, the error flag trip level is 4.75 V for a normal 5.0 V
regulated output, or 9.50 V for a 10 V output voltage.
Figure 2 is a timing diagram which shows the ERROR
signal and the regulated output voltage as the input voltage
4.70 V
1.3 V
Pullup
to Ext
Pullup
to Vout
4.70 V + Vdropout
1.3 V
Figure 18. ERROR Output Timing
Programming the Output Voltage (LP2951)
The LP2951CX may be pin−strapped for the nominal
fixed output voltage using its internal voltage divider by
tying Pin 1 (output) to Pin 2 (sense) and Pin 7 (feedback) to
Pin 6 (5.0 V tap). Alternatively, it may be programmed for
any output voltage between its 1.235 reference voltage and
its 30 V maximum rating. An external pair of resistors is
required, as shown in Figure 19.
www.onsemi.com
9
LP2950, LP2951, NCV2951
for reducing noise on the 3 lead LP2950. However,
increasing the capacitor from 1.0 mF to 220 mF only
decreases the noise from 430 mV to 160 mVrms for a 100 kHz
bandwidth at the 5.0 V output.
Noise can be reduced fourfold by a bypass capacitor
across R1, since it reduces the high frequency gain from 4
to unity. Pick
Vin
100 k
Error
Output
5
8
Vin
Vout
Error
SNS
Shutdown
Input
3
SD
VO T
1
2
Vout
1.23 to 30 V
NC
6 NC
R1
0.01 mF
C
3.3 mF
R2
Figure 19. Adjustable Regulator
1
2pR1 x 200 Hz
Unregulated
Input
The complete equation for the output voltage is:
V
+ V (1 ) R1ńR2) ) I
R1
ref
[
or about 0.01 mF. When doing this, the output capacitor must
be increased to 3.3 mF to maintain stability. These changes
reduce the output noise from 430 mV to 126 mVrms for a
100 kHz bandwidth at 5.0 V output. With bypass capacitor
added, noise no longer scales with output voltage so that
improvements are more dramatic at higher output voltages.
GND FB
4
7
out
Bypass
MTB23P06E
1.0 mF
10 k
0.01 mF
FB
where Vref is the nominal 1.235 V reference voltage and IFB
is the feedback pin bias current, nominally − 20 nA. The
minimum recommended load current of 1.0 mA forces an
upper limit of 1.2 MW on the value of R2, if the regulator
must work with no load. IFB will produce a 2% typical error
in Vout which may be eliminated at room temperature by
adjusting R1. For better accuracy, choosing R2 = 100 k
reduces this error to 0.17% while increasing the resistor
program current to 12 mA. Since the LP2951 typically draws
75 mA at no load with Pin 2 open circuited, the extra 12 mA
of current drawn is often a worthwhile tradeoff for
eliminating the need to set output voltage in test.
Error
Output
5 Error
Vout
5.0 V ±1.0%
0 to 1.0 A
8
Vin
Vout
SNS
LP2951CN
Shutdown
Input
3
SD
VO T
1
2
6
220 mF
GND FB
4
7
0.002 mF
1.0 M
2.0 k
Output Noise
In many applications it is desirable to reduce the noise
present at the output. Reducing the regulator bandwidth by
increasing the size of the output capacitor is the only method
Figure 20. 1.0 A Regulator with 1.2 V Dropout
www.onsemi.com
10
LP2950, LP2951, NCV2951
TYPICAL APPLICATIONS
+V = 2.0 to 30 V
IL
IL = 1.23/R
Load
Unregulated Input
6.0 to 10 Vdc
8
Vin
8
NC
5 Error
Vin
Vout
1N4001
1
2
NC
SNS
0.1 mF LP2951CN
3
6 NC
SD
VO T
330 pF
GND FB
4
7
2.2 mF
4.2 V ±0.025 V
Error
Output
2.0 M
1.0%
806 k
1.0%
Shutdown
Input
5
0.1 mF
Vout
Error
1
2
SNS
LP2951CN
3
6
SD
VO T
GND FB
4
7
Lithium Ion
Rechargeable
Cell
50 k
1.0 mF
R
GND
Figure 21. Lithium Ion Battery Cell Charger
Figure 22. Low Drift Current Sink
+Vin
+Vin
8
Vin
470 k
2N3906
5
470 k
Reset
Normally
Closed
Error
Vout
SNS
LP2951CN
3
SD
CMOS
Gate
*Sleep
Input
VO T
1
2
Vout
NC
6 NC
Error
Output
R1
GND FB
4
7
1.0 mF
5
470 k
8
Vin
47 k
Error
Vout
SNS
LP2951CN
Shutdown
Input
3
SD
GND
4
R2
Error flag occurs when Vin is too
low to maintain Vout, or if Vout is reduced by excessive load current.
2
Vout
2N3906
1
NC
200 k
3.3 mF
6 NC
VO T
100 k 100 pF
FB
7
100 k
Figure 23. Latch Off When Error Flag Occurs
Figure 24. 5.0 V Regulator with 2.5 V Sleep Function
www.onsemi.com
11
LP2950, LP2951, NCV2951
+Vin
5
NC
8
Vin
Vout
Error
D2
1
2
SNS
LP2951CN
#1
3
6
SD
VO T
D1
Memory
V+
1.0 mF
20
3.6 V
NiCad
GND FB
4
7
Early Warning
27 k
All diodes are 1N4148.
D3
Reset
2.7 M
Q1
Early Warning flag on low input voltage.
mP
D4
Main output latches off at lower input voltages.
VDD
2N3906
5
Battery backup on auxiliary output.
8
Vin
330 k
Vout
Error
1
2
SNS
LP2951CN
#2
3
6
SD
VO T
GND
4
Operation: Regulator #1’s Vout is programmed one
diode drop above 5.0 V. Its error flag becomes active
when Vin < 5.7 V. When Vin drops below 5.3 V, the
error flag of regulator #2 becomes active and via Q1
latches the main output “off”. When Vin again exceeds
5.7 V, regulator #1 is back in regulation and the early
warning signal rises, unlatching regulator #2 via D3.
Main
Output
1.0 mF
FB
7
Figure 25. Regulator with Early Warning and Auxiliary Output
+Vin
Current Limit
Section
0.05
470
680
2N3906
1000 mF
2N3906
MJE2955
.33 mF
10 k
4.7 M
Error
Flag
5
220
8
Vin
Error
Vout
SNS
LP2951CN
3
SD
VO T
GND FB
4
7
20 k
1
2
NC
6 NC
.01 mF
Vout @ 2.0 A
47
4.7 mF
Tant
100 mF
R1
R2
0.033 mF
Vout = 1.25V (1.0 + R1/R2)
For 5.0 V output, use internal resistors. Wire Pin 6 to 7,
and wire Pin 2 to +Vout Bus.
Figure 26. 2.0 A Low Dropout Regulator
www.onsemi.com
12
LP2950, LP2951, NCV2951
+ 5.0 V
4.7 k
Output*
1
4
20 mA
5
NC
8
Vin
Vout
Error
SNS
LP2951CN
3
NC
1N4001
5
0.1 mF
SD
VO T
Gnd
4
2
1
2
4
NC
6
* High for
IL < 3.5 mA
NC
FB
7
1N457
360
1N457
1N457
Figure 27. Open Circuit Detector for 4.0 to 20 mA Current Loop
31.6 k
100 k
2
NC
1
5
8
Vin
Error
Vout
SNS
LP2951CN
3
3
SD
VO T
Gnd
4
1
Main V+
2
Memory V+
1.0 mF
6
20
NC
NiCad Backup
Battery
FB
7
NC
Figure 28. Low Battery Disconnect
JUNCTION‐TO‐AIR (°C/W)
R θ JA, THERMAL RESISTANCE
100
2.4
PD(max) for TA = 50°C
Free Air
Mounted
Vertically
90
2.0
80
Minimum
Size Pad
70
60
50
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0 oz. Copper
L
1.6
L
1.2
0.8
0.4
RqJA
40
0
0
5.0
10
15
20
25
30
L, LENGTH OF COPPER (mm)
Figure 29. DPAK Thermal Resistance and Maximum
Power Dissipation versus PCB Copper Length
www.onsemi.com
13
PD, MAXIMUM POWER DISSIPATION (W)
MC34164P−5
6.0 V Lead-Acid
Battery
2N3906
LP2950, LP2951, NCV2951
ORDERING INFORMATION (LP2950)
Output Voltage
(Volts)
Tolerance (%)
Package
Shipping†
LP2950CZ−3.0G
3.0
1.0
TO−92
(Pb−Free)
2000 Units / Bag
LP2950CZ−3.0RAG
3.0
1.0
TO−92
(Pb−Free)
2000 Units / Tape & Reel
LP2950ACZ−3.0G
3.0
0.5
TO−92
(Pb−Free)
2000 Units / Bag
LP2950ACZ−3.0RAG
3.0
0.5
TO−92
(Pb−Free)
2000 Units / Tape & Reel
LP2950CZ−3.3G
3.3
1.0
TO−92
(Pb−Free)
2000 Units / Bag
LP2950CZ−3.3RAG
3.3
1.0
TO−92
(Pb−Free)
2000 Units / Tape & Reel
LP2950ACZ−3.3G
3.3
0.5
TO−92
(Pb−Free)
2000 Units / Bag
LP2950ACZ−3.3RAG
3.3
0.5
TO−92
(Pb−Free)
2000 Units / Tape & Reel
LP2950CZ−5.0G
5.0
1.0
TO−92
(Pb−Free)
2000 Units / Bag
LP2950CZ−5.0RAG
5.0
1.0
TO−92
(Pb−Free)
2000 Units / Tape & Reel
LP2950CZ−5.0RPG
5.0
1.0
TO−92
(Pb−Free)
2000 Units / Ammo Pack
LP2950ACZ−5.0G
5.0
0.5
TO−92
(Pb−Free)
2000 Units / Bag
LP2950ACZ−5.0RAG
5.0
0.5
TO−92
(Pb−Free)
2000 Units / Tape & Reel
LP2950CDT−3.0RKG
3.0
1.0
DPAK
(Pb−Free)
2500 Units / Tape & Reel
LP2950CDT−3.3G
3.3
1.0
DPAK
(Pb−Free)
75 Units / Rail
LP2950CDT−3.3RKG
3.3
1.0
DPAK
(Pb−Free)
2500 Units / Tape & Reel
LP2950ACDT−3.3RG
3.3
0.5
DPAK
(Pb−Free)
2500 Units / Tape & Reel
LP2950CDT−5.0G
5.0
1.0
DPAK
(Pb−Free)
75 Units / Rail
LP2950CDT−5.0RKG
5.0
1.0
DPAK
(Pb−Free)
2500 Units / Tape & Reel
LP2950ACDT−5.0G
5.0
0.5
DPAK
(Pb−Free)
75 Units / Rail
LP2950ACDT−5RKG
5.0
0.5
DPAK
(Pb−Free)
2500 Units / Tape & Reel
Part Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
14
LP2950, LP2951, NCV2951
ORDERING INFORMATION (LP2951)
Output Voltage
(Volts)
Tolerance (%)
Package
Shipping†
LP2951CD−3.0R2G
3.0
1.0
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
LP2951ACD−3.0R2G
3.0
0.5
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
LP2951CD−3.3R2G
3.3
1.0
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
LP2951ACD−3.3G
3.3
0.5
SOIC−8
(Pb−Free)
98 Units / Rail
LP2951ACD−3.3R2G
3.3
0.5
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
LP2951CDG
5.0 or Adj.
1.0
SOIC−8
(Pb−Free)
98 Units / Rail
LP2951CDR2G
5.0 or Adj.
1.0
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
LP2951ACDG
5.0 or Adj.
0.5
SOIC−8
(Pb−Free)
98 Units / Rail
LP2951ACDR2G
5.0 or Adj.
0.5
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
LP2951ACDM−3.0RG
3.0
0.5
Micro8
(Pb−Free)
4000 Units / Tape & Reel
LP2951ACDM−3.3RG
3.3
0.5
Micro8
(Pb−Free)
4000 Units / Tape & Reel
LP2951CDMR2G
5.0 or Adj.
1.0
Micro8
(Pb−Free)
4000 Units / Tape & Reel
LP2951ACDMR2G
5.0 or Adj.
0.5
Micro8
(Pb−Free)
4000 Units / Tape & Reel
Part Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ORDERING INFORMATION (NCV2951)
Output Voltage
(Volts)
Tolerance (%)
Package
Shipping†
3.3
0.5
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
NCV2951ACDR2G*
5.0 or Adj.
0.5
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
NCV2951CDR2G*
5.0 or Adj.
1.0
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
NCV2951ACDMR2G*
5.0 or Adj.
0.5
Micro8
(Pb−Free)
4000 Units / Tape & Reel
Part Number
NCV2951ACD3.3R2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
15
LP2950, LP2951, NCV2951
MARKING DIAGRAMS
DPAK
CASE 369C
TO−92
CASE 029
2950
CZ−xx
ALYW
2950A
CZ−xx
ALYW
50−yG
ALYWW
50−yyG
ALYWW
50A−yG
ALYWW
50AyyG
ALYWW
SOIC−8
CASE 751
8
1
8
51z
ALYW
G
*
1
8
51z−33
ALYW
G
*
1
51z−3
ALYW
G
PDIP−8
CASE 626
8
8
51CN
AWL
YYWWG
1
8
51ACN
AWL
YYWWG
1
Micro8
CASE 846A
1
8
8
51CN−xx
AWL
YYWWG
51ACN−xx
AWL
YYWWG
1
xx
= 3.0, 3.3, or 5.0
y
= 3 or 5
yy
= 30, 33, or 50
z
= A or C
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This marking diagram also applies to NCV2951.
www.onsemi.com
16
8
PAyy
AYWG
G
1
P−yy
AYWG
G
1
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
SCALE 1:1
12
3
STRAIGHT LEAD
1
DATE 05 MAR 2021
2
3
BENT LEAD
STYLES AND MARKING ON PAGE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
DATE 05 MAR 2021
STYLES AND MARKING ON PAGE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
DATE 05 MAR 2021
STYLE 1:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 2:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. ANODE
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 6:
PIN 1. GATE
2. SOURCE & SUBSTRATE
3. DRAIN
STYLE 7:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 8:
PIN 1. DRAIN
2. GATE
3. SOURCE & SUBSTRATE
STYLE 9:
PIN 1. BASE 1
2. EMITTER
3. BASE 2
STYLE 10:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 11:
PIN 1. ANODE
2. CATHODE & ANODE
3. CATHODE
STYLE 12:
PIN 1. MAIN TERMINAL 1
2. GATE
3. MAIN TERMINAL 2
STYLE 13:
PIN 1. ANODE 1
2. GATE
3. CATHODE 2
STYLE 14:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
STYLE 15:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
STYLE 16:
PIN 1. ANODE
2. GATE
3. CATHODE
STYLE 17:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
STYLE 18:
PIN 1. ANODE
2. CATHODE
3. NOT CONNECTED
STYLE 19:
PIN 1. GATE
2. ANODE
3. CATHODE
STYLE 20:
PIN 1. NOT CONNECTED
2. CATHODE
3. ANODE
STYLE 21:
PIN 1. COLLECTOR
2. EMITTER
3. BASE
STYLE 22:
PIN 1. SOURCE
2. GATE
3. DRAIN
STYLE 23:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 24:
PIN 1. EMITTER
2. COLLECTOR/ANODE
3. CATHODE
STYLE 25:
PIN 1. MT 1
2. GATE
3. MT 2
STYLE 26:
PIN 1.
2.
3.
STYLE 27:
PIN 1. MT
2. SUBSTRATE
3. MT
STYLE 28:
PIN 1. CATHODE
2. ANODE
3. GATE
STYLE 29:
PIN 1. NOT CONNECTED
2. ANODE
3. CATHODE
STYLE 30:
PIN 1. DRAIN
2. GATE
3. SOURCE
STYLE 32:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
STYLE 33:
PIN 1. RETURN
2. INPUT
3. OUTPUT
STYLE 34:
PIN 1. INPUT
2. GROUND
3. LOGIC
STYLE 35:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
VCC
GROUND 2
OUTPUT
STYLE 31:
PIN 1. GATE
2. DRAIN
3. SOURCE
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 3 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
4
1 2
DATE 21 JUL 2015
3
SCALE 1:1
A
E
b3
C
A
B
c2
4
L3
Z
D
1
L4
2
3
NOTE 7
b2
e
c
SIDE VIEW
b
0.005 (0.13)
TOP VIEW
H
DETAIL A
M
BOTTOM VIEW
C
Z
H
L2
GAUGE
PLANE
C
L
L1
DETAIL A
Z
SEATING
PLANE
BOTTOM VIEW
A1
ALTERNATE
CONSTRUCTIONS
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 9:
STYLE 10:
PIN 1. ANODE
PIN 1. CATHODE
2. CATHODE
2. ANODE
3. RESISTOR ADJUST
3. CATHODE
4. CATHODE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.028 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.114 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.72
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.90 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
6.17
0.243
SCALE 3:1
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
XXXXXX
A
L
Y
WW
G
3.00
0.118
1.60
0.063
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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