LV3313PM-TLM-E

Ordering number : ENA1257 LV3313PM Bi-CMOS LSI Electronic Volume IC for Car Audio Systems http://onsemi.com Overview The LV3313PM is an electronic volume IC that implements a rich set of audio control functions including input selection switching function, an input gain, volume, loudness, balance, fader, and bass/treble control. Features  Zero-cross switching circuits (Input gain control block and Volume control block) can switch signal detection location automatically.  Zero-cross switching circuits (Input gain control block and Volume control block) and soft mute circuits used for low noise even when input signals are present.  Low power consumption due to the use of BiMOS process.  All functions are controlled using serial data (CCB). Functions  Input selector : Four input signals can be selected (three single-ended inputs and one differential input).  Input gain control : The input signal can be amplified by 0dB to +18dB (1dB steps).  Loudness control : Taps are output starting at the -32dB position of the ladder resistor and a loudness function implemented with external capacitor and resistor components.  Volume control : +10dB to -79dB/- (1dB steps) L/R independent control.  Bass control : +12dB to -12dB in 2dB steps  Treble control : +12dB to -12dB in 2dB steps  Fader control : The fader volume can be attenuations by one of 16 levels. Independent control each four channels. (A total of 16 settings with attenuations of 0dB to -2dB in 1dB steps, -2dB to -20dB in 2dB steps, and -30dB, -45dB, - 60dB and -dB settings.)  Mute  CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format.  CCB is a registered trademark of Semiconductor Components Industries, LLC. Semiconductor Components Industries, LLC, 2013 May, 2013 71608 MS PC 20080625-S00005 No.A1257-1/18 LV3313PM Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0V Parameter Symbol Conditions Maximum supply voltage VDD max VDD Maximum input voltage VIN max All input pins Allowable power dissipation Pd max Ratings Unit 9.5 V VSS-0.3 to VDD V Ta  85C, when mounted on a printed circuit 600 mW board * Operating temperature Topr -40 to +85 C Storage temperature Tstg -50 to +125 C * Specified circuit board : 114.3  76.1  1.6mm3 : glass epoxy board Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ratings at Ta = 25C, VSS = 0V Ratings Parameter Symbol Conditions Unit min typ Supply voltage VDD VDD High-level input voltage VIH CL, DI, CE 3.0 5.5 V Low-level input voltage VIL CL, DI, CE VSS 1.0 V VSS VDD Input voltage amplitude VIN Input pulse width TW 7.0 max CL CL, DI, CE 1 Thold CL, DI, CE 1 Operating frequency fopg CL tf Vp-p s Tsetup tr V s Hold time Falling time 9.0 1 Setup time Rising time 8.0 s 500 CL, DI, CE 0.1/fopg kHz s Electrical Characteristics at Ta = 25°C, VDD = 8V, VSS = 0V Ratings Parameter Symbol Conditions Unit min typ max Input block Input resistance Rin L1-L3, R1-R3 35 50 65 Minimum input gain Gin min L1-L3, R1-R3 -1.0 0 +1.0 dB Maximum input gain Gi max +17 +18 +19 dB ATerr -1.0 +1.0 dB BAL -0.5 +0.5 dB 65 k Inter-step setting error Left/Right balance k Volume block Input resistance Inter-step setting error Left/Right balance Rvr LVRIN, RVRIN ATerr +10dB to -40dB BAL 35 50 -0.5 +0.5 dB -0.5 +0.5 dB 14 dB Bass block Bass control range Inter-step setting error Left/Right balance Gb max max. boost/cut 10 ATerr -10dB to +10dB -0.5 +0.5 dB -0.5 +0.5 dB BAL 12 Treble block Treble control range Inter-step setting error Left/Right balance Gb max max. boost/cut 10 14 dB ATerr -10dB to +10dB -0.5 +0.5 dB -0.5 +0.5 dB BAL 12 Fader block Input resistance Rfed Inter-step setting error ATerr Left/Right balance BAL 65 k 0dB to -2dB -0.5 35 50 +0.5 dB -4dB to -20dB -1.0 +1.0 dB -30dB -2.0 +2.0 dB -45dB -3.0 +3.0 dB 0dB to -30dB -0.5 +0.5 dB No.A1257-2/18 LV3313PM Overall Characteristics at Ta = 25°C, VDD = 8V, VSS = 0V Ratings Parameter Symbol Conditions Unit min A loss of insertion ATT Total harmonic distortion THD typ max -1.0 VIN = 1Vrms, f = 1kHz 0.004 +1.0 dB 0.01 % Inter-input crosstalk CT VIN = 1Vrms, f = 1kHz 80 88 dB Left/Right channel crosstalk CT VIN = 1Vrms, f = 1kHz 80 88 dB Maximum attenuation VO min VIN = 1Vrms, f = 1kHz 80 88 Output noise voltage VN Current drain IDD Input high-level current IIH CL, DI, CE, VIN = 5.5V Input low-level current IIL CL, DI, CE, VIN = 0V Maximum input voltage VCL Common-mode rejection ratio CMRR dB 10 25 V 16 23 mA 10 A A -10 THD = 1% RL = 10k all controls flat, fIN = 1kHz 2.2 Vrms VIN = 1Vrms, f = 1kHz 50 dB Package Dimensions unit : mm (typ) 3148A 13.2 13.2 10.0 1.0 10.0 44 1 0.8 0.35 0.2 2.8max 0.1 (2.5) (1.0) SANYO : QIP44M(10X10) No.A1257-3/18 LV3313PM L4M L4P LSEL0 LVRIN LCT LF3C1 LF1C1 LF1C2 LF1C3 LVROUT LFIN Pin Assignment 33 32 31 30 29 28 27 26 25 24 23 L3 34 22 LFOUT L2 35 21 LROUT L1 36 20 AVSS VDD 37 19 CE MUTE 38 18 DI TEST 39 PH 40 VREF 41 R1 42 14 DVSS R2 43 13 RROUT R3 44 12 RFOUT LV3313PM 17 CL 16 OSC Top view 1 2 3 4 5 6 7 8 9 10 11 R4M R4P RSELO RVRIN RCT RF3C1 RF1C1 RF1C2 RF1C3 RVROUT RFIN 15 VREG No.A1257-4/18 R1 R2 R3 + + 40 + 39 + 38 VREF 37 PH 36 DIFF INPUT SELECT BIAS VOLTAGE CIRCUIT INPUT SELECTOR RVREF LVREF INPUT GAIN + VOLUME SOFT MUTE ZERO CROSS DET 2BAND EQ OSC CONTROL CIRCUIT 41 42 13 12 FADER VOLUME FADER VOLUME 14 23 11 10 43 9 8 7 6 5 30 4 3 2 1 + FADER VOLUME CCB INTERFACE FADER VOLUME 15 R4P R4M + 35 LOGIC CIRCUIT 2BAND EQ 24 16 + 34 ZERO CROSS DET 28 19 18 17 + 33 MUTE CIRCUIT 31 20 TEST L4M 32 21 MUTE L4P 22 VDD LSELO 29 L1 LVRIN 27 + LCT 26 L2 SOFT MUTE LF3C1 VOLUME LF1C1 INPUT GAIN LF1C2 25 + INPUT SELECTOR LF1C3 DIFF INPUT SELECT LVROUT L3 + + LFIN + + + PA PA + RFOUT + PA PA μCOM RROUT DVSS + VREG OSC CL DI CE AVSS + LROUT + LFOUT LV3313PM Block Diagram RFIN RVROUT RF1C3 RF1C2 RF1C1 RF3C1 RCT RVRIN RSELO 44 No.A1257-5/18 LV3313PM Application Circuit 0.1μF 1μF 1μF 4.7kΩ 68kΩ 220pF 2700pF + + + 1μF + + 33 32 31 30 29 28 27 26 25 24 23 L4P LSELO LVRIN LCT LF3C1 LF1C1 LF1C2 LF1C3 LVROUT LFIN 10μF L4M 0.1μF 0.1μF 34 L3 LFOUT 22 + 10μF 35 L2 LROUT 21 10μF 36 L1 AVSS 20 1μF 37 VDD + PA + 1μF + PA + 1μF CE 19 38 MUTE DI 18 39 TEST CL 17 40 PH μCOM OSC 16 0.47μF + 41 VREF VREG 15 22μF + 42 R1 DVSS 14 43 R2 RROUT 13 1μF + + PA + PA 10μF R4P RSELO RVRIN RCT RF3C1 RF1C1 RF1C2 RF1C3 RVROUT RFOUT 12 R4M 1μF 1 2 3 4 5 6 7 8 9 10 11 44 R3 1μF + 1μF 1μF + 10μF RFIN + + 1μF 1μF 0.1μF 0.1μF + 220pF 2700pF + 10μF 68kΩ 4.7kΩ 0.1μF No.A1257-6/18 LV3313PM Control System Timing and Data Format The LV3313PM is controlled by applying the stipulated data to the CL, DI and CE pins. The data consists of a total of 104 bits, of which 8 bits are the device address, 96 bits are the control data. CE B0 DI B1 B2 B3 A0 A1 A2 A3 D0 D1 D2 D3 D4 D90 D91 D92 D93 D94 D95 D5 CL data 1μs 1μs 1μs min min min CE 1μs min 1μs min CL DI 1μs ≤ TDEST tr CE tr tf CL DI tr, tf Send to data Address code Data setting (96bit) B0 to B3, A0 to A3 D0 to D95 Address code B0 B1 B2 B3 A0 A1 A2 A3 1 0 0 0 0 0 0 1 No.A1257-7/18 LV3313PM Data setting Input switching control D0 D1 D2 Operation 0 0 0 INIT 1 0 0 L1 (R1) 0 1 0 L2 (R2) 1 1 0 L3 (R3) 0 0 1 L4 (R4) Input gain control D3 D4 D5 D6 D7 Lch D8 D9 D10 D11 D12 Rch 0 0 0 0 0 0dB 1 0 0 0 0 +1dB 0 1 0 0 0 +2dB 1 1 0 0 0 +3dB 0 0 1 0 0 +4dB 1 0 1 0 0 +5dB 0 1 1 0 0 +6dB 1 1 1 0 0 +7dB 0 0 0 1 0 +8dB 1 0 0 1 0 +9dB 0 1 0 1 0 +10dB 1 1 0 1 0 +11dB 0 0 1 1 0 +12dB 1 0 1 1 0 +13dB 0 1 1 1 0 +14dB 1 1 1 1 0 +15dB 0 0 0 0 1 +16dB 1 0 0 0 1 +17dB 0 1 0 0 1 +18dB No.A1257-8/18 LV3313PM Volume control (10dB to -43dB) D13 D14 D15 D16 D17 D18 D19 D20 Lch D21 D22 D23 D24 D25 D26 D27 D28 Rch 0 1 1 0 1 1 1 0 10dB 1 1 1 0 1 1 1 0 9dB 0 0 0 1 1 1 1 0 8dB 1 0 0 1 1 1 1 0 7dB 0 1 0 1 1 1 1 0 6dB 1 1 0 1 1 1 1 0 5dB 0 0 1 1 1 1 1 0 4dB 1 0 1 1 1 1 1 0 3dB 0 1 1 1 1 1 1 0 2dB 1 1 1 1 1 1 1 0 1dB 0 0 0 0 0 0 0 0 0dB 1 0 0 0 0 0 0 0 -1dB 0 1 0 0 0 0 0 0 -2dB 1 1 0 0 0 0 0 0 -3dB 0 0 1 0 0 0 0 0 -4dB 1 0 1 0 0 0 0 0 -5dB 0 1 1 0 0 0 0 0 -6dB 1 1 1 0 0 0 0 0 -7dB 0 0 0 1 0 0 0 0 -8dB 1 0 0 1 0 0 0 0 -9dB 0 1 0 1 0 0 0 0 -10dB 1 1 0 1 0 0 0 0 -11dB 0 0 1 1 0 0 0 0 -12dB 1 0 1 1 0 0 0 0 -13dB 0 1 1 1 0 0 0 0 -14dB 1 1 1 1 0 0 0 0 -15dB 0 0 0 0 1 0 0 0 -16dB 1 0 0 0 1 0 0 0 -17dB 0 1 0 0 1 0 0 0 -18dB 1 1 0 0 1 0 0 0 -19dB 0 0 1 0 1 0 0 0 -20dB 1 0 1 0 1 0 0 0 -21dB 0 1 1 0 1 0 0 0 -22dB 1 1 1 0 1 0 0 0 -23dB 0 0 0 1 1 0 0 0 -24dB 1 0 0 1 1 0 0 0 -25dB 0 1 0 1 1 0 0 0 -26dB 1 1 0 1 1 0 0 0 -27dB 0 0 1 1 1 0 0 0 -28dB 1 0 1 1 1 0 0 0 -29dB 0 1 1 1 1 0 0 0 -30dB 1 1 1 1 1 0 0 0 -31dB 0 0 0 0 0 1 0 0 -32dB 1 0 0 0 0 1 0 0 -33dB 0 1 0 0 0 1 0 0 -34dB 1 1 0 0 0 1 0 0 -35dB 0 0 1 0 0 1 0 0 -36dB 1 0 1 0 0 1 0 0 -37dB 0 1 1 0 0 1 0 0 -38dB 1 1 1 0 0 1 0 0 -39dB 0 0 0 1 0 1 0 0 -40dB 1 0 0 1 0 1 0 0 -41dB 0 1 0 1 0 1 0 0 -42dB 1 1 0 1 0 1 0 0 -43dB No.A1257-9/18 LV3313PM Volume control (-44dB to -) D13 D14 D15 D16 D17 D18 D19 D20 Lch D21 D22 D23 D24 D25 D26 D27 D28 Rch 0 0 1 1 0 1 0 0 -44dB 1 0 1 1 0 1 0 0 -45dB 0 1 1 1 0 1 0 0 -46dB 1 1 1 1 0 1 0 0 -47dB 0 0 0 0 1 1 0 0 -48dB 1 0 0 0 1 1 0 0 -49dB 0 1 0 0 1 1 0 0 -50dB 1 1 0 0 1 1 0 0 -51dB 0 0 1 0 1 1 0 0 -52dB 1 0 1 0 1 1 0 0 -53dB 0 1 1 0 1 1 0 0 -54dB 1 1 1 0 1 1 0 0 -55dB 0 0 0 1 1 1 0 0 -56dB 1 0 0 1 1 1 0 0 -57dB 0 1 0 1 1 1 0 0 -58dB 1 1 0 1 1 1 0 0 -59dB 0 0 1 1 1 1 0 0 -60dB 1 0 1 1 1 1 0 0 -61dB 0 1 1 1 1 1 0 0 -62dB 1 1 1 1 1 1 0 0 -63dB 0 0 0 0 0 0 1 0 -64dB 1 0 0 0 0 0 1 0 -65dB 0 1 0 0 0 0 1 0 -66dB 1 1 0 0 0 0 1 0 -67dB 0 0 1 0 0 0 1 0 -68dB 1 0 1 0 0 0 1 0 -69dB 0 1 1 0 0 0 1 0 -70dB 1 1 1 0 0 0 1 0 -71dB 0 0 0 1 0 0 1 0 -72dB 1 0 0 1 0 0 1 0 -73dB 0 1 0 1 0 0 1 0 -74dB 1 1 0 1 0 0 1 0 -75dB 0 0 1 1 0 0 1 0 -76dB 1 0 1 1 0 0 1 0 -77dB 0 1 1 1 0 0 1 0 -78dB 1 1 1 1 0 0 1 0 -79dB 0 0 0 0 1 0 1 0 - No.A1257-10/18 LV3313PM Tone block Treble GAIN D29 D30 D31 D32 Lch D33 D34 D35 D36 Rch 0 1 1 1 +12dB 1 0 1 1 +10dB 0 0 1 1 +8dB 1 1 0 1 +6dB 0 1 0 1 +4dB 1 0 0 1 +2dB 0 0 0 0 0dB 1 0 0 0 -2dB 0 1 0 0 -4dB 1 1 0 0 -6dB 0 0 1 0 -8dB 1 0 1 0 -10dB 0 1 1 0 -12dB D37 D38 D39 D40 Lch D41 D42 D43 D44 Rch 0 1 1 1 +12dB 1 0 1 1 +10dB 0 0 1 1 +8dB 1 1 0 1 +6dB 0 1 0 1 +4dB 1 0 0 1 +2dB 0 0 0 0 0dB 1 0 0 0 -2dB 0 1 0 0 -4dB 1 1 0 0 -6dB 0 0 1 0 -8dB 1 0 1 0 -10dB 0 1 1 0 -12dB Bass GAIN No.A1257-11/18 LV3313PM Fader block D45 D46 D47 D48 D49 D50 LFOUT D51 D52 D53 D54 D55 D56 LROUT D57 D58 D59 D60 D61 D62 RFOUT D63 D64 D65 D66 D67 D68 RROUT 0 0 0 0 0 0 0dB 1 0 0 0 0 0 -1dB 0 1 0 0 0 0 -2dB 1 1 0 0 0 0 -4dB 0 0 1 0 0 0 -6dB 1 0 1 0 0 0 -8dB 0 1 1 0 0 0 -10dB 1 1 1 0 0 0 -12dB 0 0 0 1 0 0 -14dB 1 0 0 1 0 0 -16dB 0 1 0 1 0 0 -18dB 1 1 0 1 0 0 -20dB 0 0 1 1 0 0 -30dB 1 0 1 1 0 0 -45dB 0 1 1 1 0 0 -60dB 1 1 1 1 0 0 - Loudness control D69 Operation 0 off 1 on Zero cross control D70 Operation 0 off 1 on Zero cross signal detection block control D71 Operation 0 Input gain 1 Volume D72 Operation 0 Manual detection 1 Automatic detection D73 D74 0 0 Zero-cross signal detection timer overflow settings D75 D76 Operation 0 0 Timer time 10ms 1 0 Timer time 20ms 0 1 Timer time 40ms 1 1 Timer time 80ms No.A1257-12/18 LV3313PM Soft mute control D77 Operation 0 Soft mute mode off 1 Soft mute mode on D78 Operation 0 mute set off 1 mute set on D79 D80 Operation 0 0 normal mode 1 0 test mode Soft mute settling time select control D81 D82 Operation 0 0 mute time 0.64ms 1 0 mute time 5.12ms 0 1 mute time 40ms 1 1 mute time 80ms D83 D84 D85 D86 D87 0 0 0 0 0 D88 D89 D90 D91 D92 D93 D94 D95 0 0 0 0 0 0 0 0 Test mode block No.A1257-13/18 LV3313PM Pin Functions Pin No. Pin name 36 L1 35 L2 34 L3 42 R1 43 R2 44 R3 Function Equivalent Circuit Single end input pins. VDD + - LVref RVref 33 L4M 32 L4P 1 R4M 2 R4P Differential input pins. VDD M + VDD P LVref RVref 31 LSELO 3 RSELO Input selector output pins. VDD + - 30 LVRIN 4 RVRIN Main volume input pins. VDD + - LVref RVref 29 LCT 5 RCT 24 LVROUT 10 RVROUT Loudness function pins. VDD Tone output pins. VDD + 23 LFIN Fader block input pins. 11 RFIN Drive at low impedance. 22 LFOUT Fader output pins.Attenuation is possible 21 LROUT separately for the front end and rear end. 12 RFOUT 13 RROUT VDD VDD + Continued on next page. No.A1257-14/18 LV3313PM Continued from preceding page. Pin No. 41 Pin name Vref Function Equivalent Circuit Connect a capacitor of a few tens of uF between Vref and AVSS (VSS) as a 0.55  VDD VDD voltage generator, current ripple countermeasure. + LVref RVref 15 VREG Internal logic voltage pin. VDD + 37 VDD Power supply pin. 20 AVSS Ground pin. 38 MUTE External muting control pin. VDD Setting this pin to VSS level sets forcibly fader volume block to - level. 27 LF1C1 Capacitor connection pins for configuring 26 LF1C2 equalizer bass band filter. 25 LF1C3 Connect a capacitor between LF1C1 (RF1C1) 7 RF1C1 and LF1C2 (RF1C2), and between 8 RF1C2 LF1C2 (RF1C2) and LF1C3 (RF1C3). 9 RF1C3 VDD + - VDD VDD F1C1 F1C3 VDD F1C2 Vref 28 LF3C1 Capacitor connection pins for configuring 6 RF3C1 equalizer treble band filter. VDD Connect a high band compensation capacitor between LF3C1 (RF3C1) and VSS. 17 CL Input pin for serial data and clock used for 18 DI control. 19 CE F3C1 VDD Chip enable pin.Data is written to the internal latch and the analog switches are operated when the level changes from High to Low. Data transfer is enabled when the level is High. Continued on next page. No.A1257-15/18 LV3313PM Continued from preceding page. Pin No. Pin name 39 TEST 14 DVSS 16 OSC Function Equivalent Circuit IC test pin. Normally this pin is OPEN. Logic system ground pin. External oscillat input pin. Normally this pin is OPEN. 40 PH Automatic zero cross detection pin. VDD VDD No.A1257-16/18 LV3313PM Usage Cautions (1) Data Transmission at power on  The status of internal analog switches is unstable at power on. Therefore, perform muting or some other countermeasure until the data has been set.  At power on, initial setting data must be sent once in order to stabilize the bias of each block in a short time. (2) Description of zero cross switching circuit operation The LV3313PM have a function to switch zero cross comparator signal detection locations, enabling the selection of the optimum detection location for blocks whose data is to be updated.Basically, the switching noise can be minimized by inputting the signal immediately following the block whose data is to be updated to the zero cross comparator, so it is necessary to switch the detection location every time. Input gain Volume Switch Zero cross comparator LV3313PM zero cross detection circuit (3) Zero Cross Switching Control method The zero cross switching control method consists of setting the zero cross control bits to the zero cross detection mode, and specifying the detection blocks before transmitting the data. These control bits are latched immediately following data transfer, that is to say beforehand in sync with the falling edge of CE, so when updating data of volumes, etc., it is possible to perform mode setting and zero cross switching with one data transfer. (4) Soft mute operation The LV3313PM have a soft mute function for low switching noise, when this mute function set operation. (mute/unmute function select) The Soft mute time can be selected by send to CCB control. (0.6ms, 5ms, 40ms, 80ms) A soft mute function can be implemented by set to soft mute on. (Set to mute on/off) Soft mute time Soft mute time No.A1257-17/18 LV3313PM ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A1257-18/18