LV8481CS-TE-L-H

Ordering number : ENA1600 Bi-CMOS IC LV8481CS Saturated Driver with 2 channels + Constant Current Driver Overview The LV8481CS is low-voltage motor driver with a saturated driver with 2 channels + constant current driver. Since it is in wafer level package, this IC is optimized for the stepping motor driver and shutter driver of various portable equipments including the mobile phones with camera. Functions • Saturated driver H bridge with 2 channels + Constant current driver. • I2C bus interface • Built-in AF stepping motor sequence logic (enabling 2-phase excitation and 1-2 phase excitation) • Built-in lens home position sequence logic • Enabling power-saving by MOS process • Built-in 4 bit DAC for constant current • Built-in constant current detection resistance • Wafer level package. WLP10 (0.97mm × 2.47mm × 0.5mmt) • Built-in thermal shutdown circuit and LVS circuit. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC, VM max Output applied voltage VOUT max Input applied voltage VIN max ENA, SCL, SDA GND pin flow-out current IGND Per channel 400 mA Allowable power dissipation Pd max With specified substrate * 550 mW Operating temperature Topr -30 to +85 °C Storage temperature Tstg -40 to +150 °C OUT1, OUT2, OUT3, OUT4, OUT5 5.0 V 5.0 V -0.3 to +5.0 V * Specified substrate : 50.0mm × 50.0mm ×1.6mm, glass epoxy 1 layers printed circuit board Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. D0209 SY PC 20091020-S00001 No.A1600-1/13 LV8481CS Allowable Operating Conditions at Ta = 25°C Parameter Symbol Supply voltage VCC High level input voltage VIH Low level input voltage VIL Conditions Ratings Unit 2.4 to 4.5 V 0.4 × VCC to V to VCC × 0.13 V ENA, SCL and SDA Electrical Characteristics at Ta = 25°C, VCC = 2.8V Parameter Symbol Ratings Conditions min Supply current typ Unit max ICCO EN = 0V 0.1 1 uA ICCO1 EN = 3V 1.2 1.8 mA Ron11 VCC = 3.0V (Sum of the upper and lower side outputs) EN = 3.0V, IOUT = 100mA 2.7 3.3 Ω Ron12 VCC = 4.5V (Sum of the upper and lower side outputs) EN = 3.0V, IOUT = 100mA 2.1 2.6 Ω Ron21 VCC = 3.0V (Sum of the upper and lower side outputs + RF (0.5Ω)) EN = 3.0V, IOUT = 100mA 2.7 3.2 Ω Ron22 VCC = 4.5V (Sum of the upper and lower side outputs + RF (0.5Ω)) EN = 3.0V, IOUT = 100mA 2.1 2.55 Ω Output constant current DAC1 IOUT1 D3-D0code : 0000 260 mA Output constant current DAC2 IOUT2 D3-D0code : 0001 250 mA Output constant current DAC3 IOUT3 D3-D0code : 0010 240 mA Output constant current DAC4 IOUT4 D3-D0code : 0011 230 mA Output constant current DAC5 IOUT5 D3-D0code : 0100 220 mA Output constant current DAC6 IOUT6 D3-D0code : 0101 210 mA Output constant current DAC7 IOUT7 D3-D0code : 0110 200 mA Output constant current DAC8 IOUT8 D3-D0code : 0111 190 mA Output constant current DAC9 IOUT9 D3-D0code : 1000 180 mA Output constant current DAC10 IOUT10 D3-D0code : 1001 170 mA Output constant current DAC11 IOUT11 D3-D0code : 1010 160 mA Output constant current DAC12 IOUT12 D3-D0code : 1011 150 mA Output constant current DAC13 IOUT13 D3-D0code : 1100 140 mA Output constant current DAC14 IOUT14 D3-D0code : 1101 130 mA Output constant current DAC15 IOUT15 D3-D0code : 1110 120 mA Output constant current DAC16 IOUT16 D3-D0code : 1111 110 mA Output turn ON time Traise OUT1-OUT4 1 3 Output turn OFF time Tfall OUT1-OUT4 0.2 1 us AF PLS period Taf 2 2.2 ms Input curren IIN VIN = 3V 0 1 uA SDA pin low level output VOL IO = 300uA 0.2 0.3 V Time of onset of movements TI2CSH I2C comand SH operation 10 us after receiving I2C communication TI2CAF I2C comand AF sequence operation 1.2 ms 6 ms Output ON resistance 1 (out1 to out3) Output ON resistance 2 (out4 to out5 + sence R) 2 Thermal shut down operation 1.8 us TI CDP I2C comand Defaultposition sequence operation TTSD ENA = 3V Design target value 175 °C TΔTSD ENA = 3V Design target value 35 °C temperature Hysteresis (Assured design target) * : Design target value, not to be measured at production test. No.A1600-2/13 LV8481CS Package Dimensions unit : mm (typ) 3362 SIDE VIEW BOTTOM VIEW 0.235 TOP VIEW 5 4 3 0.27 1 0.235 0.5 0.5 MAX 0.14 SIDE VIEW SANYO : WLP10(2.47X0.97) Pd max -- Ta 0.8 Allowable power dissipation, Pd max - W 2 0.5 0.97 2.47 Specified board:50.0 × 50.0 × 1.6mm3 glass epoxy 0.6 0.55 0.4 0.29 0.2 0 --30 0 30 60 90 120 Ambient temperature, Ta - C Pin Assignment 5 4 3 2 1 1pin mark 0.5 A 0.5 0.97 B 2.47 1pin mark 1 2 Ball side view 3 4 5 A OUT5 VCC ENA SDA SCL B GND OUT4 OUT3 OUT2 OUT1 Pin No. Pin Name A1 OUT5 A2 VCC A3 ENA A4 SDA A5 SCL B1 GND B2 OUT4 B3 OUT3 B4 OUT2 B5 OUT1 Top view No.A1600-3/13 LV8481CS Block Diagram VCC ENA OUT1 AF OUT2 S/P Conversion Control SDA I2C Interface SCL VCC OUT3 OUT4 GND VCC SH R_sense + 4bit DAC 1.3V OUT5 + R_sense LVS TSD No.A1600-4/13 LV8481CS Serial Bus Communication Specifications I2C serial transfer timing conditions Standard mode twH SCL th1 twL th2 tbus SDA th1 ts2 ts1 ts3 Resend start condition Start condition ton Stop condition toff Input waveform condition Standard mode Parameter symbol Conditions min typ SCL clock frequency Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 4.7 ts2 Setup time of SDA with respect to the rising edge of SCL 250 ns ts3 Setup time of SCL with respect to the rising edge of SDA 4.0 us th1 Hold time of SDA with respect to the falling edge of SDA 4.0 us th2 Hold time of SDA with respect to the falling edge of SCL 0 us twL SCL low period pulse width 4.7 us twH SCL high period pulse width 4.0 ton SCL, SDA (input) rising time 1000 ns toff SCL, SDA (input) falling time 300 ns tbus Interval between stop condition and start condition Pulse width Input waveform conditions Bus free time 100 unit fscl Data hold time 0 max SCL clock frequency kHz us us 4.7 us High-speed mode Parameter Symbol Conditions min typ SCL clock frequency Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 0.6 ts2 Setup time of SDA with respect to the rising edge of SCL 100 ns ts3 Setup time of SCL with respect to the rising edge of SDA 0.6 us th1 Hold time of SDA with respect to the falling edge of SDA 0.6 us th2 Hold time of SDA with respect to the falling edge of SCL 0.08 us twL SCL low period pulse width 1.3 us twH SCL high period pulse width 0.6 ton SCL, SDA (input) rising time 300 ns toff SCL, SDA (input) falling time 300 ns tbus Interval between stop condition and start condition Pulse width Input waveform conditions Bus free time 1.3 400 unit fscl Data hold time 0 max SCL clock frequency kHz us us us No.A1600-5/13 LV8481CS 2 I C bus transmission method Start and stop conditions The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a data transfer operation. SCL SDA ts2 th2 When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is started when SDA is changed from high to low while SCL and SDA are high. Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is high. Start condition Stop condition th1 th3 SCL SDA Data transfer and acknowledgement response After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I2C bus, a unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave address and to the command (R/W) indicating the transfer direction of the subsequent data. Every time 8 bits of data for each byte are transferred, the ACK signal is sent from the receiving end to the sending end. Immediately after the clock pulse of SCL bit 8 in the data transferred has fallen to low, SDA at the sending end is released, and SDA is set to low at the receiving end, causing the ACK signal to be sent. When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status, the receiving end releases SDA at the falling edge of the ninth SCL clock. Start M S B Slave address L S B W A C K M S B Data L S B A C K M S B Data L S B A C K Stop SCL 1st byte SDA (WRITE) S7 S6 S5 S4 S3 S2 S1 RW 3rd byte A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 RW : 1/0 Number of Slave Address is 0110010. (S7→S1) No.A1600-6/13 LV8481CS Serial Map Register Address Data A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 1 D7 D6 D5 D4 D3 0 0 0 FL × 0 0 0 0 0 × × × × × 0 0 0 0 0 × × × × 0 0 0 0 D2 D1 D0 0 0 0 AFMODE [7 : 0] 0 0 AFMODE [5 : 3] HOLD time set [2 : 0] 0 0 0 SHMODE [2 : 0] 0 0 0 CURRENTMODE [3 : 0] 0 0 0 0 Upper : Register name Lower : Default value *Caution : address 00000111 is IC testmode. This address is out of use. Serial Each Mode Settings Rotational Direction Setting 0 0 0 D0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Rotational direction 0 CW 1 CCW AF ON/OFF Setting 0 0 0 0 D1 0 ON/OFF 0 Standby mode 1 Operation mode AF counter Reset 0 0 0 0 0 D2 Counter Reset 0 Reset on 1 Reset off No.A1600-7/13 LV8481CS Step Number Setting 0 0 0 0 0 0 0 0 0 D7 D6 D7 (32P) D6 (16P) D5 (8P) D4 (4P) D3 (2P) Number of steps 0 0 0 0 0 2step 0 0 0 0 1 4step 0 0 0 1 0 6step 0 0 0 1 1 8step 0 0 1 0 0 10step 0 0 1 0 1 12step 0 0 1 1 0 14step 0 0 1 1 1 16step 0 1 0 0 0 18step 0 1 0 0 1 20step 0 1 0 1 0 22step 0 1 0 1 1 24step 0 1 1 0 0 26step 0 1 1 0 1 28step 0 1 1 1 0 30step 0 1 1 1 1 32step 1 0 0 0 0 34step 1 0 0 0 1 36step 1 0 0 1 0 38step 1 0 0 1 1 40step 1 0 1 0 0 42step 1 0 1 0 1 44step 1 0 1 1 0 46step 1 0 1 1 1 48step 1 1 0 0 0 50step 1 1 0 0 1 52step 1 1 0 1 0 54step 1 1 0 1 1 56step 1 1 1 0 0 58step 1 1 1 0 1 60step 1 1 1 1 0 62step 1 1 1 1 1 64step Note): D3 : 2Pulse D4 : 4Pulse D5 : 8Pulse D6 : 16Pulse D7 : 32Pulse D5 D4 D3 D2 D1 D0 on/off (2step) setting register on/off (4step) setting register on/off (8step) setting register on/off (16step) setting register on/off (32step) setting register No.A1600-8/13 LV8481CS AF HOLDTIME Setting 0 0 0 0 0 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 HOLD PULSE Number 1 (at AF sequence) 0 0 0 1Puls (2msec/1msec) 1Puls (10msec/5msec) 0 0 1 2Puls (4msec/2msec) 2Puls (20msec/10msec) 0 1 0 4Puls (8msec/4msec) 4Puls (40msec/20msec) 0 1 1 5Puls (10msec/5msec) 5Puls (50msec/25msec) 1 0 0 8Puls (16msec/8msec) 8Puls (80msec/40msec) 1 0 1 16Puls (32msec/16msec) 16Puls (160msec/80msec) 1 1 0 32Puls (64msec/32msec) 32Puls (320msec/160msec) 1 1 1 1Puls (2msec/1msec) 1Puls (10msec/5msec) D2 D1 D0 HOLD PULSE Number (at Default position sequence) Note) : HOLDTIME value make a written (2-phase excitation/1-2 phase excitation). AF Excitation Setting 0 0 0 0 0 D3 Excitation system 0 2-phase excitation 1 1-2 phase excitation 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 1 D7 D6 D5 D4 D3 D2 D1 D0 Default position sequence setting 0 0 0 0 0 0 D4 ON/OFF 0 Off 1 Default position sequence ON Default position and AF sequence + steps Setting 0 0 0 0 0 D5 +64step (on/off) 0 Off 1 +64step 0 0 0 Further note : When the pulses of 64 steps or more in total are set in Default position sequence and AF sequence and the flag of D5 is “1”, the pulse of the number of AFsteps + 64steps can be set. AF sequence and Default position sequence Flag 0 0 0 0 0 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 The situation between Standby state and Under execution of the sequences AF and Default position can be confirmedin the state of “D7”. D7 FL 0 Standby state 1 Under execution When the sequence ends, FL automatically becomes zero. No.A1600-9/13 LV8481CS AF sequence diagram Hold time Standby (current-carrying off) Lens stroke Hold time Driver operation Position Holdcurrent-carrying By target steps Step operation Target position Hold- Current-carrying off current-carrying AF sequence END I2C Control signal reception (1) Set default value at OUT1 = H, OUT2 = L, OUT3 = H and OUT4 = L. (2) STMspeed at the AF sequence becomes 500pps. (3) The hold current-carrying time, it is the same time both front and rear times. Default Position Sequence diagram Hold time Hold time Standby (current-carrying off) Lens position Lens Default position Driver operation Hold current-carrying To the lens default position, Step operation Default position CurrentHold-current-carrying carrying off I2C control signal reception Default position sequence END Further note : (1) When the flag of D4 in the address 00000001 of a default position sequence is “1”, whether or not the total of a default position sequence is 65step or more is set by using a flag in D5. The command is transmitted by the I2C communication after setting HOLD time. (2) The number of step, the rotational direction and AFon/off are set in the address 00000000. And, a default position sequence is performed at the IC side when the data is transmitted by using I2C communication. (3) STMspeed in a default position sequence becomes 100pps. (4) Hold current-carrying time, it becomes congruent with the previous or nest time. No.A1600-10/13 LV8481CS SH bridge, OUT4 to 5 Operation Setting 1 0 0 0 0 0 0 1 0 D7 D6 D5 D4 D1 D0 OUT4 OUT5 0 0 Z Z Standby All channels OFF 0 1 H L Constant current between OUT4 and OUT5 1 0 L H Constant current between OUT5 and OUT4 1 1 L L Brake Logic D3 D2 D1 D0 Bridge state • Constant current is driven When applying current between channels OUT4 and OUT5. SH bridge, on/off Setting 1 0 0 0 0 D2 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 ON/OFF 0 Standby 1 Operation Constant Current Setting 1 0 0 0 0 D3 D2 D1 D0 Constant current value 0 0 0 0 260mA 0 0 0 1 250mA 0 0 1 0 240mA 0 0 1 1 230mA 0 1 0 0 220mA 0 1 0 1 210mA 0 1 1 0 200mA 0 1 1 1 190mA 1 0 0 0 180mA 1 0 0 1 170mA 1 0 1 0 160mA 1 0 1 1 150mA 1 1 0 0 140mA 1 1 0 1 130mA 1 1 1 0 120mA 1 1 1 1 110mA No.A1600-11/13 LV8481CS AF sequence (2-phase excitation drive) (1 cycle = 4CLK) CLK Position a d b c d a 100% L1 0 -100% 100% 0 L2 -100% AF sequence a→b→c→d→a (Clockwise direction) AF sequence (1-2 phase excitation drive) (1 cycle = 8CLK) CLK Position L1 a b c d e f g h a b c d 100% 0 -100% L2 100% 0 -100% AF sequence a→b→c→d→e→f→g→h→a (Clockwise direction) No.A1600-12/13 LV8481CS SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2009. Specifications and information herein are subject to change without notice. PS No.A1600-13/13