DATA SHEET
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Noninverting 3-State Buffer
MARKING
DIAGRAMS
MC74VHC1G125,
MC74VHC1GT125
The MC74VHC1G125 / MC74VHC1GT125 is a single
non−inverting 3−state buffer in tiny footprint packages. The
MC74VHC1G125 has CMOS−level input thresholds while the
MC74VHC1GT125 has TTL−level input thresholds.
The internal circuit is composed of three stages, including a buffered
3−state output which provides high noise immunity and stable output.
The input structures provide protection when voltages up to 5.5 V
are applied, regardless of the supply voltage. This allows the device to
be used to interface 5 V circuits to 3 V circuits. Some output structures
also provide protection when VCC = 0 V and when the output voltage
exceeds VCC. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
•
•
•
Designed for 2.0 V to 5.5 V VCC Operation
3.5 ns tPD at 5 V (typ)
Inputs/Outputs Over−Voltage Tolerant up to 5.5 V
IOFF Supports Partial Power Down Protection
Source/Sink 8 mA at 3.0 V
Available in SC−88A, SC−74A, TSOP−5, SOT−953 and UDFN6
Packages
Chip Complexity < 100 FETs
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
XX MG
G
SC−74A
DBV SUFFIX
CASE 318BQ
XXX MG
G
TSOP−5
DT SUFFIX
CASE 483
5
1
5
XX MG
G
1
SOT−953
P5 SUFFIX
CASE 527AE
Features
•
•
•
•
•
•
SC−88A
DF SUFFIX
CASE 419A
1
1
1
UDFN6
1.45 x 1.0
CASE 517AQ
XM
UDFN6
1.2 x 1.0
CASE 517AA
XM
UDFN6
1.0 x 1.0
CASE 517BX
XX
M
G
XM
XM
1
= Specific Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
OE
EN
A
*Date Code orientation and/or position may
vary depending upon manufacturing location.
Y
Figure 1. Logic Symbol
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
April, 2022 − Rev. 21
1
Publication Order Number:
MC74VHC1G125/D
MC74VHC1G125, MC74VHC1GT125
VCC
OE
1
5
A
VCC
A
5
1
OE
1
6
VCC
A
2
5
NC
GND
3
4
Y
GND
2
2
GND
Y
4
3
Y
OE
4
3
(SOT−953)
(SC−88A / TSOP−5 / SC−74A)
(UDFN6)
Figure 2. Pinout (Top View)
PIN ASSIGNMENT
(SC−88A / TSOP−5 / SC−74A)
PIN ASSIGNMENT (SOT−953)
PIN ASSIGNMENT (UDFN)
Pin
Function
Pin
Function
Pin
Function
1
OE
1
A
1
OE
2
A
2
GND
2
A
3
GND
3
OE
3
GND
4
Y
4
Y
4
Y
5
VCC
5
VCC
5
NC
6
VCC
FUNCTION TABLE
Input
Output
OE
A
Y
L
L
L
L
H
H
H
X
Z
X = Don’t Care
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2
MC74VHC1G125, MC74VHC1GT125
MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
TSOP−5, SC−88A (NLV)
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
−0.5 to +7.0
−0.5 to +6.5
V
VIN
DC Input Voltage
TSOP−5, SC−88A (NLV)
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
−0.5 to +7.0
−0.5 to +6.5
V
−0.5 to VCC + 0.5
V
VOUT
Characteristics
DC Output Voltage (NLV)
1Gxx
1GTxx
DC Output Voltage
IIK
DC Input Diode Current
IOK
DC Output Diode Current (NLV)
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (VCC = 0 V)
−0.5 to VCC + 0.5
−0.5 to +7.0
−0.5 to +7.0
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (VCC = 0 V)
−0.5 to VCC + 0.5
−0.5 to +6.5
−0.5 to +6.5
V
VIN < GND
−20
mA
VOUT > VCC, VOUT < GND
±20
mA
VOUT < GND
−20
VOUT < GND
−20
mA
±25
mA
1Gxx
1GTxx
DC Output Diode Current
IOUT
ICC or IGND
TSTG
DC Output Source/Sink Current
DC Supply Current per Supply Pin or Ground Pin
Storage Temperature Range
±50
mA
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 secs
260
°C
TJ
Junction Temperature Under Bias
+150
°C
qJA
Thermal Resistance (Note 2)
SC−88A
SC−74A
SOT−553
SOT−953
UDFN6
377
320
324
254
154
°C/W
PD
Power Dissipation in Still Air
SC−88A
SC−74A
SOT−553
SOT−953
UDFN6
332
390
386
491
812
mW
Level 1
−
MSL
Moisture Sensitivity
FR
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
−
ESD Withstand Voltage (Note 3)
Human Body Model
Charged Device Model
2000
1000
V
±100
mA
VESD
ILatchup
Latchup Performance (Note 4)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Applicable to devices with outputs that may be tri−stated.
2. Measured with minimum pad spacing on an FR4 board, using 10mm−by−1inch, 2 ounce copper trace no air flow per JESD51−7.
3. HBM tested to ANSI/ESDA/JEDEC JS−001−2017. CDM tested to EIA/JESD22−C101−F. JEDEC recommends that ESD qualification to
EIA/JESD22−A115−A (Machine Model) be discontinued per JEDEC/JEP172A.
4. Tested to EIA/JESD78 Class II.
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3
MC74VHC1G125, MC74VHC1GT125
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
VCC
Positive DC Supply Voltage
VIN
DC Input Voltage
VOUT
Min
Max
Unit
2.0
5.5
V
0
5.5
V
0
VCC
V
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (VCC = 0 V)
0
0
0
VCC
5.5
5.5
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (VCC = 0 V)
0
0
0
VCC
5.5
5.5
V
−55
+125
°C
TSOP−5, SC−88A (NLV)
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0
0
100
20
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
VCC = 2.0 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
0
0
0
0
20
20
10
5
DC Output Voltage (NLV)
1Gxx
1GTxx
DC Output Voltage
TA
tr , tf
Operating Temperature Range
Input Rise and Fall Time
Input Rise and Fall Time
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (MC74VHC1G125)
Symbol
VIH
VIL
VOH
Parameter
Test
Conditions
High−Level Input
Voltage
Low−Level Input
Voltage
−40°C ≤ TA ≤ 85°C
TA = 25°C
−55°C ≤ TA ≤ 125°C
VCC
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
2.0
1.5
−
−
1.5
−
1.5
−
V
3.0
2.1
−
−
2.1
−
2.1
−
4.5
3.15
−
−
3.15
−
3.15
−
5.5
3.85
−
−
3.85
−
3.85
−
2.0
−
−
0.5
−
0.5
−
0.5
3.0
−
−
0.9
−
0.9
−
0.9
4.5
−
−
1.35
−
1.35
−
1.35
5.5
−
−
1.65
−
1.65
−
1.65
V
High−Level Output
Voltage
VIN = VIH or VIL
IOH = −50 mA
IOH = −50 mA
IOH = −50 mA
IOH = −4 mA
IOH = −8 mA
2.0
3.0
4.5
3.0
4.5
1.9
2.9
4.4
2.58
3.94
2.0
3.0
4.5
−
−
−
−
−
−
−
1.9
2.9
4.4
2.48
3.80
−
−
−
−
−
1.9
2.9
4.4
2.34
3.66
−
−
−
−
−
Low−Level Output
Voltage
VIN = VIH or VIL
IOL = 50 mA
IOL = 50 mA
IOL = 50 mA
IOL = 4 mA
IOL = 8 mA
2.0
3.0
4.5
3.0
4.5
−
−
−
−
−
0.0
0.0
0.0
−
−
0.1
0.1
0.1
0.36
0.36
−
−
−
−
−
0.1
0.1
0.1
0.44
0.44
−
−
−
−
−
0.1
0.1
0.1
0.52
0.52
IIN
Input Leakage
Current
VIN = 5.5 V or
GND
2.0
to 5.5
−
−
±0.1
−
±1.0
−
±1.0
mA
IOZ
3−State Output
Leakage Current
VOUT = 0 V to
5.5 V
5.5
−
−
±0.25
−
±2.5
−
±2.5
mA
IOFF
Power Off Leakage
Current (NLV)
VIN = 5.5 V
0.0
−
−
1.0
−
10
−
10
mA
Power Off Leakage
Current
VIN = 5.5 V or
VOUT = 5.5 V
0.0
−
−
1.0
−
10
−
10
mA
Quiescent Supply
Current
VIN = VCC or
GND
5.5
−
−
1.0
−
20
−
40
mA
VOL
ICC
V
V
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4
MC74VHC1G125, MC74VHC1GT125
DC ELECTRICAL CHARACTERISTICS (MC74VHC1GT125)
Symbol
VIH
VIL
Parameter
Test
Conditions
High−Level Input
Voltage
Low−Level Input
Voltage
−40°C ≤ TA ≤ 85°C
TA = 25°C
−55°C ≤ TA ≤ 125°C
VCC
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
2.0
1.0
−
−
1.0
−
1.0
−
V
3.0
1.4
−
−
1.4
−
1.4
−
4.5
2.0
−
−
2.0
−
2.0
−
5.5
2.0
−
−
2.0
−
2.0
−
2.0
−
−
0.28
−
0.28
−
0.28
3.0
−
−
0.45
−
0.45
−
0.45
4.5
−
−
0.8
−
0.8
−
0.8
V
5.5
−
−
0.8
−
0.8
−
0.8
High−Level Output
Voltage
VIN = VIH or VIL
IOH = −50 mA
IOH = −50 mA
IOH = −50 mA
IOH = −4 mA
IOH = −8 mA
2.0
3.0
4.5
3.0
4.5
1.9
2.9
4.4
2.58
3.94
2.0
3.0
4.5
−
−
−
−
−
−
−
1.9
2.9
4.4
2.48
3.80
−
−
−
−
−
1.9
2.9
4.4
2.34
3.66
−
−
−
−
−
Low−Level Output
Voltage
VIN = VIH or VIL
IOL = 50 mA
IOL = 50 mA
IOL = 50 mA
IOL = 4 mA
IOL = 8 mA
2.0
3.0
4.5
3.0
4.5
−
−
−
−
−
0.0
0.0
0.0
−
−
0.1
0.1
0.1
0.36
0.36
−
−
−
−
−
0.1
0.1
0.1
0.44
0.44
−
−
−
−
−
0.1
0.1
0.1
0.52
0.52
IIN
Input Leakage
Current
VIN = 5.5 V or
GND
2.0
to 5.5
−
−
±0.1
−
±1.0
−
±1.0
mA
IOZ
3−State Output
Leakage Current
VOUT = 0 V to
5.5 V
5.5
−
−
±0.25
−
±2.5
−
±2.5
mA
IOFF
Power Off Leakage
Current
VIN = 5.5 V or
VOUT = 5.5 V
0
−
−
1.0
−
10
−
10
mA
ICC
Quiescent Supply
Current
VIN = VCC or
GND
5.5
−
−
1.0
−
20
−
40
mA
ICCT
Increase in
Quiescent Supply
Current per Input
Pin
One Input: VIN
= 3.4 V; Other
Input at VCC or
GND
5.5
−
−
1.35
−
1.5
−
1.65
mA
VOH
VOL
V
V
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5
MC74VHC1G125, MC74VHC1GT125
AC ELECTRICAL CHARACTERISTICS
−40°C ≤ TA ≤ 85°C
TA = 25°C
Symbol
Parameter
Conditions
VCC (V)
Min
Typ
tPLH,
tPHL
Propagation Delay,
A to Y
(Figures 3 and 4)
CL = 15 pF
3.0 to 3.6
−
−
CL = 50 pF
CL = 15 pF
4.5 to 5.5
CL = 50 pF
tPZL,
tPZH
Output Enable
Time, OE to Y
(Figures 3 and 4)
CL = 15 pF
3.0 to 3.6
CL = 50 pF
CL = 15 pF
4.5 to 5.5
CL = 50 pF
tPLZ,
tPHZ
Output Disable
Time, OE to Y
(Figures 3 and 4)
CL = 15 pF
3.0 to 3.6
CL = 50 pF
CL = 15 pF
4.5 to 5.5
CL = 50 pF
CIN
COUT
Input Capacitance
Output Capacitance
Output in
High
Impedance
State
Max
Min
4.5
8.0
6.4
11.5
−
3.5
−
−
−55°C ≤ TA ≤ 125°C
Max
Min
Max
Unit
−
9.5
−
12.0
ns
−
13.0
−
16.0
5.5
−
6.5
−
8.5
4.5
7.5
−
8.5
−
10.5
4.5
8.0
−
9.5
−
11.5
−
6.4
11.5
−
13.0
−
15.0
−
3.5
5.1
−
6.0
−
8.5
−
4.5
7.1
−
8.0
−
10.5
−
6.5
9.7
−
11.5
−
14.5
−
8.0
13.2
−
15.0
−
18.0
−
4.8
6.8
−
8.0
−
10.0
−
7.0
8.8
−
10.0
−
12.0
−
4.0
10
−
10
−
10
pF
−
6.0
−
−
−
−
−
pF
ns
ns
Typical @ 25°C, VCC = 5.0 V
CPD
8.0
Power Dissipation Capacitance (Note 5)
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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6
MC74VHC1G125, MC74VHC1GT125
OPEN
VCC
Test
Switch
Position
CL, pF
RL, W
tPLH / tPHL
Open
See AC Characteristics Table
X
tPLZ / tPZL
VCC
1k
tPHZ / tPZH
GND
1k
GND
RL
OUTPUT
DUT
RT
X = Don’t Care
CL *
CL includes probe and jig capacitance
RT is ZOUT of pulse generator (typically 50 W)
f = 1 MHz
Figure 3. Test Circuit
tr = 3 ns
tf = 3 ns
90%
90%
Vmi
INPUT
VCC
VCC
Vmi
INPUT
Vmi
Vmi
10%
GND
10%
tPHL
GND
tPZL
tPLH
tPLZ
~VCC
VOH
Vmo
OUTPUT
Vmo
OUTPUT
Vmo
VOL + VY
VOL
VOL
tPLH
tPZH
tPHL
tPHZ
VOH
OUTPUT
Vmo
Vmo
VOH
VOH − VY
Vmo
OUTPUT
VOL
~0 V
Figure 4. Switching Waveforms
Vmo, V
VCC, V
Vmi, V
tPLH, tPHL
3.0 to 3.6
VCC/2
VCC/2
VCC/2
0.3
4.5 to 5.5
VCC/2
VCC/2
VCC/2
0.3
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7
tPZL, tPLZ, tPZH, tPHZ
VY, V
MC74VHC1G125, MC74VHC1GT125
ORDERING INFORMATION
Packages
Specific Device Code
Pin 1 Orientation
(See below)
Shipping†
M74VHC1G125DFT1G
SC−88A
W0
Q2
3000 / Tape & Reel
M74VHC1G125DFT1G−L22038**
SC−88A
W0
Q2
3000 / Tape & Reel
M74VHC1G125DFT2G
SC−88A
W0
Q4
3000 / Tape & Reel
M74VHC1G125DFT2G−L22038**
SC−88A
W0
Q4
3000 / Tape & Reel
NLVVHC1G125DFT1G*
SC−88A
W0
Q2
3000 / Tape & Reel
M74VHC1GT125DF1G
SC−88A
W1
Q2
3000 / Tape & Reel
M74VHC1GT125DF2G
SC−88A
W1
Q4
3000 / Tape & Reel
M74VHC1GT125DF2G−L22038**
SC−88A
W1
Q4
3000 / Tape & Reel
NLVVHC1GT125DF1G*
SC−88A
W1
Q2
3000 / Tape & Reel
NLVVHC1GT125DF2G*
SC−88A
W1
Q4
3000 / Tape & Reel
MC74VHC1G125DBVT1G
SC−74A
W0
Q4
3000 / Tape & Reel
MC74VHC1GT125DBVT1G
SC−74A
W1
Q4
3000 / Tape & Reel
M74VHC1G125DTT1G**
TSOP−5
W0
Q4
3000 / Tape & Reel
M74VHC1GT125DT1G**
TSOP−5
W1
Q4
3000 / Tape & Reel
NLVVHC1GT125DT1G*
TSOP−5
W1R
Q4
3000 / Tape & Reel
MC74VHC1G125P5T5G
SOT−953
T
Q2
8000 / Tape & Reel
MC74VHC1G125P5T5G−L22088**
SOT−953
T
Q2
8000 / Tape & Reel
MC74VHC1GT125P5T5G
(In Development)
SOT−953
TBD
Q2
8000 / Tape & Reel
MC74VHC1G125MU1TCG
(In Development)
UDFN6, 1.45 x 1.0, 0.5P
TBD
Q4
3000 / Tape & Reel
MC74VHC1GT125MU1TCG
UDFN6, 1.45 x 1.0, 0.5P
D
Q4
3000 / Tape & Reel
Device
MC74VHC1GT125MU2TCG
UDFN6, 1.2 x 1.0, 0.4P
7
Q4
3000 / Tape & Reel
MC74VHC1G125MU3TCG
(In Development)
UDFN6, 1.0 x 1.0, 0.35P
TBD
Q4
3000 / Tape & Reel
MC74VHC1GT125MU3TCG
UDFN6, 1.0 x 1.0, 0.35P
L
Q4
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
**Please refer to NLV specifications for this device.
Pin 1 Orientation in Tape and Reel
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−74A
CASE 318BQ
ISSUE B
5
1
SCALE 2:1
5X
DATE 18 JAN 2018
b
0.20 C A B
E1
5
M
4
1
2
E
3
B
0.05
A1
e
D
A
L
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE.
DIM
A
A1
b
c
D
E
E1
e
L
M
TOP VIEW
A
SIDE VIEW
DETAIL A
C
c
SEATING
PLANE
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
0.90
1.10
0.01
0.10
0.25
0.50
0.10
0.26
2.85
3.15
2.50
3.00
1.35
1.65
0.95 BSC
0.20
0.60
0_
10 _
GENERIC
MARKING DIAGRAM*
0.95
PITCH
XXX MG
G
XXX
M
G
2.40
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
5X
1.00
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
5X
0.70
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON66279G
SC−74A
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
SCALE 2:1
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DATE 17 JAN 2013
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
B
M
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
J
GENERIC MARKING
DIAGRAM*
C
K
H
XXXMG
G
SOLDER FOOTPRINT
0.50
0.0197
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
mm Ǔ
ǒinches
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42984B
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88A (SC−70−5/SOT−353)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN6, 1.2x1.0, 0.4P
CASE 517AA−01
ISSUE D
1
SCALE 8:1
EDGE OF PACKAGE
2X
0.10 C
ÉÉ
ÉÉ
ÉÉ
L1
E
DETAIL A
Bottom View
(Optional)
TOP VIEW
2X
EXPOSED Cu
0.10 C
(A3)
0.10 C
A1
A
10X
0.08 C
ÉÉÉ
ÉÉÉ
A3
DETAIL B
Side View
(Optional)
5X
XM
L
3
X
M
L2
b
0.10 C A B
0.05 C
6
= Specific Device Code
= Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
4
e
NOTE 3
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.15
0.25
1.20 BSC
1.00 BSC
0.40 BSC
0.30
0.40
0.00
0.15
0.40
0.50
GENERIC
MARKING DIAGRAM*
C
A1
6X
DIM
A
A1
A3
b
D
E
e
L
L1
L2
MOLD CMPD
SEATING
PLANE
SIDE VIEW
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
D
PIN ONE
REFERENCE
DATE 03 SEP 2010
MOUNTING FOOTPRINT*
BOTTOM VIEW
6X
6X
0.42
0.40
PITCH
0.22
1.07
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON22068D
6 PIN UDFN, 1.2X1.0, 0.4P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN6, 1.45x1.0, 0.5P
CASE 517AQ
ISSUE O
1
SCALE 4:1
A
B
D
DATE 15 MAY 2008
L
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
L1
PIN ONE
REFERENCE
0.10 C
ÉÉÉ
ÉÉÉ
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÉÉ
ÉÉ
EXPOSED Cu
TOP VIEW
0.10 C
DETAIL B
MOLD CMPD
DETAIL B
0.05 C
6X
DIM
A
A1
A2
b
D
E
e
L
L1
OPTIONAL
CONSTRUCTIONS
A
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.07 REF
0.20
0.30
1.45 BSC
1.00 BSC
0.50 BSC
0.30
0.40
−−−
0.15
MOUNTING FOOTPRINT
0.05 C
A1
SIDE VIEW
A2
e
6X
C
SEATING
PLANE
6X
0.30
PACKAGE
OUTLINE
L
1.24
3
1
DETAIL A
6X
0.53
6
4
6X
BOTTOM VIEW
b
0.10 C A B
0.05 C
NOTE 3
1
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
XM
X
M
= Specific Device Code
= Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30313E
UDFN6, 1.45x1.0, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN6, 1x1, 0.35P
CASE 517BX
ISSUE O
SCALE 4:1
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. PACKAGE DIMENSIONS EXCLUSIVE OF
BURRS AND MOLD FLASH.
A B
D
ÉÉ
ÉÉ
ÉÉ
DATE 18 MAY 2011
E
DIM
A
A1
A3
b
D
E
e
L
L1
TOP VIEW
A3
0.05 C
A
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.12
0.22
1.00 BSC
1.00 BSC
0.35 BSC
0.25
0.35
0.30
0.40
0.05 C
SIDE VIEW
A1
C
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
5X
e
5X
0.48
L
6X
0.22
3
1
L1
1.18
6
4
6X
BOTTOM VIEW
b
0.10
M
C A B
0.05
M
C
NOTE 3
0.53
1
PKG
OUTLINE
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
XM
1
X = Specific Device Code
M = Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON56787E
UDFN6, 1x1, 0.35P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−953
CASE 527AE
ISSUE E
DATE 02 AUG 2011
SCALE 4:1
X
Y
D
5
PIN ONE
INDICATOR
A
4
HE
E
1
2 3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
DIM
A
b
C
D
E
e
HE
L
L2
L3
C
TOP VIEW
SIDE VIEW
e
L
5X
5X
L3
5X
L2
MILLIMETERS
MIN
NOM
MAX
0.34
0.37
0.40
0.10
0.15
0.20
0.07
0.12
0.17
0.95
1.00
1.05
0.75
0.80
0.85
0.35 BSC
0.95
1.00
1.05
0.175 REF
0.05
0.10
0.15
−−−
−−−
0.15
GENERIC
MARKING DIAGRAM*
5X
BOTTOM VIEW
XM
b
1
0.08 X Y
X
M
SOLDERING FOOTPRINT*
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
5X
0.35
5X
0.20
= Specific Device Code
= Month Code
PACKAGE
OUTLINE
1.20
1
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON26457D
SOT−953
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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