M74VHC1GT32DFT2G

MC74VHC1GT32 2−Input OR Gate/CMOS Logic Level Shifter The MC74VHC1GT32 is an advanced high speed CMOS 2−input OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V CMOS Logic while operating at the high−voltage power supply. The MC74VHC1GT32 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1GT32 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. Features http://onsemi.com MARKING DIAGRAMS 5 1 SC−88A/SC70−5/SOT−353 DF SUFFIX CASE 419A 1 5 VN M G G M 5 1 TSOP−5/SOT23−5/SC59−5 DT SUFFIX CASE 483 VN M G 1 VN M G G 5 • • • • • • • • • High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 65; Equivalent Gates = 15 Pb−Free Packages are Available = Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. PIN ASSIGNMENT 1 2 3 4 IN B IN A GND OUT Y VCC IN B 1 5 VCC 5 IN A 2 A FUNCTION TABLE Inputs B L H L H Output Y L H H H GND 3 4 OUT Y L L H H Figure 1. Pinout (Top View) IN A IN B ≥1 OUT Y ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Figure 2. Logic Symbol © Semiconductor Components Industries, LLC, 2007 1 February, 2007 − Rev. 10 Publication Order Number: MC74VHC1GT32/D MC74VHC1GT32 MAXIMUM RATINGS Symbol VCC VIN VOUT IIK IOK IOUT ICC PD qJA TL TJ Tstg VESD DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Power dissipation in still air Thermal resistance Lead temperature, 1 mm from case for 10 s Junction temperature under bias Storage temperature ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 125°C (Note 4) SC−88A, TSOP−5 SC−88A, TSOP−5 VOUT < GND; VOUT > VCC VCC = 0 High or Low State Characteristics Value −0.5 to +7.0 −0.5 to +7.0 −0.5 to 7.0 −0.5 to VCC + 0.5 −20 +20 +25 +50 200 333 260 +150 −65 to +150 > 2000 > 200 N/A ±500 Unit V V V mA mA mA mA mW °C/W °C °C °C V ILatchup Latchup Performance mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22−A114−A 2. Tested to EIA/JESD22−A115−A 3. Tested to JESD22−C101−A 4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN VOUT TA tr , tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range Input Rise and Fall Time VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V VCC = 0 High or Low State Characteristics Min 3.0 0.0 0.0 0.0 −55 0 0 Max 5.5 5.5 5.5 VCC +125 100 20 Unit V V V °C ns/V Device Junction Temperature versus Time to 0.1% Bond Failures Junction Temperature °C 80 90 100 110 120 130 140 Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 NORMALIZED FAILURE RATE FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 ° C TJ = 120° C TJ = 100 ° C TJ = 110° C TJ = 80 ° C 100 TIME, YEARS TJ = 90 ° C 1 1 10 1000 Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 2 MC74VHC1GT32 DC ELECTRICAL CHARACTERISTICS VCC Symbol VIH Parameter Minimum High−Level Input Voltage Maximum Low−Level Input Voltage Minimum High−Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOH = −50 mA VIN = VIH or VIL IOH = −4 mA IOH = −8 mA VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOL = 4 mA IOL = 8 mA VIN = 5.5 V or GND VIN = VCC or GND Input: VIN = 3.4 V VOUT = 5.5 V Test Conditions (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 0 to 5.5 5.5 5.5 0.0 2.9 4.4 2.58 3.94 0.0 0.0 0.1 0.1 0.36 0.36 ±0.1 2.0 1.35 0.5 3.0 4.5 Min 1.4 2.0 2.0 0.53 0.8 0.8 2.9 4.4 2.48 3.80 0.1 0.1 0.44 0.44 ±1.0 20 1.50 5.0 TA = 25°C Typ Max TA ≤ 85°C Min 1.4 2.0 2.0 0.53 0.8 0.8 2.9 4.4 2.34 3.66 0.1 0.1 0.52 0.52 ±1.0 40 1.65 10 mA mA mA mA V V Max −55 ≤ TA ≤ 125°C Min 1.4 2.0 2.0 0.53 0.8 0.8 Max Unit V VIL V VOH V V VOL Maximum Low−Level Output Voltage VIN = VIH or VIL IIN ICC ICCT IOPD Maximum Input Leakage Current Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current ÎÎ Î Î ÎÎ Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ ÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎ Î Î Î Î Î ÎÎ Î Î Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î ÎÎ Î Î ÎÎ Î Î Î ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎ Î Î Î Î Î ÎÎ Î Î Î Î ÎÎ Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎ Î Î Î ÎÎ Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr = tf = 3.0ns) Symbol tPLH, tPHL Parameter Test Conditions Min TA = 25°C Typ 4.8 6.1 3.7 4.4 5.5 TA ≤ 85°C −55 ≤ TA ≤ 125°C Min Max Max 7.9 11.4 5.5 7.5 10 Min Max Unit ns Maximum Propagation Delay, Input A or B to Y VCC = 3.3 ± 0.3 V VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 9.5 13.0 6.5 8.5 10 11.5 15.5 8.0 10.0 10 CIN Maximum Input Capacitance pF Typical @ 25°C, VCC = 5.0 V 11 CPD Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC. http://onsemi.com 3 MC74VHC1GT32 Input A or B 50% tPLH Output Y 50% VCC GND tPHL VOH 50% VCC VOL Figure 4. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance Figure 5. Test Circuit ORDERING INFORMATION Device MC74VHC1GT32DFT1 M74VHC1GT32DFT1G MC74VHC1GT32DFT2 M74VHC1GT32DFT2G MC74VHC1GT32DTT1 M74VHC1GT32DTT1G Package SC−88A / SOT−353 / SC−70 SC−88A / SOT−353 / SC−70 (Pb−Free) SC−88A / SOT−353 / SC−70 SC−88A / SOT−353/ SC−70 (Pb−Free) TSOP−5 / SOT−23 / SC−59 TSOP−5 / SOT−23 / SC−59 (Pb−Free) 3000 / Tape & Reel Shipping† †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC74VHC1GT32 PACKAGE DIMENSIONS SC−88A, SOT−353, SC−70 CASE 419A−02 ISSUE J A G 5 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. S 1 2 3 −B− DIM A B C D G H J K N S D 5 PL 0.2 (0.008) M B M N J C INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC −−− 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC −−− 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 H K SOLDERING FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 mm inches 1.9 0.0748 SCALE 20:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 MC74VHC1GT32 PACKAGE DIMENSIONS TSOP−5 CASE 483−02 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 NOTE 5 2X D 5X 0.20 C A B 5 1 2 4 3 0.10 T 0.20 T L G A B S M K DETAIL Z 2X DETAIL Z J C 0.05 H T SEATING PLANE SOLDERING FOOTPRINT* 1.9 0.074 0.95 0.037 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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