MC100E111FNR2G

5 V ECL 1:9 Differential Clock Driver MC100E111 Description The MC100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within-device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. The lowest TPD delay time results from terminating only one output pair, and the greatest TPD delay time results from terminating all the output pairs. This shift is about 10–20 pS in TPD. The skew between any two output pairs within a device is typically about 25 nS. If other output pairs are not terminated, the lowest TPD delay time results from both output pairs and the skew is typically 25 nS. When all outputs are terminated, the greatest TPD (delay time) occurs and all outputs display about the same 10–20 pS increase in TPD, so the relative skew between any two output pairs remains about 25 nS. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. www.onsemi.com PLCC−28 FN SUFFIX CASE 776−02 MARKING DIAGRAM* 1 MC100E111G AWLYYWW A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. Features • • • • • • • • • • • • Guaranteed Skew Spec Differential Design VBB Output PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: > 3 kV Human Body Model Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Moisture Sensitivity: Level 3 (Pb-Free) (For Additional Information, see Application Note AND8003/D) Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 178 Devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2016 March, 2021 − Rev. 18 1 ORDERING INFORMATION Device Package Shipping† MC100E111FNG PLCC−28 (Pb-Free) 37 Units/Tube MC100E111FNR2G PLCC−28 (Pb-Free) 500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: MC100E111/D MC100E111 Q0 Q0 Q1 VCCO Q1 Q2 Q2 25 24 23 20 19 22 21 Table 1. PIN DESCRIPTION PIN VEE 26 18 Q3 EN 27 17 Q3 IN 28 16 Q4 15 VCCO Pinout: 28-Lead PLCC (Top View) VCC 1 IN 2 14 Q4 VBB 3 13 Q5 NC 4 12 Q5 5 6 7 8 Q8 Q8 Q7 VCCO 9 10 11 Q7 Q6 Q6 IN, IN EN Q0, Q0−Q8, Q8 VBB VCC, VCCO VEE NC * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 28-Lead Pinout Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 IN Q4 IN Q4 Q5 EN Q5 Q6 Q6 Q7 Q7 Q8 Q8 VBB Figure 2. Logic Symbol www.onsemi.com 2 FUNCTION ECL Differential Input Pair ECL Enable ECL Differential Outputs Reference Voltage Output Positive Supply Negative Supply No Connect MC100E111 Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 8 V 6 −6 V 50 100 mA ±0.5 mA −40 to +85 °C VCC PECL Mode Power Supply VEE = 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V Iout Output Current Continuous Surge IBB VBB Sink/Source TA Operating Temperature Range Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm PLCC−28 PLCC−28 63.5 43.5 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board PLCC−28 22 to 26 °C/W Tsol Wave Solder (Pb-Free) 265 °C VI ≤ VCC VI ≥ VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 3. 100E SERIES PECL DC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 40 60 Min 85°C Typ Max 45 60 Min Typ Max Unit 50 69 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 3975 4020 4120 3975 4020 4120 3975 4020 4120 mV VOL Output LOW Voltage (Note 2) 3190 3300 3380 3190 3300 3380 3190 3300 3380 mV VIH Input HIGH Voltage (Single-Ended) 3835 3975 4120 3835 3975 4120 3835 3975 4120 mV VIL Input LOW Voltage (Single-Ended) 3190 3355 3525 3190 3355 3525 3190 3355 3525 mV VBB Output Voltage Reference 3.64 3.75 3.62 3.74 3.62 3.74 V Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) 3.4 4.6 3.4 4.6 3.4 4.6 V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.5 0.25 0.5 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min and max vary 1:1 with VCC. www.onsemi.com 3 MC100E111 Table 4. 100E SERIES NECL DC CHARACTERISTICS (VCCx = 0.0 V; VEE = −5.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 40 60 Min 85°C Typ Max 45 60 Min Typ Max Unit 50 69 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1025 −980 −880 −1025 −980 −880 −1025 −980 −880 mV VOL Output LOW Voltage (Note 2) −1810 −1700 −1620 −1810 −1700 −1620 −1810 −1700 −1620 mV VIH Input HIGH Voltage (Single-Ended) −1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV VIL Input LOW Voltage (Single-Ended) −1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV VBB Output Voltage Reference −1.38 −1.25 −1.38 −1.26 −1.38 −1.26 V Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) −1.6 −0.4 −1.6 −0.4 −1.6 −0.4 V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.5 0.25 0.5 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min and max vary 1:1 with VCC. Table 5. AC CHARACTERISTICS (VCCx = 5.0 V; VEE= 0.0 V or VCCx = 0.0 V; VEE= −5.0 V (Note 1)) −40°C Symbol Characteristic Min Typ 25°C Max Min Max Min Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output IN (Diff) (Note 2) IN (SE) (Note 3) Enable (Note 4) Disable (Note 4) 430 380 400 400 ts Setup Time (Note 5) EN to IN 250 0 200 0 200 0 tH Hold Time (Note 6) IN to EN 50 −200 0 −200 0 −200 tR Release Time (Note 7) EN to IN 350 100 300 100 300 100 tJITTER 800 Typ fMAX tskew 800 Typ 85°C Max 800 Unit MHz ps 630 680 900 900 430 380 450 450 630 680 850 850 430 380 450 450 630 680 850 850 ps ps ps Within-Device Skew (Note 8) 25 75 25 50 25 50 ps Random Clock Jitter (RMS)