MC100E137FNR2G

5 V ECL 8‐Bit Ripple Counter MC10E137 Description The MC10E137 is a very high speed binary ripple counter. The two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECLinPS™ output edge rates. This allows the counter to operate at very high frequencies while maintaining a moderate power dissipation level. The device is ideally suited for multiple frequency clock generation as well as a counter in a high performance ATE time measurement board. Both asynchronous and synchronous enables are available to maximize the device’s flexibility for various applications. The asynchronous enable input, A_Start, when asserted enables the counter while overriding any synchronous enable signals. The E137 features XORed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted the counter becomes disabled on the next CLK transition; all outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK. If EN1 (or EN2) and CLK edges are coincident, sufficient delay has been inserted in the CLK path (to compensate for the XOR gate delay and the internal D-flip flop setup time) to insure that the synchronous enable signal is clocked correctly, hence, the counter is disabled. All input pins left open will be pulled LOW via an input pulldown resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device. The asynchronous Master Reset resets the counter to an all zero state upon assertion. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. www.onsemi.com PLCC−28 FN SUFFIX CASE 776−02 MARKING DIAGRAM* 1 MC10E137FNG AWLYYWW A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC10E137FNG PLCC−28 (Pb-Free) 37 Units/Tube Features • • • • • • • • • Differential Clock Input and Data Output Pins VBB Output for Single-Ended Use Synchronous and Asynchronous Enable Pins Asynchronous Master Reset PECL Mode Operating Range: ♦ VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: ♦ VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 50 kW Pull-down Resistors Transistor Count = 330 devices ESD Protection: © Semiconductor Components Industries, LLC, 2016 March, 2021 − Rev. 10 Human Body Model: > 2 kV Machine Model: > 200 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: 3 (Pb-Free) ♦ For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 These Devices are Pb-Free, Halogen Free and are RoHS Compliant ♦ • • • • 1 ♦ Publication Order Number: MC10E137/D MC10E137 Q7 Q7 Q6 Q6 VCCO Q5 Q5 25 24 23 22 21 20 19 Table 1. PIN DESCRIPTION A_Start 26 18 Q4 EN1 27 17 Q4 EN2 28 16 VCC VEE Pinout: 28-Lead PLCC (Top View) 1 Q3 15 CLK 2 14 Q3 CLK 3 13 Q2 4 12 Q2 VBB 5 6 MR VCCO 7 8 9 10 11 Q0 Q0 Q1 Q1 VCCO PIN FUNCTION CLK, CLK ECL Differential Clock Inputs Q0-Q7, Q0-Q7 ECL Differential Q Outputs A_Start ECL Asynchronous Enable Input EN1, EN2 ECL Synchronous Enable Inputs MR Asynchronous Master Reset VBB Reference Voltage Output VCC, VCCO Positive Supply VEE Negative Supply * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 28-Lead Pinout A_Start EN1 EN2 D VBB Q0 Q0 Q7 Q7 Q1 Q1 Q CLK CLK CLK CLK R Q CLK CLK D Q Q R MR Figure 2. Logic Diagram www.onsemi.com 2 CLK CLK D Q Q R CLK CLK D Q Q R MC10E137 Table 2. SEQUENTIAL TRUTH TABLE EN1 EN2 A_Start MR CLK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Reset Function X X X H X L L L L L L L L Count L L L L L L L L L L L L Z Z Z L L L L L L L L L L L L L L L L L L L H H H L H Stop H H L L L L L L Z Z L L L L L L L L L L L L H H H H Asynch Start H H L L L L H H H L L L Z Z Z L L L L L L L L L L L L L L L H H H L L H L H L Count L L L L L L L L L L L L Z Z Z L L L L L L L L L L L L L H H H L L H L L H L H Stop L L H H L L L L Z Z L L L L L L L L H H L L L L H H Synch Start H H H H H H L L L L L L Z Z Z L L L L L L L L L L L L H H H L L H H H L L H L Stop H H L L L L L L Z Z L L L L L L L L H H H H L L L L Count L L L L L L L L L L L L Z Z Z L L L L L L L L L L L L H H H H H H L H H H L H Reset X X X H X L L L L L L L L Z = Low to High Transition Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V Iout Output Current Continuous Surge 50 100 mA TA Operating Temperature Range 0 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm PLCC−28 63.5 43.5 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board PLCC−28 22 to 26 °C/W VEE PECL Operating Range NECL Operating Range 4.2 to 5.7 −5.7 to −4.2 V Tsol Wave Solder (Pb-Free) 265 °C VI v VCC VI w VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 3 MC10E137 Table 4. 10E SERIES PECL DC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V (Note 1)) 0°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 121 145 121 145 121 145 mA VOH Output HIGH Voltage (Note 2) 3980 40 70 4160 4020 4105 4190 4090 4185 4280 mV VOL Output LOW Voltage (Note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mV VIH Input HIGH Voltage (Single-Ended) 3830 3995 4160 3870 4030 4190 3940 4110 4280 mV VIL Input LOW Voltage (Single-Ended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mV VBB Output Voltage Reference 3.62 3.73 3.65 3.75 3.69 3.81 V Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) 2.2 4.6 2.2 4.6 2.2 4.6 V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.3 0.5 0.25 0.3 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. Table 5. 10E SERIES NECL DC CHARACTERISTICS (VCCx = 0.0 V; VEE = −5.0 V (Note 1)) 0°C Symbol Characteristic Min 25°C Typ Max 121 145 Min 85°C Typ Max 121 145 Min Typ Max Unit 121 145 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1020 −930 −840 −980 −895 −810 −910 −815 −720 mV VOL Output LOW Voltage (Note 2) −1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595 mV VIH Input HIGH Voltage (Single-Ended) −1170 −1005 −840 −1130 −970 −810 −1060 −890 −720 mV VIL Input LOW Voltage (Single-Ended) −1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV VBB Output Voltage Reference −1.38 −1.27 −1.35 −1.25 −1.31 −1.19 V Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) −2.8 −0.4 −2.8 −0.4 −2.8 −0.4 V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current 150 0.5 0.3 150 0.5 0.065 0.3 0.2 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. www.onsemi.com 4 MC10E137 Table 6. AC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note NO TAG)) 0°C Symbol Characteristic Min Typ fCOUNT Maximum Count Frequency 1800 2200 tPLH tPHL Propagation Delay to Output CLK to Q0 CLK to Q1 CLK to Q2 CLK to Q3 CLK to Q4 CLK to Q5 CLK to Q6 CLK to Q7 A_Start to Q0 MR to Q0 1300 1600 1950 2275 2625 2950 3250 3575 950 700 1700 2025 2425 2750 3125 3450 3775 4075 1325 1000 25°C Max 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 Min Typ 1800 2200 1300 1600 1950 2275 2625 2950 3250 3575 950 700 1700 2050 2450 2775 3150 3475 3800 4125 1325 1000 85°C Max 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 Min Typ 1800 2200 1350 1650 2025 2350 2700 3050 3375 3700 950 700 1750 2100 2500 2850 3225 3550 3925 4250 1325 1000 Max Unit MHz 2200 2550 3000 3425 3825 4250 4600 4950 1700 1300 ps ts Setup Time (EN1, EN2) 0 −150 0 −150 0 −150 ps th Hold Time (EN1, EN2) 300 150 300 150 300 150 ps tRR Reset Recovery Time MR, A_Start 400 200 400 200 400 200 ps tPW Minimum Pulse Width CLK, MR, A_Start 400 VPP Input Voltage Swing CLK/CLK (Differential Configuration) (Note 4) 0.25 tJITTER Random Clock Jitter (RMS) tr tf Rise/Fall Times (20%−80%) Q0,Q1 Q2 to Q7 400 1.0 0.25