MC100E210
5VECL Dual 1:4, 1:5
Differential Fanout Buffer
The MC100E210 is a low voltage, low skew dual differential ECL
fanout buffer designed with clock distribution in mind. The device
features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The
device features fully differential clock paths to minimize both device and
system skew. The dual buffer allows for the fanout of two signals through
a single chip, thus reducing the skew between the two fundamental
signals from a part−to−part skew down to an output−to−output skew. This
capability reduces the skew by a factor of 4 as compared to using two
LVE111’s to accomplish the same task.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10−20 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10−20 pS increase in TPD, so the
relative skew between any two output pairs remains about 25 nS.
For more information on using PECL, designers should refer to
Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, VBB should be left open.
• Dual Differential Fanout Buffers
• 200 ps Part−to−Part Skew
• 50 ps Typical Output−to−Output Skew
• Low Voltage ECL/PECL Compatible
• The 100 Series Contains Temperature Compensation
• 28−lead PLCC Packaging
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Internal Input 75 K Pulldown Resistors
• Q Output will Default LOW with Inputs Open or at VEE
• ESD Protection: Human Body Model; >2 KV,
Machine Model; >200 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 179 devices
Semiconductor Components Industries, LLC, 2003
October, 2003 − Rev. 2
1
http://onsemi.com
MARKING
DIAGRAM
1 28
MC100E210FN
AWLYYWW
PLCC−28
FN SUFFIX
CASE 776
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Package
Shipping†
MC100E210FN
PLCC−28
37 Units / Rail
MC100E210FNR2
PLCC−28 500 Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
MC100E210/D
MC100E210
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Qa0 Qa0 Qa1 VCCO Qa1 Qa2 Qa2
25
24
23
22
21
20
19
VEE
26
18
Qa3
VBB
27
17
Qa3
CLKa
28
16
Qb0
15
VCCO
VCC
28−Lead PLCC
(Top View)
1
CLKa
2
14
Qb0
CLKb
3
13
Qb1
CLKb
4
12
Qb1
LOGIC SYMBOL
Qa0
Qa0
CLKa
Qa1
CLKa
Qa1
Qa2
Qa2
Qa3
5
6
7
8
9
10
Qa3
11
Qb0
Qb4 Qb4 Qb3 VCCO Qb3 Qb2 Qb2
Qb0
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
CLKb
Qb1
CLKb
Qb1
Qb2
PIN DESCRIPTION
PIN
FUNCTION
CLKa, CLKb
CLKa, CLKb
Qa0:3, Qb0:4
Qa0:3, Qb0:4
VBB
VCC, VCCO
VEE
ECL Differential Input Pairs
ECL Differential Input Pairs
ECL Differential Outputs
ECL Differential Outputs
Reference Output Voltage
Positive Supply
Negative Supply
Qb2
Qb3
Qb3
Qb4
Qb4
VBB
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
Standard Board
28 PLCC
22 to 26
°C/W
VEE
PECL Operating Range
NECL Operating Range
4.2 to 5.7
−5.7 to −4.2
V
V
Tsol
Wave Solder
265
°C
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