5 V ECL Voltage Controlled
Oscillator Amplifier
MC100EL1648
Description
The MC100EL1648 is a voltage controlled oscillator amplifier that
requires an external parallel tank circuit consisting of the inductor (L)
and capacitor (C). A varactor diode may be incorporated into the tank
circuit to provide a voltage variable input for the oscillator (VCO).
This device may also be used in many other applications requiring
a fixed frequency clock.
The MC100EL1648 is ideal in applications requiring a local
oscillator, systems that include electronic test equipment, and digital
high−speed telecommunications.
The MC100EL1648 is based on the VCO circuit topology of the
MC1648. The MC100EL1648 uses advanced bipolar process
technology which results in a design which can operate at an extended
frequency range.
The ECL output circuitry of the MC100EL1648 is not a traditional
open emitter output structure and instead has an on−chip termination
emitter resistor, RE, with a nominal value of 510 W. This facilitates
direct ac−coupling of the output signal into a transmission line.
Because of this output configuration, an external pull−down resistor is
not required to provide the output with a dc current path. This output is
intended to drive one ECL load (3.0 pF). If the user needs to fanout the
signal, an ECL buffer such as the EL16 (EL11, EL14) type Line
Receiver/Driver should be used.
Features
•
•
•
•
•
•
Typical Operating Frequency Up to 1100 MHz
Low−Power 19 mA at 5.0 Vdc Power Supply
PECL Mode Operating Range: VCC = 4.2 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V
to −5.5 V
Input Capacitance = 6.0 pF (TYP)
These are Pb−Free Devices
NOTE:
EXTERNAL
TANK
CIRCUIT
8
8
1
1
SOIC−8 NB
D SUFFIX
CASE 751−07
TSSOP−8
DT SUFFIX
CASE 948R−02
MARKING DIAGRAMS*
8
8
K1648
ALYW
G
1
1
SOIC−8 NB
A
L
Y
W
G
1648
ALYWG
G
TSSOP−8
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
The MC100EL1648 is NOT useable as a crystal oscillator.
VCC
www.onsemi.com
VCC
BIAS POINT
OUTPUT
TANK
VEE
VEE
AGC
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2008
March, 2021 − Rev. 9
1
Publication Order Number:
MC100EL1648/D
MC100EL1648
Table 1. PIN DESCRIPTION
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pin No.
Symbol
1
TANK
2, 3
VCC
Positive Supply
4
OUT
ECL Output
BIAS
VEE
VEE
8
7
6
5
1
2
3
4
VCC
OUT
Description
AGC
OSC Input Voltage
5
AGC
Automatic Gain Control Input
6, 7
VEE
Negative Output
8
BIAS
OSC Input Reference Voltage
TANK VCC
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 2. Pinout Assignments
Table 2. ATTRIBUTES
Characteristic
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1 kV
> 100 V
> 1 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb−Free Pkg
SOIC−8
TSSOP−8
Level 1
Level 3
Flammability Rating
Oxygen Index: 23 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
11
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
7 to 0
V
−7 to 0
V
6 to 0
−6 to 0
V
V
50
100
MA
mA
VCC
Power Supply PECL Mode
VEE = 0 V
VEE
Power Supply NECL Mode
VCC = 0 V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
°C/W
Tsol
Wave Solder
1.0 MW must be used).
** The 1200 W resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
0.1 mF
Tank Circuit Option #1, Varactor Diode
VCC
0.1 mF
3
8
0.1mF
Test Point
0.1 mF
2
4 (3)
FOUT
C
L
1
Tank #2
6
VEE
100 mF
7
0.01 mF
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35pF Variable Capacitance (@ 10 pF)
Note 1 Capacitor for tank may be variable type.
(See Tank Circuit #3.)
Note 2 Use high impedance probe (> 1 MW ).
5
0.1 mF
0.1 mF
Tank Circuit Option #2, Fixed LC
Figure 3. Typical Test Circuit with Alternate Tank Circuits
50%
VP-P
ta
PRF = 1.0MHz
t
Duty Cycle (Vdc) - a
tb
tb
Figure 4. Output Waveform
www.onsemi.com
4
MC100EL1648
OPERATION THEORY
Q2 and Q3, in conjunction with output transistor Q1,
provide a highly buffered output that produces a square
wave. The typical output waveform can be seen in Figure 4.
The bias drive for the oscillator and output buffer is provided
by Q9 and Q11 transistors. In order to minimize current, the
output circuit is realized as an emitter−follower buffer with
an on chip pull−down resistor RE.
Figure 5 illustrates the simplified circuit schematic for the
MC100EL1648. The oscillator incorporates positive feedback
by coupling the base of transistor Q6 to the collector of Q7. An
automatic gain control (AGC) is incorporated to limit the
current through the emitter−coupled pair of transistors (Q7 and
Q6) and allow optimum frequency response of the oscillator.
In order to maintain the high quality factor (Q) on the oscillator,
and provide high spectral purity at the output, transistor Q4 is
used to translate the oscillator signal to the output differential
pair Q2 and Q3. Figure 16 indicates the high spectral purity
of the oscillator output (pin 4 on 8−pin SOIC). Transistors
VCC 2
800 W
VCC 3
1.36 KW
3.1 KW
660 W
167 W
Q9
Q1
Q3
1.6 KW
Q2
OUTPUT
4
Q4
Q11
Q10
Q7 Q6
D1
330 W
Q8
D2
400 W
Q5
16 KW
VEE
7
BIAS
8
TANK
1
VEE
6
82 W
AGC
5
Figure 5. Circuit Schematic
www.onsemi.com
5
400 W
660 W
510 W
MC100EL1648
30
Measured Frequency (MHz)
FREQUENCY (MHz)
25
Calculated Frequency (MHz)
20
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
15
* The 1200 W resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
10
5
0
0
300
500
1000
2000
10000
0.1mF
CAPACITANCE (pF)
2
8
10mF
3
1200*
L
0.1mF
C
4
SIGNAL
UNDER
TEST
1
Tank #3
6
VEE
100 mF
7
0.01 mF
5
0.1 mF
0.1 mF
Figure 6. Low Frequency Plot
100
FREQUENCY (MHZ)
80
60
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
40
20
* The 1200 W resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
Measured Frequency (MHz)
Calculated Frequency (MHz)
0
0
0.2
0.3
300
0.1mF
CAPACITANCE (pF)
2
8
10mF
3
1200*
L
0.1mF
C
4
1
Tank #3
6
VEE
100 mF
0.01 mF
Figure 7. High Frequency Plot
www.onsemi.com
6
7
0.1 mF
5
0.1 mF
SIGNAL
UNDER
TEST
MC100EL1648
FIXED FREQUENCY MODE
capacitors should have very low dielectric loss (high−Q). At
a minimum, the capacitors selected should be operating at
100 MHz below their series resonance point. As the desired
frequency of operation increases, the values of the tank
capacitor will decrease since the series resonance point is
a function of the capacitance value. Typically, the inductor
is realized as a surface−mount chip or a wound coil. In
addition, the lead inductance and board inductance and
capacitance also have an impact on the final operating point.
The following equation will help to choose the appropriate
values for your tank circuit design.
The MC100EL1648 external tank circuit components are
used to determine the desired frequency of operation as
shown in Figure 8, tank option #2. The tank circuit
components have direct impact on the tuning sensitivity, IEE,
and phase noise performance. Fixed frequency of the tank
circuit is usually realized by an inductor and capacitor (LC
network) that contains a high Quality factor (Q). The plotted
curve indicates various fixed frequencies obtained with
a single inductor and variable capacitor. The Q of the
components in the tank circuit has a direct impact on the
resulting phase noise of the oscillator. In general, when the
Q is high the oscillator will result in lower phase noise.
f0 +
570
FREQUENCY (MHz)
LT = Total Inductance
CT = Total Capacitance
Figure 9 and Figure 10 represent the ideal curve of
inductance/capacitance versus frequency with one known
tank component. This helps the designer of the tank circuit
to choose desired value of inductor/capacitor component for
the wanted frequency. The lead inductance and board
inductance and capacitance will also have an impact on the
tank component values (inductor and capacitor).
Calculated Frequency (MHz)
370
270
170
70
0
−30
50
0.3
300
500
1000
2000
45
10000
INDUCTANCE (nH)
CAPACITANCE (pF)
VCC
0.1 mF
8
0.1 mF
3
2
C
L
Tank #2
35
30
Inductance vs. Frequency with 5 pF Cap
25
20
15
5
FOUT
0
400
1
700
1000
1300
160
FREQUENCY (MHz)
6
VEE
100 mF
40
10
4
7
Figure 9. Capacitor Value Known (5 pF)
5
50
0.01 mF
0.1 mF
45
0.1 mF
40
CAPACITANCE (F)
0.1 mF
Test
Point
Ǹ LT * CT
Where
Measured Frequency (MHz)
470
1
2p
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
Note 1 Capacitor for tank may be variable type.
(See Tank Circuit #3.)
Note 2 Use high impedance probe (> 1 MW ).
35
30
Capacitance vs. Frequency with 4 nH Inductance
25
20
15
10
QL ≥ 100
5
Figure 8. Fixed Frequency LC Tank
0
Only high quality surface−mount RF chip capacitors
should be used in the tank circuit at high frequencies. These
400
700
1000
FREQUENCY (Hz)
1300
Figure 10. Inductor Value Known (4 nH)
www.onsemi.com
7
160
MC100EL1648
VOLTAGE CONTROLLED MODE
When operating the oscillator in the voltage controlled
mode with Tank Circuit #1 (Figure 3), it should be noted that
the cathode of the varactor diode (D), pin 8 (for 8 lead
package) or pin 10 (for 14 lead package) should be biased at
least 1.4 V above VEE.
Typical transfer characteristics employing the
capacitance of the varactor diode (plus the input capacitance
of the device, about 6.0 pF typical) in the voltage controlled
mode is shown in Plot 1, Dual Varactor MMBV609 Vin vs.
Frequency. Figure 6, Figure 7, and Figure 8 show the
accuracy of the measured frequency with the different
variable capacitance values. The 1.0 kW resistor in Figure 11
is used to protect the varactor diode during testing. It is not
necessary as long as the dc input voltage does not cause the
diode to become forward biased. The tuning range of the
oscillator in the voltage controlled mode may be calculated
as follows:
The tank circuit configuration presented in Figure 11,
Voltage Controlled Varactor Mode, allows the VCO to be
tuned across the full operating voltage of the power supply.
Deriving from Figure 6, the tank capacitor, C, is replaced
with a varactor diode whose capacitance changes with the
voltage applied, thus changing the resonant frequency at
which the VCO tank operates as shown in Figure 3, tank
option #1. The capacitive component in Equation 1 also
needs to include the input capacitance of the device and
other circuit and parasitic elements.
190
FREQUENCY (MHz)
170
150
130
110
Ǹ CD(max) ) CS
f max
+
f min
Ǹ CD(min) ) CS
90
70
50
Where
0
2
4
6
8
10
f min +
Vin, INPUT VOLTAGE (V)
Figure 12. Plot 1. Dual Varactor MMBV609,
VIN vs. Frequency
Where
CS = Shunt Capacitance (input plus external
capacitance)
VCC
0.1 mF
8 (10)
2
VIN
Good RF and low−frequency bypassing is necessary on
the device power supply pins. Capacitors on the AGC pin
and the input varactor trace should be used to bypass the
AGC point and the VCO input (varactor diode),
guaranteeing only dc levels at these points. For output
frequency operation between 1.0 MHz and 50 MHz, a 0.1 mF
capacitor is sufficient. At higher frequencies, smaller values
of capacitance should be used; at lower frequencies, larger
values of capacitance. At high frequencies, the value of
bypass capacitors depends directly on the physical layout of
the system. All bypassing should be as close to the package
pins as possible to minimize unwanted lead inductance.
Several different capacitors may be needed to bypass
various frequencies.
4 (3)
L*
C
CD = Varactor Capacitance as a function of bias
voltage
0.1 mF
3 (1)
1 KW
Tank #1
1 (12)
6 (7) 7 (8)
VEE
100 mF
0.01 mF
0.1 mF
1
2p Ǹǒ L(CD(max) ) CS Ǔ
5 (5) **
0.1 mF FOUT
*Use high impedance probe (>1.0 MegW must be used).
**The 1200 W resistor and the scope termination impedance constitute a 25:1 attenuator probe. Coax shall be
CT−070−50 or equivalent.
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = MMBV609
Figure 11. Voltage Controlled Varactor Mode
www.onsemi.com
8
MC100EL1648
WAVE−FORM CONDITIONING − SINE OR SQUARE WAVE
Figure 13. At frequencies above 100 MHz typical, it may be
desirable to increase the tank circuit peak−to−peak voltage
in order to shape the signal into a more square waveform at
the output of the MC100EL1648. This is accomplished by
tying a series resistor (1.0 kW minimum) from the AGC to
the most positive power potential (+5.0 V if a positive volt
supply is used, ground if a −5.2 V supply is used). Figure 14
illustrates this principle.
The peak−to−peak swing of the tank circuit is set
internally by the AGC pin. Since the voltage swing of the
tank circuit provides the drive for the output buffer, the AGC
potential directly affects the output waveform. If it is desired
to have a sine wave at the output of the MC100EL1648,
a series resistor is tied from the AGC point to the most
negative power potential (ground if positive volt supply is
used, −5.2 V if a negative supply is used) as shown in
+5.0Vdc
1
+5.0Vdc
14
10
1
3
14
10
Output
3
Output
1.0k min
12
5
7
12
8
5
7
Figure 13. Method of Obtaining a Sine−Wave Output
8
Figure 14. Method of Extending the Useful Range
of the MC100EL1648 (Square Wave Output)
www.onsemi.com
9
MC100EL1648
10 dB / DEC
SPECTRAL PURITY
99.8
99.9
100.0
100.1
100.2
B.W. = 10 kHz, Center Frequency = 100 MHz
Scan Width = 50 kHz/div, Vertical Scale = 10 dB/div
Figure 15. Spectral Purity
0.1 mF
2
8
10 mF
3
1200*
L
0.1 mF
C
4
SIGNAL
UNDER
TEST
1
Tank #3
6
VEE
100 mF
0.01 mF
7
0.1 mF
5
L = Micro Metal torroid #T20−22, 8 turns #30
Enameled Copper wire (@ 40 nH)
C = 3.0−35 pF Variable Capacitance (@ 10 pF)
** The 1200 W resistor and the scope termination
impedance constitute a 25:1 attenuator probe.
Coax shall be CT−070−50 or equivalent.
0.1 mF
Spectral Purity Test Circuit
Figure 16. Spectral Purity of Signal Output for 200 MHz Testing
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 17. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
www.onsemi.com
10
MC100EL1648
ORDERING INFORMATION
Device
MC100EL1648DG
MC100EL1648DTR2G
Package
Shipping†
SOIC−8 NB
(Pb−Free)
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP 8
CASE 948R−02
ISSUE A
DATE 04/07/2000
SCALE 2:1
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
T U
S
V
4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
0.25 (0.010)
B
−U−
A
−V−
S
M
M
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
DOCUMENT NUMBER:
DESCRIPTION:
98AON00236D
TSSOP 8
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
