MC100EL17DWG

MC100EL17 5V ECL Quad Differential Receiver Description The MC100EL17 is a low-voltage, quad differential receiver. The device is functionally equivalent to the E116 device Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. www.onsemi.com SOIC−20 WB DW SUFFIX CASE 751D−05 Features • • • • • • • 325 ps Propagation Delay The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on D Inputs, Pullup and Pulldown Resistors on D Inputs Q Output will Default LOW with Inputs Open or at VEE These Devices are Pb-Free, Halogen Free and are RoHS Compliant MARKING* DIAGRAM 20 100EL17 AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device MC100EL17DWG © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 8 1 Package Shipping SOIC−20 WB (Pb-Free) 38 Units/Tube Publication Order Number: MC100EL17/D MC100EL17 VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VCC D0 D0 D1 D1 D2 D2 D3 D3 VBB Table 1. PIN DESCRIPTION PIN FUNCTION Dn, Dn Qn, Qn VBB VCC VEE ECL Differential Data Inputs ECL Differential Data Outputs Reference Voltage Output Positive Supply Negative Supply * All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: (Top View) Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 KW Internal Input Pullup Resistor 75 KW ESD Protection Human Body Model Machine Model Charged Device Model > 2 KV > 200 V >4V Moisture Sensitivity (Note 1) Pb-Free Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 141 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V Iout Output Current Continuous Surge 50 100 mA IBB VBB Sink/Source ± 0.5 mA VI ≤ VCC VI ≥ VEE TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC-20 WB 90 60 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC-20 WB 30 to 35 °C/W Tsol Wave Solder (Pb-Free)