MC100EL33DTG

5 V ECL ÷4 Divider MC10EL33, MC100EL33 Description The MC10EL/100EL33 is an integrated ÷4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EL33’s in a system. The 100 Series contains temperature compensation. www.onsemi.com 8 1 SOIC−8 NB D SUFFIX CASE 751−07 Features MARKING DIAGRAM • 650 ps Propagation Delay • 4.0 GHz Toggle Frequency • ESD Protection: 8 HEL33 ALYW G > 1 kV Human Body Model ♦ > 100 V Machine Model PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on CLK(s) and R. Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity: ♦ Level 1 for SOIC−8 NB ♦ For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 95 Devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant ♦ • • • • • • • • 1 8 KEL33 ALYW G 1 H K A L Y W G = MC10 = MC100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device © Semiconductor Components Industries, LLC, 2016 April, 2021 − Rev. 12 1 Package Shipping MC10EL33DG SOIC−8 (Pb-Free) 98 Units / Tube MC100EL33DG SOIC−8 (Pb-Free) 98 Units / Tube Publication Order Number: MC10EL33/D MC10EL33, MC100EL33 Reset CLK 1 8 R 2 Table 1. PIN DESCRIPTION VCC 7 Q 6 Q Pin CLK, CLK Reset Q, Q VBB VCC VEE ÷4 CLK 3 Function ECL Clock Inputs* ECL Asynch Reset* ECL Data Outputs Reference Voltage Output Positive Supply Negative Supply *Pins will default low when left open. VBB 4 5 VEE Figure 1. Logic Diagram and Pinout Assignment Table 2. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V Iout Output Current Continuous Surge 50 100 mA IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−8 NB SOIC−8 NB 190 130 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W Tsol Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C VI ≤ VCC VI ≥ VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2 MC10EL33, MC100EL33 Table 3. 10EL SERIES PECL DC CHARACTERISTICS (VCC = 5.0 V; VEE = 0.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 27 33 Min 85°C Typ Max 27 33 Min Typ Max Unit 27 33 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mV VOL Output LOW Voltage (Note 2) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mV VIH Input HIGH Voltage (Single-Ended) 3770 4110 3870 4190 3940 4280 mV VIL Input LOW Voltage (Single-Ended) 3050 3500 3050 3520 3050 3555 mV VBB Output Voltage Reference 3.57 3.7 3.65 3.75 3.69 3.81 V Input HIGH Voltage Common Mode Range (DIfferential Configuration) (Note 3) 2.5 4.6 2.5 4.6 2.5 4.6 V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.5 0.3 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / −0.5 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 4. 10EL SERIES NECL DC CHARACTERISTICS (VCC = 0.0 V; VEE = −5.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 27 33 Min 85°C Typ Max 27 33 Min Typ Max Unit 27 33 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1080 −990 −890 −980 −895 −810 −910 −815 −720 mV VOL Output LOW Voltage (Note 2) −1950 −1800 −1650 −1950 −1790 −1630 −1950 −1773 −1595 mV VIH Input HIGH Voltage (Single-Ended) −1230 −890 −1130 −810 −1060 −720 mV VIL Input LOW Voltage (Single-Ended) −1950 −1500 −1950 −1480 −1950 −1445 mV VBB Output Voltage Reference −1.43 −1.30 −1.35 −1.25 −1.31 −1.19 V Input HIGH Voltage Common Mode Range (DIfferential Configuration) (Note 3) −2.5 −0.4 −2.5 −0.4 −2.5 −0.4 V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.5 0.3 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / −0.5 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. www.onsemi.com 3 MC10EL33, MC100EL33 Table 5. 100EL SERIES PECL DC CHARACTERISTICS (VCC = 5.0 V; VEE = 0.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 27 33 Min 85°C Typ Max 27 33 Min Typ Max Unit 31 37 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 2) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV VIH Input HIGH Voltage (Single-Ended) 3835 4120 3835 4120 3835 4120 mV VIL Input LOW Voltage (Single-Ended) 3190 3525 3190 3525 3190 3525 mV VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V Input HIGH Voltage Common Mode Range (DIfferential Configuration) (Note 3) 2.5 4.6 2.5 4.6 2.5 4.6 V 150 mA VIHCMR IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 6. 100EL SERIES NECL DC CHARACTERISTICS (VCC = 0.0 V; VEE = −5.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 27 33 Min 85°C Typ Max 27 33 Min Typ Max Unit 31 37 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 2) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single-Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single-Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V Input HIGH Voltage Common Mode Range (DIfferential Configuration) (Note 3) −2.5 −0.4 −2.5 −0.4 −2.5 −0.4 V 150 mA VIHCMR IIH Input HIGH Current 150 150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. www.onsemi.com 4 MC10EL33, MC100EL33 Table 7. AC CHARACTERISTICS (VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −5.0 V (Note 1)) −40°C Symbol Characteristic Min Typ fmax Maximum Toggle Frequency 3.4 4.2 tPLH tPHL Propagation Delay CLK to Q Reset to Q 560 400 670 540 tRR Set/Reset Recovery 400 200 VPP Input Swing (Note 2) 150 tJITTER Cycle-to-Cycle Jitter tr tf 25°C Max 860 700 1000 Min Typ 3.8 4.2 610 460 700 550 400 200 100 810 660 150 1.0 Output Rise/Fall Times Q (20%−80%) 85°C Max 1000 Min Typ 3.8 4.2 640 570 740 480 400 200 150 1.0 225 350 100 Max GHz 840 670 350 100 1000 225 ps ps 1.0 225 Unit mV ps 350 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. 10 Series: VEE can vary +0.25 V / −0.5 V. 100 Series: VEE can vary +0.8 V / −0.5 V. 2. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. CLK tRR RESET Q Figure 2. Timing Diagram Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices) www.onsemi.com 5 MC10EL33, MC100EL33 Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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