MC100EL39DW

MC100EL39 5V ECL ÷2/4, ÷4/6 Clock Generation Chip The MC100EL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EL39s, the Master Reset (MR) input must be asserted to ensure synchronization. For systems which only use one EL39, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of a single device. http://onsemi.com SO−20 WB DW SUFFIX CASE 751D MARKING DIAGRAM* 20 100EL39 AWLYYWWG Features • • • • • • • • • • • • • • 50 ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization ESD Protection: Human Body Model; > 2 kV, Machine Model; > 100 V The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on EN, MR, CLK(s), and DIVSEL(s) Q Output will Default LOW with Inputs Open or at VEE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Pb = Level 1 Pb−Free = Level 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index 28 to 34 Transistor Count = 419 devices Pb−Free Packages are Available* 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 November, 2008 − Rev. 7 1 Publication Order Number: MC100EL39/D MC100EL39 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 19 18 17 16 15 14 13 12 11 3 2 VCC EN DIVSELb 1 4 5 6 CLK CLK VBB 7 8 MR VCC 9 10 NC DIVSELa VCC Table 1. PIN DESCRIPTION Pin Function CLK, CLK EN MR Q0, Q0; Q1, Q1 Q2, Q2; Q3, Q3 DIVSELa, DIVSELb VBB VCC VEE NC NOTE: All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Diff ÷2/4 Outputs ECL Diff ÷4/6 Outputs ECL Frequency Select Input ECL Frequency Select Input Reference Voltage Output Positive Supply Negative Supply No Connect Figure 1. Pinout: SOIC−20 (Top View) Table 2. FUNCTION TABLE DIVSELa Q0 CLK P2/4 CLK R Q0 P4/6 R MR CLK* EN* MR* Divide Hold Q0−3 Reset Q0−3 Z ZZ X L H X L L H Z = Low-to-High Transition ZZ = High-to-Low Transition *Pin will default low when left open. Q1 Q1 EN Function Q2 DIVSELa** Q0, Q1 Outputs Q2 0 1 Divide by 2 Divide by 4 DIVSELb** Q2, Q3 Outputs 0 1 Divide by 4 Divide by 6 Q3 Q3 DIVSELb **Pin will default low when left open. Figure 2. Logic Diagram http://onsemi.com 2 MC100EL39 Table 3. MAXIMUM RATINGS Rating Unit VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−20 SOIC−20 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20 30 to 35 °C/W Tsol Wave Solder