MC100EP14DTG

MC100EP14 3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100EP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions. The EP14 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The common enable (EN) is synchronous, outputs are enabled/ disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • • • • • • • • • 400 ps Typical Propagation Delay 100 ps Device−to−Device Skew 25 ps Within Device Skew Maximum Frequency > 2 GHz Typical The 100 Series Contains Temperature Compensation PECL and HSTL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2014 April, 2014 − Rev. 7 http://onsemi.com TSSOP−20 DT SUFFIX CASE 948E MARKING DIAGRAM* 20 100 EP14 ALYWG G 1 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. 1 Publication Order Number: MC100EP14/D MC100EP14 VCC EN VCC CLK1 CLK1 VBB CLK0 CLK0 CLK_SEL VEE 20 19 18 17 16 15 14 13 12 11 1 0 D Q 1 2 3 4 5 6 7 8 9 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 WARNING: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. TSSOP−20 (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Pin Table 2. FUNCTION TABLE Function CLK0*, CLK0** ECL/PECL/HSTL CLK Input CLK1*, CLK1** ECL/PECL/HSTL CLK Input Q0:4, Q0:4 ECL/PECL Outputs CLK_SEL* ECL/PECL Active Clock Select Input EN* ECL Sync Enable VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply CLK0 CLK1 CLK_SEL EN Q L H X X X X X L H X L L H H X L L L L H L H L H L* * On next negative transition of CLK0 or CLK1 * Pins will default low when left open. ** Pins will default to VCC/2 when left open. http://onsemi.com 2 MC100EP14 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor ESD Protection 37.5 kW Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) TSSOP−8 Flammability Rating Oxygen Index: 28 to 34 > 4 kV > 200 V > 2 kV Pb Pkg Pb−Free Pkg Level 1 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 357 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−20 TSSOP−20 140 100 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−20 23 to 41 °C/W Tsol Wave Solder