MC10EP195, MC100EP195
3.3V ECL Programmable
Delay Chip
The MC10/100EP195 is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
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The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP195 has a digitally selectable resolution of about
MARKING
DIAGRAM*
10 ps and a net range of up to 10.2 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
MCXXX
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
EP195
will LOCK and HOLD current values present against any subsequent
AWLYYWWG
LQFP−32
changes in D[10:0]. The approximate delay values for varying tap
FA SUFFIX
32
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
CASE 873A
Table 6 and Figure 4.
1
Because the EP195 is designed using a chain of multiplexers it has a
fixed minimum delay of 2.2 ns. An additional pin D10 is provided for
1
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
MCXXX
by LEN, in cascading multiple PDCs for increased programmable
1 32
EP195
range. The cascade logic allows full control of multiple PDCs.
AWLYYWWG
QFN32
Switching devices from all “1” states on D[0:9] with SETMAX LOW
G
MN SUFFIX
to all “0” states on D[0:9] with SETMAX HIGH will increase the
CASE 488AM
delay equivalent to “D0”, the minimum increment.
XXX
= 10 or 100
Select input pins D[10:0] may be threshold controlled by
A
= Assembly Location
combinations of interconnects between VEF (pin 7) and VCF (pin 8)
WL, L = Wafer Lot
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
YY, Y
= Year
levels, leave VCF and VEF open. For ECL operation, short VCF and
WW, W = Work Week
VEF (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V
G or G = Pb−Free Package
supply reference to VCF and leave open VEF pin. The 1.5 V reference
(Note: Microdot may be in either location)
voltage to VCF pin can be accomplished by placing a 2.2 kW resistor
*For additional marking information, refer to
between VCF and VEE for a 3.3 V power supply.
Application Note AND8002/D.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
ORDERING INFORMATION
differential input is connected to VBB as a switching reference voltage.
See detailed ordering and shipping information in the package
VBB may also rebias AC coupled inputs. When used, decouple VBB
dimensions section on page 17 of this data sheet.
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
• Maximum Input Clock Frequency >1.2 GHz Typical
• Open Input Default State
• Programmable Range: 0 ns to 10 ns
• Safety Clamp on Inputs
• Delay Range: 2.2 ns to 12.2 ns
• A Logic High on the EN Pin Will Force Q to Logic
Low
• 10 ps Increments
• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
• PECL Mode Operating Range:
Inputs
VCC = 3.0 V to 3.6 V with VEE = 0 V
•
VBB Output Reference Voltage
• NECL Mode Operating Range:
• These are Pb−Free Devices
VCC = 0 V with VEE = −3.0 V to −3.6 V
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 19
1
Publication Order Number:
MC10EP195/D
MC10EP195, MC100EP195
28
27
D1
29
D2
30
D3
VEE
31
D4
32
D5
D6
D7
D8
1
26
25
24
VEE
D9
2
23
D0
D10
3
22
VCC
IN
4
MC10EP195
21
Q
IN
5
MC100EP195
20
Q
VBB
6
19
VCC
VEF
7
18
VCC
VCF
8
17
9
10
11
12
13
14
NC
16
15
EN
CASCADE
CASCADE
VCC
SETMAX
SETMIN
LEN
VEE
Figure 1. 32−Lead LQFP Pinout (Top View)
27
26
D1
28
D2
29
D3
VEE
30
D4
31
D5
D6
D7
32
25
D8
1
24
VEE
D9
2
23
D0
D10
3
22
VCC
IN
4
21
Q
IN
5
20
Q
VBB
6
19
VCC
VEF
7
18
VCC
VCF
8
17
NC
11
12
13
14
VEE
LEN
SETMIN
SETMAX
VCC
CASCADE
15
16
EN
10
CASCADE
9
Figure 2. 32−Lead QFN (Top View)
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2
Exposed Pad (EP)
MC10EP195, MC100EP195
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
23, 25, 26, 27,
29, 30, 31, 32,
1, 2
D[0:9]
LVCMOS, LVTTL,
ECL Input
Low
Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to VEE.
(Note 1)
3
D[10]
LVCMOS, LVTTL,
ECL Input
Low
Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW
to VEE. (Note 1)
4
IN
ECL Input
Low
Noninverted Differential Input. Internal 75 kW to VEE.
5
IN
ECL Input
High
Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to
VCC.
6
VBB
−
−
ECL Reference Voltage Output
7
VEF
−
−
Reference Voltage for ECL Mode Connection
8
VCF
−
−
LVCMOS, ECL, OR LVTTL Input Mode Select
9, 24, 28
VEE
−
−
Negative Supply Voltage. All VEE Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
13, 18, 19, 22
VCC
−
−
Positive Supply Voltage. All VCC Pins must be externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
10
LEN
ECL Input
Low
Single−ended D pins LOAD / HOLD input. Internal 75 kW to VEE.
11
SETMIN
ECL Input
Low
Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
VEE. (Note 1)
12
SETMAX
ECL Input
Low
Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
VEE. (Note 1)
14
CASCADE
ECL Output
−
Inverted Differential Cascade Output for D[10]. Typically Terminated
with 50 W to VTT = VCC − 2 V.
15
CASCADE
ECL Output
−
Noninverted Differential Cascade Output. for D[10] Typically
Terminated with 50 W to VTT = VCC − 2 V.
16
EN
ECL Input
Low
17
NC
−
−
No Connect. The NC Pin is Electrically Connected to the Die and
”MUST BE” Left Open
21
Q
ECL Output
−
Noninverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.
20
Q
ECL Output
−
Inverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.
Single−ended Output Enable Pin. Internal 75 kW to VEE.
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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3
MC10EP195, MC100EP195
Table 2. CONTROL PIN
Pin
State
EN
LOW (Note 3)
Function
Input Signal is Propagated to the Output
HIGH
LEN
Output Holds Logic Low State
LOW (Note 3)
Transparent or LOAD mode for real time delay values present on D[0:10].
HIGH
SETMIN
SETMAX
D10
LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]
are not recognized and do not affect delay.
LOW (Note 3)
Output Delay set by D[0:10]
HIGH
Set Minimum Output Delay
LOW (Note 3)
Output Delay set by D[0:10]
HIGH
Set Maximum Output Delay
LOW (Note 3)
CASCADE Output LOW, CASCADE Output HIGH
HIGH
CASCADE Output LOW, CASCADE Output HIGH
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE
VCF
VEF Pin (Note 4)
VCF
No Connect
VCF
1.5 V $ 100 mV
ECL Mode
LVCMOS Mode
LVTTL Mode (Note 5)
4. Short VCF (pin 8) and VEF (pin 7).
5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, RCF (suggested resistor value
is 2.2 kW $5%), between VCF and VEE pins.
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
CONTROL DATA SELECT INPUTS PINS (D [0:10])
POWER SUPPLY
LVCMOS
LVTTL
LVPECL
LVNECL
PECL Mode Operating Range
YES
YES
YES
N/A
NECL Mode Operating Range
N/A
N/A
N/A
YES
Table 5. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
(R1)
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6)
75 kW
> 2 kV
> 100 V
> 2 kV
Pb−Free Pkg
LQFP−32
Level 2
QFN−32
Level 1
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
1217 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
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4
5
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Figure 3. Logic Diagram
VEE
VEF
VCF
VBB
EN
IN
IN
R1
LEN
R1
SET MAX
SET MIN
R1
R1
R1
512
GD*
D9
R1
1
0
D10
Latch
R1
1
D8
R1
256
GD*
0
D7
1
CASCADE
CASCADE
R1
128
GD*
0
R1
64
GD*
D6
1
0
16
GD*
1
R1
D4
10 BIT LATCH
D5
1
0
R1
8
GD*
D3
1
0
R1
4
GD*
D2
1
0
R1
2
GD*
D1
1
0
*GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE
(MINIMUM FIXED DELAY APPROX. 2.2 ns)
R1
32
GD*
0
D0
R1
1
GD*
R1
1
0
1
GD*
1
0
Q
Q
MC10EP195, MC100EP195
MC10EP195, MC100EP195
Table 6. THEORETICAL DELAY VALUES
D(9:0) Value
SETMIN
SETMAX
Programmable Delay*
XXXXXXXXXX
H
L
0 ps
0000000000
L
L
0 ps
0000000001
L
L
10 ps
0000000010
L
L
20 ps
0000000011
L
L
30 ps
0000000100
L
L
40 ps
0000000101
L
L
50 ps
0000000110
L
L
60 ps
0000000111
L
L
70 ps
0000001000
L
L
80 ps
0000010000
L
L
160 ps
0000100000
L
L
320 ps
0001000000
L
L
640 ps
0010000000
L
L
1280 ps
0100000000
L
L
2560 ps
1000000000
L
L
5120 ps
1111111111
L
L
10230 ps
XXXXXXXXXX
L
H
10240 ps
*Fixed minimum delay not included.
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6
MC10EP195, MC100EP195
14000.0
13000.0
85°C
12000.0
11000.0
25°C
−40°C
DELAY ( ps)
10000.0
9000.0
VCC = 0 V
8000.0
VEE = −3.3 V
7000.0
6000.0
5000.0
4000.0
3000.0
2000.0
1000.0
0.0
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
800.0
900.0
1000.0
Decimal Value of Select Inputs (D[9:0])
Figure 4. Measured Delay vs. Select Inputs
Table 7. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
6
V
−6
V
6
−6
V
V
50
100
mA
mA
±0.5
mA
VCC
Positive Mode Power Supply
VEE = 0 V
VEE
Negative Mode Power Supply
VCC = 0 V
VI
Positive Mode Input Voltage
Negative Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
LQFP−23
LQFP−23
80
55
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
LQFP−23
12 to 17
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P
QFN−32
12
°C/W
Tsol
Wave Solder
265
°C
Pb−Free