MC100EP210SMNG

MC100EP210S 2.5V 1:5 Dual Differential LVDS Compatible Clock Driver Description The MC100EP210S is a low skew 1−to−5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs. The EP210S specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. Two internal 50 W resistors are provided across the inputs. For LVDS inputs, VTA and VTB pins should be unconnected. For LVPECL inputs, VTA and VTB pins should be connected to the VTT (VCC − 2.0 V) supply. Designers can take advantage of the EP210S performance to distribute low skew LVDS clocks across the backplane or the board. http://onsemi.com MARKING DIAGRAM* MC100 EP210S AWLYYWWG LQFP−32 FA SUFFIX CASE 873A 1 Features • • • • • • • • • 20 ps Typical Output−to−Output Skew 85 ps Typical Device−to−Device Skew 550 ps Typical Propagation Delay The 100 Series Contains Temperature Compensation Maximum Frequency > 1 GHz Typical Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V Internal 50 W Input Termination Resistors LVDS Input/Output Compatible These are Pb−Free Devices 1 32 QFN32 MN SUFFIX CASE 488AM xxx A WL, L YY, Y WW, W G MCxxx EP210S ALYWG = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2011 June, 2011 − Rev. 10 1 Publication Order Number: MC100EP210S/D MC100EP210S Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1 VCC Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 VCC 24 23 22 21 20 19 18 32 17 31 30 29 28 27 26 25 VCC 25 16 VCC VEE 1 24 Qa3 Qa2 26 15 Qb2 VTA 2 23 Qa3 Qa2 27 14 Qb2 CLKa 3 22 Qa4 Qa1 28 13 Qb3 CLKa 4 Qa1 29 12 Qb3 VTB 5 20 Qb0 Qa0 30 11 Qb4 CLKb 6 19 Qb0 Qa0 31 10 Qb4 CLKb 7 18 Qb1 VCC 32 9 VCC VEE 8 17 Qb1 MC100EP210S 1 2 3 4 5 6 7 8 21 Qa4 MC100EP210S 9 10 11 12 13 14 15 16 CLKb VTB CLKb CLKa VEE VTA CLKa VCC Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 VCC VEE Figure 1. 32−Lead QFN Pinout (Top View) Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 32−Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION CLKn, CLKn LVDS, LVPECL CLK Inputs* Qn0:4, Qn0:4 LVDS Outputs VTA 50 W Termination Resistors VTB 50 W Termination Resistors VCC Positive Supply VEE Ground EP for QFN−32, only The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat− sinking conduit. The pad is electrically connected to VEE. *Under open or floating conditions with input pins converging to a common termination bias voltage the device is susceptible to auto oscillation. VTA 50 W CLKa CLKa VTB Qa0 50 W Qa0 Qa1 Qa1 Qa2 50 W CLKb CLKb Qb0 50 W Qb0 Qb1 Qb1 Qb2 Qa2 Qb2 Qa3 Qb3 Qa3 Qb3 Qa4 Qb4 Qa4 Qb4 Figure 2. Logic Diagram http://onsemi.com 2 MC100EP210S Table 2. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Charged Device Model > 2 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP−32 QFN−32 Flammability Rating Pb Pkg Pb−Free Pkg Level 2 Level 2 Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 461 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. Table 3. MAXIMUM RATINGS Rating Unit VCC Symbol Power Supply Parameter VEE = 0 V Condition 1 6 V VEE Power Supply (GND) VCC = 2.5 V −6 V VI LVDS, LVPECL Input Voltage VEE = 0 V 6 V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 32 LQFP 32 LQFP 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 32 LQFP 12 to 17 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W Tsol Wave Solder 265 265 °C Pb Pb−Free Condition 2 VI ≤ VCC Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3 MC100EP210S Table 4. DC CHARACTERISTICS VCC = 2.5 V, VEE = 0 V (Note 2) −40°C Symbol Characteristic Min 25°C Typ Max 150 200 Min 85°C Typ Max 150 200 Min Typ Max Unit 150 200 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 1250 1400 1550 1250 1400 1550 1250 1400 1550 mV VOL Output LOW Voltage (Note 3) 800 950 1100 800 950 1100 800 950 1100 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) 1.2 2.5 1.2 2.5 1.2 2.5 V RT Internal Termination Resistor 43 57 43 57 43 57 W IIH Input HIGH Current 150 mA IIL Input LOW Current 150 150 mA 50 150 CLK CLK −150 −150 150 150 150 −150 −150 150 150 −150 −150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. 3. All loading with 100 W across LVDS differential outputs. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 5. AC CHARACTERISTICS VCC = 2.375 to 2.625 V, VEE = 0 V (Note 5) −40°C Symbol Characteristic fmaxLVDS/ LVPECL Maximum Frequency (See Figure 2. Fmax/JITTER) tPLH tPHL Propagation Delay tskew Min Typ 25°C Max Min >1 425 Typ 85°C Max Min >1 525 625 Within−Device Skew (Note 6) Device−to−Device Skew (Note 7) Duty Cycle Skew (Note 8) 20 85 80 tJITTER RMS Random Clock Jitter VPP Minimum Input Swing tr/tf Output Rise/Fall Time (20%−80%) 450 Typ Max >1 550 650 25 160 100 20 85 80 0.2