MC100EP32DTR2G

3.3V/5V ECL B2 Divider MC10EP32, MC100EP32 Description The MC10/100EP32 is an integrated B2 divider with differential CLK inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01ĂmF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP32’s in a system. The 100 Series contains temperature compensation. www.onsemi.com 8 8 1 1 TSSOP−8 SOIC−8 NB DT SUFFIX D SUFFIX CASE 751−07 CASE 948R−02 DFN−8 MN SUFFIX CASE 506AA Features • 350 ps Typical Propagation Delay • Maximum Frequency > 4 GHz Typical (Figure 3) • PECL Mode Operating Range: 8 8 VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: ♦ VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State ♦ 1 • • Safety Clamp on Inputs • Q Output Will Default LOW with Inputs Open or at VEE • These Devices are Pb-Free, Halogen Free and are RoHS Compliant HEP32 ALYW G 1 8 8 1 HP32 ALYWG G KEP32 ALYW G 1 H K 3K M = MC10 = MC100 = MC100 = Date Code KP32 ALYWG G A L Y W G 3K MG G • MARKING DIAGRAMS* 1 4 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2016 April, 2021 − Rev. 13 1 Publication Order Number: MC10EP32/D MC10EP32, MC100EP32 Table 1. PIN DESCRIPTION RESET 1 8 VCC Pin R CLK 2 7 Q B2 CLK VBB 3 6 4 5 Q Function CLK, CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset VBB Reference Voltage Output Q, Q ECL Data Outputs VCC Positive Supply VEE Negative Supply EP (DFN−8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. VEE Figure 1. 8-Lead Pinout (Top View) and Logic Diagram *Pins will default LOW when left open. Table 2. TRUTH TABLE CLK CLK RESET Q Q X Z X Z Z L L F H F Z = LOW to HIGH Transition Z = HIGH to LOW Transition F = Divide by 2 Function CLK tRR RESET Q Figure 2. Timing Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC−8 NB TSSOP−8 DFN−8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 78 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2 MC10EP32, MC100EP32 Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V Iout Output Current Continuous Surge 50 100 mA IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−8 NB 190 130 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm TSSOP−8 185 140 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm DFN8 129 84 °C/W qJC Thermal Resistance (Junction-to-Case) (Note 1) DFN8 35 to 40 °C/W Tsol Wave Solder (Pb-Free)