2.5 V/3.3 V Any Level
Positive Input to
-3.3 V/-5.5 V NECL
Output Translator
MC100EP91
www.onsemi.com
Description
The MC100EP91 is a triple any level positive input to NECL output
translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL,
CML or LVDS signals, and translates them to differential NECL
output signals (−3.0 V/−5.5 V).
To accomplish the level translation the EP91 requires three power
rails. The VCC pins should be connected to the positive power supply,
and the VEE pin should be connected to the negative power supply.
The GND pins are connected to the system ground plane. Both VEE
and VCC should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D input will be biased at VCC/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
•
•
•
•
•
•
Maximum Input Clock Frequency = > 2.0 GHz Typical
Maximum Input Data Rate = > 2.0 Gb/s Typical
500 ps Typical Propagation Delay
Operating Range:
VCC = 2.375 V to 3.8 V; VEE = −3.0 V to −5.5 V; GND = 0 V
Q Output will Default LOW with Inputs Open or at GND
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
20
24
1
SOIC−20 WB
DW SUFFIX
CASE 751D
1
QFN−24
MN SUFFIX
CASE 485L
MARKING DIAGRAMS*
24
20
1
MC100EP91
AWLYYWWG
100
EP91
ALYWG
G
SOIC−20 WB
QFN−24
1
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping†
MC100EP91DWG
SOIC−20 WB
(Pb-Free)
38 Units / Tube
MC100EP91DWR2G
SOIC−20 WB
(Pb-Free)
1000 Tape & Reel
QFN−24
(Pb-Free)
92 Units / Tube
MC100EP91MNG
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
March, 2021 − Rev. 7
1
Publication Order Number:
MC100EP91/D
MC100EP91
Positive Level
Input
D0
R1
D0
R1
D1
R1
D1
R1
NECL Output
Q0
R2
Q0
Q1
R2
Q1
VCC
VBB
GND
D2
R1
D2
R1
Q2
R2
VEE
Q2
Figure 1. Logic Diagram
Table 1. PIN DESCRIPTION
Pin
SOIC
QFN
Name
I/O
Default
State
1, 20
3, 4, 12
VCC
−
−
Positive Supply Voltage. All VCC Pins must be Externally
Connected to Power Supply to Guarantee Proper
Operation
10
15, 16
VEE
−
−
Negative Supply Voltage. All VEE Pins must be Externally
Connected to Power Supply to Guarantee Proper
Operation
14, 17
19, 20, 23,
24
GND
−
−
Ground
4, 7
7, 11
VBB
−
−
ECL Reference Voltage Output
2, 5, 8
5, 8, 13
D[0:2]
LVPECL, LVDS, LVTTL,
LVCMOS, CML, HSTL Input
Low
Noninverted Differential Inputs [0:2]. Internal 75 kW to GND.
3, 6, 9
6, 9, 14
D[0:2]
LVPECL, LVDS,
LVTTL,LVCMOS, CML,
HSTL Input
High
Inverted Differential Inputs [0:2]. Internal 75 kW to GND and
75 kW to VCC. When Inputs are Left Open They Default to
(VCC − GND) / 2
19,16,13
2, 22, 18
Q[0:2]
NECL Output
−
Noninverted Differential Outputs [0:2]. Typically Terminated
with 50 W to VTT = VCC − 2 V
18,15,12
1, 21, 17
Q[0:2]
NECL Output
−
Inverted Differential Outputs [0:2]. Typically Terminated with
50 W to VTT = VCC − 2 V
11
10
NC
−
−
No Connect. The NC Pin is NOT Electrically Connected to
the Die and may Safely be Connected to Any Voltage from
VEE to VCC
N/A
−
EP
−
Description
Exposed Pad (Note 1)
1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat−sinking conduit and may
only be electrically connected to VEE (not GND).
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2
MC100EP91
GND GND Q1
24
VCC Q0
Q0 GND Q1 Q1 GND Q2
Q2 NC
20
18
12
19
17
16
15
14
13
11
MC100EP91
1
2
3
4
VCC
D0
D0 VBB D1
5
6
7
8
D1 VBB D2
9
10
D2
VEE
23
22
Q1 GND GND
21
20
Exposed Pad
(EP)
19
Q0
1
18
Q2
Q0
2
17
Q2
VCC
3
16
VEE
VCC
4
15
VEE
D0
5
14
D2
D0
6
13
D2
MC100EP91
7
VBB
Figure 2. SOIC−20 Lead Pinout (Top View)
8
9
D1
D1
10
11
NC VBB
12
VCC
Figure 3. QFN−24 Lead Pinout (Top View)*
*All VCC, VEE and GND pins must be externally connected to a power supply and the underside exposed pad must be attached to an adequate
heat−sinking conduit to guarantee proper operation.
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor (R1)
75 kW
Internal Input Pullup Resistor (R2)
75 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 2 kV
Moisture Sensitivity (Note 1)
Pb-Free Pkg
SOIC−20 WB
QFN−24
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
446 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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3
MC100EP91
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
Positive Power Supply
GND = 0 V
3.8 to 0
V
VEE
Negative Power Supply
GND = 0 V
−6
V
Positive Input Voltage
GND = 0 V
VI ≤ VCC
3.8 to 0
V
VOP
Operating Voltage
GND = 0 V
VCC − VEE
9.8
V
Iout
Output Current
Continuous
Surge
50
100
mA
IBB
PECL VBB Sink/Source
±0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
JESD 51−3 (1S-Single Layer Test Board)
0 lfpm
500 lfpm
SOIC−20 WB
SOIC−20 WB
90
60
°C/W
qJA
Thermal Resistance (Junction-to-Ambient)
JESD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias
0 lfpm
500 lfpm
QFN−24
QFN−24
37
32
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
SOIC−20 WB
QFN−24
30 to 35
11
°C/W
Tsol
Wave Solder (Pb-Free)
225
°C
VI
Parameter
Condition 1
Condition 2
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. DC CHARACTERISTICS POSITIVE INPUTS (VCC = 2.5 V, VEE = −3.0 V to −5.5 V, GND = 0 V (Note 1))
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
10
14
20
10
14
20
10
14
20
mA
ICC
Positive Power Supply Current
VIH
Input HIGH Voltage (Single-Ended)
1335
VCC
1335
VCC
1335
VCC
mV
VIL
Input LOW Voltage (Single-Ended)
GND
875
GND
875
GND
875
mV
0
2.5
0
2.5
0
2.5
V
150
mA
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 2)
IIH
Input HIGH Current (@ VIH)
IIL
Input LOW Current (@ VIL)
D
D
150
0.5
−150
150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
1. Input parameters vary 1:1 with VCC. VCC can vary +1.3 V / −0.125 V.
2. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.
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4
MC100EP91
Table 5. DC CHARACTERISTICS POSITIVE INPUT (VCC = 3.3 V; VEE = −3.0 V to −5.5 V; GND = 0 V (Note 1))
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
10
16
24
10
16
24
10
16
24
mA
ICC
Positive Power Supply Current
VIH
Input HIGH Voltage (Single-Ended)
2135
VCC
2135
VCC
2135
VCC
mV
VIL
Input LOW Voltage (Single-Ended)
GND
1675
GND
1675
GND
1675
mV
VBB
PECL Output Voltage Reference
1775
1975
1775
1975
1775
1975
mV
3.3
0
3.3
0
3.3
V
150
mA
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 2)
IIH
Input HIGH Current (@ VIH)
IIL
Input LOW Current (@ VIL)
D
D
1875
0
1875
150
0.5
−150
1875
150
0.5
−150
mA
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
1. Input parameters vary 1:1 with VCC. VCC can vary +0.5 / −0.925 V.
2. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.
Table 6. DC CHARACTERISTICS NECL OUTPUT (VCC = 2.375 V to 3.8 V; VEE = −3.0 V to −5.5 V; GND = 0 V (Note 1))
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
40
50
60
38
50
68
38
50
68
mA
IEE
Negative Power Supply Current
VOH
Output HIGH Voltage (Note 2)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
VOL
Output LOW Voltage (Note 2)
−1945
−1770
−1600
−1945
−1770
−1600
−1945
−1770
−1600
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
1. Output parameters vary 1:1 with GND.
2. All loading with 50 W resistor to GND − 2.0 V.
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5
MC100EP91
Table 7. AC CHARACTERISTICS (VCC = 2.375 V to 3.8 V; VEE = −3.0 V to −5.5 V; GND = 0 V)
−40°C
Symbol
VOUTPP
25°C
Min
Typ
fin ≤ 1.0 GHz
fin ≤ 1.5 GHz
fin ≤ 2.0 GHz
575
525
300
800
750
600
Differential
Single-Ended
375
300
500
450
600
650
15
25
50
Characteristic
Output Voltage Amplitude
(Figure 4)
(Note 1)
tPLH
tPHL0
Propagation Delay
D to Q
tSKEW
Pulse Skew (Note 2)
Output-to-Output (Note 3)
Part-to-Part (Diff) (Note 3)
tJITTER
RMS Random Clock Jitter (Note 4)
Peak-to-Peak Data Dependant Jitter
(Note 5)
VINPP
Input Voltage Swing (Differential Configuration)
(Note 6)
tr, tf
Output Rise/Fall Times @ 50 MHz (20%−80%)
Q, Q
85°C
Min
Typ
600
525
250
800
750
550
375
300
500
450
600
675
75
95
125
15
30
50
0.5
20
2.0
200
800
1200
75
150
250
fin = 2.0 GHz
fin = 2.0 Gb/s
Max
Max
Min
Typ
Max
550
400
150
800
750
500
400
300
550
500
650
750
ps
75
105
125
15
30
70
80
105
150
ps
0.5
20
2.0
0.5
20
2.0
ps
200
800
1200
200
800
1200
mV
75
150
250
75
150
275
Unit
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to GND − 2.0 V. Input edge rates 150 ps (20% − 80%).
2. Pulse Skew = |tPLH − tPHL|
3. Skews are valid across specified voltage range, part-to-part skew is for a given temperature.
4. RMS Jitter with 50% Duty Cycle Input Clock Signal.
5. Peak-to-Peak Jitter with input NRZ PRBS 231−1 at 2.0 Gb/s.
6. Input voltage swing is a Single-Ended measurement operating in differential mode. The device has a DC gain of ≈ 50.
10
9.0
750
8.0
AMP
7.0
650
6.0
5.0
550
4.0
450
3.0
2.0
350
1.0
RMS JITTER
250
RMS JITTER (ps)
OUTPUT VOLTAGE AMPLITUDE
(mV)
850
0.5
1.0
1.5
2.0
0
2.5
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
D
VINPP = VIH(D) − VIL(D)
D
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 5. AC Reference Measurement
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6
MC100EP91
Application Information
and the maximum input swing of 3.0 V. Within these
conditions, the input voltage can range from VCC to GND.
Examples interfaces are illustrated below in a 50 W
environment (Z = 50 W).
All MC100EP91 inputs can accept LVPECL, LVTTL,
LVCMOS, HSTL, CML, or LVDS signal levels. The
limitations for differential input signal (LVDS, HSTL,
LVPECL, or CML) are the minimum input swing of 150 mV
VCC
Z
VCC
EP91
LVDS
Driver
VCC
Z
D
LVPECL
Driver
Z
D
Z
D
50 W
GND
VTT = VCC − 2.0 V
VEE
GND
Figure 6. Standard LVPECL Interface
VCC
GND
VCC
Z
Z
D
EP91
Z
VCC
VCC
50 W
HSTL
Driver
VEE
Figure 7. Standard LVDS Interface
VCC
50 W
D
CML
Driver
EP91
D
Z
D
50 W
EP91
100 W
D
50 W
GND
VCC
50 W
GND
GND
VEE
GND
GND
VEE
GND
Figure 8. Standard HSTL Interface
VCC
Z
VCC
VCC
EP91
LVCMOS
Driver
D
LVTTL
Driver
1.5 V
Figure 9. Standard 50 W Load CML Interface
VCC
Z
D
D
EP91
Open
D
(externally generated
reference voltage)
GND
GND
VEE
GND
Figure 10. Standard LVTTL Interface
GND
VEE
Figure 11. Standard LVCMOS Interface
(D will default to VCC/2 when left open.
A reference voltage of VCC/2 should be applied
to D input, if D is interfaced to CMOS signals)
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7
MC100EP91
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = GND − 2.0 V
Figure 12. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN24, 4x4, 0.5P
CASE 485L
ISSUE B
1 24
SCALE 2:1
D
PIN 1
REFEENCE
2X
0.15 C
2X
ÉÉÉ
ÉÉÉ
ÉÉÉ
0.15 C
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
ÇÇÇ
EXPOSED Cu
DETAIL B
0.10 C
SEATING
PLANE
L
24X
7
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
4.00 BSC
2.70
2.90
4.00 BSC
2.70
2.90
0.50 BSC
0.30
0.50
0.05
0.15
XXXXX
XXXXX
ALYWG
G
13
E2
1
24
A1
A3
GENERIC
MARKING DIAGRAM*
D2
DETAIL A
ÉÉ
ÉÉ
ÇÇ
ALTERNATE TERMINAL
CONSTRUCTIONS
C
A1
SIDE VIEW
MOLD CMPD
DETAIL B
A
A3
NOTE 4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
L1
TOP VIEW
0.08 C
L
L
A
B
DATE 05 JUN 2012
19
e
e/2
24X
b
0.10 C A B
0.05 C
BOTTOM VIEW
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT
4.30
24X
0.55
2.90
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1
4.30
2.90
0.50
PITCH
24X
0.32
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
DESCRIPTION:
98AON11783D
QFN24, 4X4, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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