MC100EPT21DR2G

MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8−lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal. The VBB output allows this EPT21 to be cap coupled in either single−ended or differential input mode. When single−ended cap coupled, VBB output is tied to the D input and D is driven for a non−inverting buffer, or VBB output is tied to the D input and D is driven for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 mF capacitor. For additional information see AND8020/D. For a single−ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single−ended direct connection or port to another device. http://onsemi.com MARKING DIAGRAMS* 8 SO−8 D SUFFIX CASE 751 8 1 1 KPT21 ALYW G 8 TSSOP−8 DT SUFFIX CASE 948R 8 1 1 KA21 ALYWG G Features • • • • • • • • 1.4 ns Typical Propagation Delay Maximum Frequency > 275 MHz Typical DFN8 MN SUFFIX CASE 506AA LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs 1 3RMG G 24 mA TTL outputs A L Y W M G Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V The 100 Series Contains Temperature Compensation VBB Output These Devices are Pb−Free and are RoHS Compliant = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2012 September, 2012 − Rev. 22 1 Publication Order Number: MC100EPT21/D MC100EPT21 Table 1. PIN DESCRIPTION NC D D VBB 1 8 LVTTL 2 3 7 6 LVPECL 4 5 VCC FUNCTION PIN Q NC Q LVTTL/LVCMOS Output D*, D* Differential LVPECL/LVDS/CML Input VCC Positive Supply VBB Output Reference Voltage GND Ground NC No Connect EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. GND * Pin will default to 1/2 of VCC when left open. Figure 1. Logic Diagram and 8−Lead Pinout (Top View) Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor D 50 kW Internal Input Pulldown Resistor D 50 kW D, D 50 kW Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model > 1.5 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC−8 TSSOP−8 DFN8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 81 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC100EPT21 Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Rating Unit 3.8 V 0 to 3.8 V ± 0.5 mA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SO−8 SO−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SO−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder < 2 to 3 sec @ 248°C