MC100EPT24DTG

MC100EPT24 3.3V LVTTL/LVCMOS to Differential LVECL Translator Description Features • • • • • • • 350 ps Typical Propagation Delay Maximum Input Clock Frequency = > 1.0 GHz Typical The 100 Series Contains Temperature Compensation Operating Range: VCC = 3.0 V to 3.6 V; VEE = −3.6 V to −3.0 V; GND = 0 V PNP LVTTL Input for Minimal Loading Q Output will Default HIGH with Input Open These Devices are Pb-Free, Halogen Free and are RoHS Compliant www.onsemi.com 8 8 1 1 SOIC−8 NB TSSOP−8 DFN8 D SUFFIX DT SUFFIX MN SUFFIX CASE 751−07 CASE 948R−02 CASE 506AA MARKING DIAGRAMS* 8 1 8 KPT24 ALYW G 1 SOIC−8 NB A L Y W M G 3U MG G The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline 8-lead package and the single gate of the EPT24 makes it ideal for those applications where space, performance, and low power are at a premium. KA24 ALYWG G 1 TSSOP−8 4 DFN8 = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping† MC100EPT24DG SOIC−8 NB (Pb-Free) 98 Units / Tube MC100EPT24DR2G SOIC−8 NB (Pb-Free) 2500 Tape & Reel MC100EPT24DTG TSSOP−8 (Pb-Free) 100 Units / Tube MC100EPT24MNR4G DFN8 (Pb-Free) 1000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 August, 2016 − Rev. 10 1 Publication Order Number: MC100EPT24/D MC100EPT24 Table 1. PIN DESCRIPTION VEE D 1 2 8 LVTTL VCC 7 PIN Q LVECL NC NC 3 Q 6 4 5 FUNCTION Q, Q Differential LVECL Outputs D LVTTL Input VCC Positive Supply GND Ground VEE Negative Supply NC No Connect EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. GND Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC−8 NB TSSOP−8 DFN8 Flammability Rating Pb-Free Pkg Level 1 Level 3 Level 1 Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 181 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2 MC100EPT24 Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC Positive Power Supply Parameter GND = 0 V Condition 1 VEE = −3.3V Condition 2 3.8 V VEE Negative Power Supply GND = 0 V VCC = 3.3V −3.8 V VIN Input Voltage GND = 0 V VI ≤ VCC 0 to VCC V Iout Output Current Continuous Surge 50 100 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 50 lfpm SOIC−8 NB SOIC−8 NB 190 130 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 50 lfpm TSSOP−8 TSSOP−8 185 140 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 50 lfpm DFN8 DFN8 129 84 °C/W Tsol Wave Solder (Pb-Free) 265 °C qJC Thermal Resistance (Junction-to-Case) 35 to 40 °C/W (Note 1) DFN8 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) Table 4. LVTTL INPUT DC CHARACTERISTICS (VCC = 3.3 V, VEE = −3.6 V to −3.0 V, GND = 0.0 V; TA = −40°C to 85°C) Symbol Characteristic Condition Min Typ Max Unit IIH Input HIGH Current VIN = 2.7 V 20 mA IIHH Input HIGH Current HIGH Voltage VCC = VIN = 3.8 V 100 mA IIL Input LOW Current VIN = 0.5 V −0.6 mA VIK Input Clamp Voltage IIN = −18 mA −1.0 V VIH Input HIGH Voltage VIL Input LOW Voltage 2.0 V 0.8 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 50 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 5. NECL OUTPUT DC CHARACTERISTICS (VCC = 3.3 V, VEE = −3.3 V, GND = 0.0 V (Note 1)) −40°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage (Note 2) -1145 −1020 -895 -1145 −1020 -895 -1145 −1030 -895 mV VOL Output LOW Voltage (Note 2) -1945 −1820 -1695 -1945 −1820 -1695 -1945 −1820 -1695 mV ICC Positive Power Supply Current 2.0 4.0 2.0 4.0 2.0 4.0 mA IEE Negative Power Supply Current 30 38 30 38 30 38 mA Symbol Characteristic 20 20 20 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 50 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Output levels will vary 1:1 with GND. VEE can vary ± 0.3 V. 2. Outputs are terminated through a 50 W resistor to GND − 2 V. www.onsemi.com 3 MC100EPT24 Table 6. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 1)) −40°C Characteristic Symbol fmax Maximum Input Clock Frequency (Figure 2) tPLH, tPHL Propagation Delay to Output Differential (Note 2) tJITTER tr tf Min 25°C Max Min >1 300 RMS Random Clock Jitter (Figure 2) Output Rise/Fall Times (20% − 80%) @ 50 MHz Typ Q, Q 70 Typ 85°C Max Min Typ >1 500 800 0.2 1 530 800 0.2