MC100EPT25MNR4G

MC100EPT25 -3.3V / -5V Differential ECL to +3.3V LVTTL Translator Description The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal. The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a inverting buffer or the D input for a non-inverting buffer. If used, the VBB pin should be bypassed to ground with at least a 0.01 mF capacitor. www.onsemi.com 8 8 1 1 SOIC−8 NB D SUFFIX CASE 751−07 TSSOP−8 DT SUFFIX CASE 948R−02 DFN−8 MN SUFFIX CASE 506AA Features • 1.1 ns Typical Propagation Delay • Maximum Frequency > 275 MHz Typical • Operating Range: 8 8 ♦ VCC = 3.0 V to 3.6 V; VEE = −5.5 V to −3.0 V; GND = 0 V 24 mA TTL Outputs Q Output Will Default LOW with Inputs Open or at VEE VBB Output Open Input Default State Safety Clamp on Inputs These Devices are Pb-Free, Halogen Free and are RoHS Compliant 1 KPT25 ALYW G 1 A L Y W M G 3V MG G • • • • • • MARKING DIAGRAMS* KA25 ALYWG G 1 4 = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Package Shipping† MC100EPT25DG SOIC−8 NB (Pb-Free) 98 Units/Tube MC100EPT25DR2G SOIC−8 NB (Pb-Free) 2500/Tape & Reel MC100EPT25DTG TSSOP−8 (Pb-Free) 100 Units/Tube MC100EPT25DTR2G TSSOP−8 (Pb-Free) 2500/Tape & Reel MC100EPT25MNR4G DFN−8 (Pb-Free) 1000/Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 August, 2016 − Rev. 17 1 Publication Order Number: MC100EPT25/D MC100EPT25 Table 1. PIN DESCRIPTION VEE D D 1 8 LVTTL 2 3 7 6 VCC PIN Q NC LVECL/ECL VBB 4 5 GND Figure 1. 8-Lead Pinout (Top View) and Logic Diagram FUNCTION Q LVTTL Output D*, D* Differential ECL Input Pair VCC Positive Supply VBB Output Reference Voltage GND Ground VEE Negative Supply NC No Connect EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. * Pins will default LOW when left open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC−8 NB TSSOP−8 DFN−8 Pb-Free Pkg Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in Transistor Count 111 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2 MC100EPT25 Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC Positive Power Supply Parameter GND = 0 V Condition 1 VEE = −5.0 V Condition 2 3.8 V VEE Negative Power Supply GND = 0 V VCC = +3.3 V −6 V VIN Input Voltage GND = 0 V 0 to VEE V IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−8 NB 190 130 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm TSSOP−8 185 140 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm DFN−8 129 84 °C/W Tsol Wave Solder (Pb-Free)