MC100LVE111FN

MC100LVE111 3.3V ECL 1:9 Differential Clock Driver The MC100LVE111 is a low skew 1−to−9 differential driver, designed with clock distribution in mind. The MC100LVE111’s function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input, which can be either differential or single−ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. The LVE111 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50 W, even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10−20 ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. The MC100LVE111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE111 to be used for high performance clock distribution in +3.3 V systems. Designers can take advantage of the LVE111’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination offers the lowest power by taking advantage of the 1.2 V supply as a terminating voltage. For more information on using PECL, designers should refer to Application Note AN1406/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. http://onsemi.com MARKING DIAGRAM* 1 28 PLCC−28 FN SUFFIX CASE 776 A WL YY WW G MC100LVE111G AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Features • • • • • • • • 200 ps Part−to−Part Skew 50 ps Output−to−Output Skew The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors Q Output will Default LOW with Inputs Open or at VEE These are Pb−Free Devices* © Semiconductor Components Industries, LLC, 2013 April, 2013 − Rev. 8 1 Publication Order Number: MC100LVE111/D MC100LVE111 Q0 Q0 Q1 VCCO Q1 Q2 Q2 25 24 23 20 19 22 21 VEE 26 18 Q3 NC 27 17 Q3 IN 28 16 Q4 15 VCCO VCC 28−Lead PLCC (Top View) 1 IN 2 14 Q4 VBB 3 13 Q5 NC 4 12 Q5 5 6 7 8 9 Q8 Q8 Q7 VCCO Q7 10 11 Q6 Q6 Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Pinout (Top View) and Logic Diagram Q0 Table 1. PIN DESCRIPTION Q0 Pin Q1 IN, IN Q0, Q0−Q8, Q8 VBB VCC, VCCO VEE NC Q1 Q2 Q2 Q3 Q3 IN Q4 IN Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 VBB Figure 2. Logic Symbol http://onsemi.com 2 Function ECL Differential Input Pair ECL Differential Outputs Reference Voltage Output Positive Supply Negative Supply No Connect MC100LVE111 Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model > 2 kV > 200 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Level 3 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 250 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm PLCC−28 PLCC−28 63.5 43.5 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board PLCC−28 22 to 26 ± 5% °C/W Tsol Wave Solder 1.5 400 350 650 700 440 390 630 680 445 395 0.2 Unit GHz 635 685 50 200 1.5 50 250 0.2 Typ ps 50 200 ps