MC100LVEL11
3.3V ECL 1:2
Differential Fanout Buffer
Description
The MC100LVEL11 is a differential 1:2 fanout buffer. The device is
functionally similar to the E111 device but with higher performance
capabilities. Having within-device skews and output transition times
significantly improved over the E111, the LVEL11 is ideally suited for
those applications which require the ultimate in AC performance.
The differential inputs of the LVEL11 employ clamping circuitry to
maintain stability under open input conditions. If the inputs are left
open (pulled to VEE) the Q outputs will go LOW.
Features
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www.onsemi.com
MARKING
DIAGRAMS*
8
8
1
KVL11
ALYW
G
SOIC−8
D SUFFIX
CASE 751
330 ps Propagation Delay
5 ps Skew Between Outputs
High Bandwidth Output Transitions
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −3.8 V
Internal Input Pulldown Resistors on D,
Pullup and Pulldown Resistors on D
Q Output will Default LOW with Inputs Open or at VEE
These Devices are Pb−Free and are RoHS Compliant
1
8
8
1
KV11
ALYWG
G
TSSOP−8
DT SUFFIX
CASE 948R
1
1
3ZMG
G
1
DFN8
MN SUFFIX
CASE 506AA
Q0
1
8
VCC
Q0
2
7
D
Q1
3
6
D
A
L
Y
W
M
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q1
4
5
VEE
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 1. Logic Diagram and Pinout Assignment
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 13
1
Publication Order Number:
MC100LVEL11/D
MC100LVEL11
Table 1. PIN DESCRIPTION
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pin
Function
Q0, Q0; Q1, Q1
ECL Data Outputs
D, D
ECL Data Inputs
VCC
Positive Supply
VEE
Negative Supply
EP
(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative
supply (GND) or leave unconnected, floating open.
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
75 kW
ESD Protection
Human Body Model
Machine Model
Charge Device Model
> 4 KV
> 400 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
63
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Rating
Units
VCC
Symbol
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +95
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lpfm
500 lpfm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lpfm
500 lpfm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
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