MC100LVEL29DWG

MC100LVEL29 3.3 V ECL Dual Differential Data and Clock D Flip‐Flop with Set and Reset Description The MC100LVEL29 is a dual master-slave flip-flop. The device features fully differential Data and Clock inputs as well as outputs. The MC100LVEL29 is pin and functionally equivalent to the MC100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE and the D input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up. Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • • • • • • • • • • 1100 MHz Flip-Flop Toggle Frequency ESD Protection: > 2 kV Human Body Model 580 ps Typical Propagation Delays The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity: Level 3 (Pb-Free) (For Additional Information, see Application Note AND8003/D) Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 313 Devices • • These Devices are Pb-Free, Halogen Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 7 1 www.onsemi.com SOIC−20 WB DW SUFFIX CASE 751D−05 MARKING DIAGRAM* 20 100LVEL29 AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device MC100LVEL29DWG Package Shipping† SOIC−20 WB (Pb-Free) 38 Units / Tube MC100LVEL29DWR2G SOIC−20 WB 1000 Tape & Reel (Pb-Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: MC100LVEL29/D MC100LVEL29 R0 VCC Q0 Q0 S0 S1 VCC Q1 Q1 VEE 20 19 18 17 16 15 14 13 12 11 Q Q R S D 1 D0 CLK 2 3 Q Q D CLK S 4 5 6 D0 CLK0 CLK0 VBB D1 R 7 8 9 10 D1 CLK1 CLK1 R1 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View) Table 1. PIN DESCRIPTION Table 2. TRUTH TABLE PIN FUNCTION D0, D0; D1, D1 R0, R1 CLK0, CLK0 CLK1, CLK1 S0, S1 Q0, Q0; Q1, Q1 VBB VCC VEE ECL Differential Data Inputs ECL Reset Inputs ECL Differential Clock Inputs ECL Differential Clock Inputs ECL Set Inputs ECL Differential Data Outputs Reference Voltage Output Positive Supply Negative Supply R S D CLK Q Q L L H L H L L L H H L H X X X Z Z X X X L H L H Undef H L H L Undef Z = LOW to HIGH Transition X = Don’t Care Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V Iout Output Current Continuous Surge 50 100 mA IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm SOIC−20 WB SOIC−20 WB 90 60 °C/W qJC Thermal Resistance (Junction-to-Case) Standard Board SOIC−20 WB 30 to 35 °C/W Tsol Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C VI ≤ VCC VI ≥ VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2 MC100LVEL29 Table 4. LVPECL DC CHARACTERISTICS (VCC = 3.3 V; VEE = 0.0 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 35 50 Min 85°C Typ Max 35 50 Min Typ Max Unit 35 50 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV VOL Output LOW Voltage (Note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV VIH Input HIGH Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single-Ended) 1490 1825 1490 1825 1490 1825 mV VBB Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3) Vpp < 500 mV Vpp ≥ 500 mV IIH Input HIGH Current IIL Input LOW Current Dn Dn V 1.3 1.5 2.9 2.9 1.2 1.4 2.9 2.9 150 0.5 −300 1.2 1.4 2.9 2.9 150 0.5 −300 150 mA mA 0.5 −300 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 5. LVNECL DC CHARACTERISTICS (VCC = 0.0 V; VEE = −3.3 V (Note 1)) −40°C Symbol Characteristic Min 25°C Typ Max 35 50 Min 85°C Typ Max 35 50 Min Typ Max Unit 35 50 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 2) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single-Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single-Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3) Vpp < 500 mV Vpp ≥ 500 mV IIH Input HIGH Current IIL Input LOW Current Dn Dn V −2.0 −1.8 −0.4 −0.4 −2.1 −1.9 150 0.5 −300 −0.4 −0.4 −2.1 −1.9 150 0.5 −300 −0.4 −0.4 150 0.5 −300 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. www.onsemi.com 3 MC100LVEL29 Table 6. AC CHARACTERISTICS (VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 1)) −40°C Symbol Characteristic Min Typ 25°C Max Min 1.1 Typ 85°C Max Typ Max Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output tS tH Setup Time Hold Time 0 100 0 100 0 100 ps tRR Set/Reset Recovery 100 100 100 ps tPW Minimum Pulse Width CLK, Set, Reset 400 400 400 tJITTER Cycle-to-Cycle Jitter VPP Input Swing (Note 2) 150 1000 150 1000 150 1000 mV tr tf Output Rise/Fall Times Q (20%−80%) 280 550 280 550 280 550 ps 480 480 680 700 1.1 Unit fmax CLK S, R 1.1 Min 500 500 TBD 580 700 720 GHz 520 520 TBD 720 740 ps ps TBD ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. VEE can vary ±0.3 V. 2. VPP(min) is the minimum input swing for which AC parameters guaranteed. Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices) Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 4 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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